hardware.h

东南大学开发的ARM7芯片SEP4020的IIS测试代码

#ifndef _HARDWARE_H
#define _HARDWARE_H

#include 	"hardware_reg.h"

//***************************************
//PMU module clk
//*************************************
#define	CLK_INTC	(1 << 14)
#define	CLK_PMU		(1 << 13)
#define	CLK_RTC		(1 << 12)
#define	CLK_GPT		(1 << 11)
#define	CLK_SPI		(1 << 10)
#define	CLK_UART0	(1 << 9)
#define	CLK_UART1	(1 << 8)
#define	CLK_GPIO	(1 << 7)
#define	CLK_MMC		(1 << 6)
#define	CLK_AC97	(1 << 5)
#define	CLK_DMA		(1 << 4)
#define	CLK_MMA		(1 << 3)
#define	CLK_LCDC	(1 << 2)
#define	CLK_ESRAM	(1 << 1)
#define	CLK_EMI		(1)


/*************************************
	macros for INTC
*************************************/

/*interrupt resources */


        
#define		INT_DMA					30	                
#define		INT_EMI					30              
#define		INT_GPT1				29 
#define		INT_GPT2				28 
#define		INT_GPT3				27
#define		INT_WD					26                  
#define		INT_SSI					17              
#define 	INT_UART0				24              
#define		INT_UART1				23              
#define		INT_UART2				22              
#define		INT_RESER				21              
	    
#define		INT_EXT14				15              
#define		INT_EXT13				14				
#define		INT_EXT12				13              
#define		INT_EXT11				12              
#define		INT_EXT10				11              
#define		INT_EXT9 				10              
#define		INT_EXT8 				9               
#define		INT_EXT7 				8               
#define		INT_EXT6 				7               
#define		INT_EXT5 				6               
#define		INT_EXT4 				5               
#define		INT_EXT3 				4               
#define		INT_EXT2 				3               
#define		INT_EXT1 				2               
#define		INT_EXT0				1
#define		INT_NULL				0


/****************************************
	macros for GPT
****************************************/
#define   GPT_EN            0X01
#define   GPT_IEN           0X00
#define   GPT_MASK_INT      0X04
#define   GPT_REBOOT_MODE   0X02
#define   GPT_FREE_MODE     0X00
#define   GPT_CAP_POSEDGE   0X0A
#define   GPT_CAP_NEGEDGE   0X12
#define   GPT_CAP_BOTHEDGE  0X1A
#define   GPT_WSVCE_VAL     0xAAAA


/*****************************************
	macros for UART
*****************************************/
#define 		UART1_IER_MODEM	0X01
#define		UART1_IER_RLS		0X02
#define		UART1_IER_THR		0X04
#define		UART1_IER_RDA		0X08

#define		UART1_IIR_MODEM	0X00
#define		UART1_IIR_THR		0X01
#define		UART1_IIR_RDA		0X02
#define		UART1_IIR_RLS		0X03
#define		UART1_IIR_TMO		0X06

#define		UART1_LCR_DIV		0X80


/*****************************************
	macros for EMI
*****************************************/


#define	EMIADDR_CSGBAB_val		0x24002000          		//base adress of csa:0x20000000
                                                            //base adress of csb:0x24000000(none now)
													 
#define	EMIADDR_CSGBCD_val		0x2c002800     		    	//base adress of csc:0x28000000
       					                					//base adress of csc:0x2C000000(none now)   
       					                	
#define	EMIADDR_CSGBEF_val		0x34003000    				//base adress of csc:0x30000000
                                                            //base adress of csc:0x34000000 

#define	EMIADDR_SMCONF_val	   	0x9b010333  	 			//write cycle: 3     read cycle:3
									//csa:32_bit sram
									//csb:none
									//csc:32_bit sram
									//csd:none
									//cde:16_bit sdram
									//cdf:32 bit sdram


#define EMIADDR_SDCONF1_val		0x0110a077			//12 row * 9 column
													//non_Interleaved Address Mode
													//2 row every flesh clock edge
													//hang_up after 64 clocks after last access
													//CAS = 2 clock
													//3 clock between precharge and active command
													//4 clock between active and write/read command toward the same bank
													//7 clock between refresh command and later commands
									
#define EMIADDR_SDCONF2_val		0x80001860			//Initialize sdam;
													//refresh cyccle:64*0x186 clocks
													//refresh all rows once a time


#define EMIADDR_NANDCONF_VAL    0x02200aaa          //4 address 0x1aa3aa      
                                                    //Trr 10 cycles
                                                    //Tclh 2 cycles
                                                    //Talh 2 cycles
                                                    //Twh  3 cycles
                                                    //Read_width 10 cycles
                                                    //Writ_width 10 cycles

 

/****************************************
	macros  for write and read registers
****************************************/
#define write_reg(reg, data) \
	*(RP)reg = data

#define read_reg(reg) \
	*(RP)reg



#endif