📄 s3c44b0x.s
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;// <o1.6..7> PG3 <0=> Input <1=> Output <2=> nRTS0 <3=> EINT3
;// <o1.8..9> PG4 <0=> Input <1=> Output <2=> IISCLK <3=> EINT4
;// <o1.10..11> PG5 <0=> Input <1=> Output <2=> IISDI <3=> EINT5
;// <o1.12..13> PG6 <0=> Input <1=> Output <2=> IISDO <3=> EINT6
;// <o1.14..15> PG7 <0=> Input <1=> Output <2=> IISLRCK <3=> EINT7
;// <h> Pull-up Resistors
;// <o2.0> PG0 Pull-up <0=> Enabled <1=> Disabled
;// <o2.1> PG1 Pull-up <0=> Enabled <1=> Disabled
;// <o2.2> PG2 Pull-up <0=> Enabled <1=> Disabled
;// <o2.3> PG3 Pull-up <0=> Enabled <1=> Disabled
;// <o2.4> PG4 Pull-up <0=> Enabled <1=> Disabled
;// <o2.5> PG5 Pull-up <0=> Enabled <1=> Disabled
;// <o2.6> PG6 Pull-up <0=> Enabled <1=> Disabled
;// <o2.7> PG7 Pull-up <0=> Enabled <1=> Disabled
;// </h>
;// </e>
PIOG_SETUP EQU 1
PCONG_Val EQU 0x00000000
PUPG_Val EQU 0x00000000
;// <e> Special Pull-up
;// <o1.0> SPUCR0: DATA[7:0] Pull-up Resistor
;// <0=> Enabled <1=> Disabled
;// <o1.1> SPUCR1: DATA[15:8] Pull-up Resistor
;// <0=> Enabled <1=> Disabled
;// <o1.2> HZ@STOP
;// <0=> Prevoius state of PAD
;// <1=> HZ @ Stop
;// </e>
PSPU_SETUP EQU 1
SPUCR_Val EQU 0x00000004
;// </e>
PRESERVE8
; Area Definition and Entry Point
; Startup Code must be linked first at Address at which it expects to run.
AREA RESET, CODE, READONLY
ARM
; Exception Vectors
; Mapped to Address 0.
; Absolute addressing mode must be used.
; Dummy Handlers are implemented as infinite loops which can be modified.
Vectors LDR PC, Reset_Addr
LDR PC, Undef_Addr
LDR PC, SWI_Addr
LDR PC, PAbt_Addr
LDR PC, DAbt_Addr
NOP ; Reserved Vector
LDR PC, IRQ_Addr
LDR PC, FIQ_Addr
IF VIM_SETUP <> 0
MACRO
$IRQ_Vector IRQ_Vec $Num, $HandlerName
$IRQ_Vector IF (VIM_CFG:AND:(1:SHL:$Num)) <> 0
IMPORT $HandlerName
LDR PC, =$HandlerName
ELSE
B .
ENDIF
MEND
IRQ_Vec 25, HandlerEINT0
IRQ_Vec 24, HandlerEINT1
IRQ_Vec 23, HandlerEINT2
IRQ_Vec 22, HandlerEINT3
IRQ_Vec 21, HandlerINT4567
IRQ_Vec 20, HandlerTICK
B .
B .
IRQ_Vec 19, HandlerZDMA0
IRQ_Vec 18, HandlerZDMA1
IRQ_Vec 17, HandlerBDMA0
IRQ_Vec 16, HandlerBDMA1
IRQ_Vec 15, HandlerWDT
IRQ_Vec 14, HandlerUERR01
B .
B .
IRQ_Vec 13, HandlerTIMER0
IRQ_Vec 12, HandlerTIMER1
IRQ_Vec 11, HandlerTIMER2
IRQ_Vec 10, HandlerTIMER3
IRQ_Vec 9, HandlerTIMER4
IRQ_Vec 8, HandlerTIMER5
B .
B .
IRQ_Vec 7, HandlerURXD0
IRQ_Vec 6, HandlerURXD1
IRQ_Vec 5, HandlerIIC
IRQ_Vec 4, HandlerSIO
IRQ_Vec 3, HandlerUTXD0
IRQ_Vec 2, HandlerUTXD1
B .
B .
IRQ_Vec 1, HandlerRTC
B .
B .
B .
B .
B .
B .
B .
IRQ_Vec 0, HandlerADC
ENDIF
Reset_Addr DCD Reset_Handler
Undef_Addr DCD Undef_Handler
SWI_Addr DCD SWI_Handler
PAbt_Addr DCD PAbt_Handler
DAbt_Addr DCD DAbt_Handler
DCD 0 ; Reserved Address
IRQ_Addr DCD IRQ_Handler
FIQ_Addr DCD FIQ_Handler
Undef_Handler B Undef_Handler
SWI_Handler B SWI_Handler
PAbt_Handler B PAbt_Handler
DAbt_Handler B DAbt_Handler
IRQ_Handler B IRQ_Handler
FIQ_Handler B FIQ_Handler
; CPU Wrapper and Bus Priorities Configuration
IF SYS_SETUP <> 0
SYS_CFG
DCD CPUW_BASE
DCD BUSP_BASE
DCD SYSCFG_Val
DCD NCACHBE0_Val
DCD NCACHBE1_Val
DCD SBUSCON_Val
ENDIF
; Memory Controller Configuration
IF MC_SETUP <> 0
MC_CFG
DCD BWSCON_Val
DCD BANKCON0_Val
DCD BANKCON1_Val
DCD BANKCON2_Val
DCD BANKCON3_Val
DCD BANKCON4_Val
DCD BANKCON5_Val
DCD BANKCON6_Val
DCD BANKCON7_Val
DCD REFRESH_Val
DCD BANKSIZE_Val
DCD MRSRB6_Val
DCD MRSRB7_Val
ENDIF
; Clock Management Configuration
IF CLK_SETUP <> 0
CLK_CFG
DCD CLK_BASE
DCD PLLCON_Val
DCD CLKCON_Val
DCD CLKSLOW_Val
DCD LOCKTIME_Val
ENDIF
; I/O Configuration
IF PIO_SETUP <> 0
PIO_CFG
DCD PCONA_Val
DCD PCONB_Val
DCD PCONC_Val
DCD PCOND_Val
DCD PCONE_Val
DCD PCONF_Val
DCD PCONG_Val
DCD PUPC_Val
DCD PUPD_Val
DCD PUPE_Val
DCD PUPF_Val
DCD PUPG_Val
DCD SPUCR_Val
ENDIF
; Reset Handler
EXPORT Reset_Handler
Reset_Handler
IF SYS_SETUP <> 0
ADR R8, SYS_CFG
LDMIA R8, {R0-R5}
STMIA R0, {R2-R4}
STR R5, [R1]
ENDIF
IF MC_SETUP <> 0
ADR R14, MC_CFG
LDMIA R14, {R0-R12}
LDR R14, =MC_BASE
STMIA R14, {R0-R12}
ENDIF
IF CLK_SETUP <> 0
ADR R8, CLK_CFG
LDMIA R8, {R0-R4}
STR R4, [R0, #LOCKTIME_OFS]
STR R1, [R0, #PLLCON_OFS]
STR R3, [R0, #CLKSLOW_OFS]
STR R2, [R0, #CLKCON_OFS]
ENDIF
IF WT_SETUP <> 0
LDR R0, =WT_BASE
LDR R1, =WTCON_Val
LDR R2, =WTDAT_Val
STR R2, [R0, #WTCNT_OFS]
STR R2, [R0, #WTDAT_OFS]
STR R1, [R0, #WTCON_OFS]
ENDIF
IF PIO_SETUP <> 0
ADR R14, PIO_CFG
LDMIA R14, {R0-R12}
LDR R14, =PIO_BASE
IF PIOA_SETUP <> 0
STR R0, [R14, #PCONA_OFS]
ENDIF
IF PIOB_SETUP <> 0
STR R1, [R14, #PCONB_OFS]
ENDIF
IF PIOC_SETUP <> 0
STR R2, [R14, #PCONC_OFS]
STR R7, [R14, #PUPC_OFS]
ENDIF
IF PIOD_SETUP <> 0
STR R3, [R14, #PCOND_OFS]
STR R8, [R14, #PUPD_OFS]
ENDIF
IF PIOE_SETUP <> 0
STR R4, [R14, #PCONE_OFS]
STR R9, [R14, #PUPE_OFS]
ENDIF
IF PIOF_SETUP <> 0
STR R5, [R14, #PCONF_OFS]
STR R10,[R14, #PUPF_OFS]
ENDIF
IF PIOG_SETUP <> 0
STR R6, [R14, #PCONG_OFS]
STR R11,[R14, #PUPG_OFS]
ENDIF
IF PSPU_SETUP <> 0
STR R12,[R14, #SPUCR_OFS]
ENDIF
ENDIF
; Setup Stack for each mode
LDR R0, =Stack_Top
; Enter Undefined Instruction Mode and set its Stack Pointer
MSR CPSR_c, #Mode_UND:OR:I_Bit:OR:F_Bit
MOV SP, R0
SUB R0, R0, #UND_Stack_Size
; Enter Abort Mode and set its Stack Pointer
MSR CPSR_c, #Mode_ABT:OR:I_Bit:OR:F_Bit
MOV SP, R0
SUB R0, R0, #ABT_Stack_Size
; Enter FIQ Mode and set its Stack Pointer
MSR CPSR_c, #Mode_FIQ:OR:I_Bit:OR:F_Bit
MOV SP, R0
SUB R0, R0, #FIQ_Stack_Size
; Enter IRQ Mode and set its Stack Pointer
MSR CPSR_c, #Mode_IRQ:OR:I_Bit:OR:F_Bit
MOV SP, R0
SUB R0, R0, #IRQ_Stack_Size
; Enter Supervisor Mode and set its Stack Pointer
MSR CPSR_c, #Mode_SVC:OR:I_Bit:OR:F_Bit
MOV SP, R0
SUB R0, R0, #SVC_Stack_Size
; Enter User Mode and set its Stack Pointer
MSR CPSR_c, #Mode_USR
IF :DEF:__MICROLIB
EXPORT __initial_sp
ELSE
MOV SP, R0
SUB SL, SP, #USR_Stack_Size
ENDIF
; Enter the C code
IMPORT __main
LDR R0, =__main
BX R0
IF :DEF:__MICROLIB
EXPORT __heap_base
EXPORT __heap_limit
ELSE
; User Initial Stack & Heap
AREA |.text|, CODE, READONLY
IMPORT __use_two_region_memory
EXPORT __user_initial_stackheap
__user_initial_stackheap
LDR R0, = Heap_Mem
LDR R1, =(Stack_Mem + USR_Stack_Size)
LDR R2, = (Heap_Mem + Heap_Size)
LDR R3, = Stack_Mem
BX LR
ENDIF
END
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