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## ## -------------------------------------------------------------## Copyright 2004-2008 Synopsys, Inc.## All Rights Reserved Worldwide## ## Licensed under the Apache License, Version 2.0 (the## "License"); you may not use this file except in## compliance with the License. You may obtain a copy of## the License at## ## http://www.apache.org/licenses/LICENSE-2.0## ## Unless required by applicable law or agreed to in## writing, software distributed under the License is## distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR## CONDITIONS OF ANY KIND, either express or implied. See## the License for the specific language governing## permissions and limitations under the License.## -------------------------------------------------------------## VMM = +incdir+$(VMM_HOME)/sv#VMM = -ntb_opts rvmTESTDIR = $(VMM_HOME)/sv/RAL/testsWB = $(VMM_HOME)/sv/examples/std_lib/wishboneMII = $(VMM_HOME)/sv/examples/std_lib/ethernetTB = tb_top.sv $(VMM) +incdir+$(WB)+$(MII)DUTDIR = $(VMM_HOME)/shared/examples/oc_ethernetDUT = -F $(DUTDIR)/rtl/rtl_file_list.lst +incdir+$(DUTDIR)/rtlOPTS =VCS = vcs -R -sverilog -ntb_opts dtm +verilog1995ext+.v -extinclude \ +warn=noBCNACMBP $(OPTS)all: tests tests: hw_reset \ bit_bash \ mem_walk%: ral_oc_ethernet.sv $(TESTDIR)/%.sv $(VCS) timescale.v $(TESTDIR)/$*.sv $(TB) $(DUT) \ +define+OC_ETHERNET_TOP_PATH=tb_top.dut \ +define+SINGLE_RAM_VARIABLEreport: urg -dir simv.vdb urg -show text -dir simv.vdbral_oc_ethernet.sv: $(DUTDIR)/oc_ethernet.ralf ralgen -b -l sv -t oc_ethernet $(DUTDIR)/oc_ethernet.ralfclean: rm -rf *~ *.key *.vro *.xml *.log csrc simv* *.h *.db *.html \ result.* urgReport ral_oc*.sv
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