📄 cstartup_sam7.lst
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##############################################################################
# #
# IAR ARM ANSI C/C++ Compiler V4.41A/W32 EVALUATION 29/Apr/2007 11:07:44 #
# Copyright 1999-2005 IAR Systems. All rights reserved. #
# #
# Cpu mode = interwork #
# Endian = little #
# Stack alignment = 4 #
# Source file = E:\arm\at91sam7x\software\at91sam7x256_iar\AT91_SAM7 #
# X256-IAR\AT91SAM7X256-BasicEMAC_IAR4_30-1_2\AT91SAM7 #
# X256-BasicEmac\compil\SrcIAR\Cstartup_SAM7.c #
# Command line = E:\arm\at91sam7x\software\at91sam7x256_iar\AT91_SAM7 #
# X256-IAR\AT91SAM7X256-BasicEMAC_IAR4_30-1_2\AT91SAM7 #
# X256-BasicEmac\compil\SrcIAR\Cstartup_SAM7.c -D ESS #
# -lC E:\arm\at91sam7x\software\at91sam7x256_iar\AT91_ #
# SAM7X256-IAR\AT91SAM7X256-BasicEMAC_IAR4_30-1_2\AT91 #
# SAM7X256-BasicEmac\compil\RAM_Debug\List\ -o #
# E:\arm\at91sam7x\software\at91sam7x256_iar\AT91_SAM7 #
# X256-IAR\AT91SAM7X256-BasicEMAC_IAR4_30-1_2\AT91SAM7 #
# X256-BasicEmac\compil\RAM_Debug\Obj\ -z2 --no_cse #
# --no_unroll --no_inline --no_code_motion --no_tbaa #
# --no_clustering --no_scheduling --debug --cpu_mode #
# thumb --endian little --cpu ARM7TDMI --stack_align #
# 4 --interwork -e --fpu None --dlib_config #
# "D:\Program Files\IAR Systems\Embedded Workbench #
# 4.0 Evaluation\ARM\LIB\dl4tptinl8n.h" -I #
# E:\arm\at91sam7x\software\at91sam7x256_iar\AT91_SAM7 #
# X256-IAR\AT91SAM7X256-BasicEMAC_IAR4_30-1_2\AT91SAM7 #
# X256-BasicEmac\compil\srciar\ -I #
# E:\arm\at91sam7x\software\at91sam7x256_iar\AT91_SAM7 #
# X256-IAR\AT91SAM7X256-BasicEMAC_IAR4_30-1_2\AT91SAM7 #
# X256-BasicEmac\compil\..\..\ -I "D:\Program #
# Files\IAR Systems\Embedded Workbench 4.0 #
# Evaluation\ARM\INC\" #
# List file = E:\arm\at91sam7x\software\at91sam7x256_iar\AT91_SAM7 #
# X256-IAR\AT91SAM7X256-BasicEMAC_IAR4_30-1_2\AT91SAM7 #
# X256-BasicEmac\compil\RAM_Debug\List\Cstartup_SAM7.l #
# st #
# Object file = E:\arm\at91sam7x\software\at91sam7x256_iar\AT91_SAM7 #
# X256-IAR\AT91SAM7X256-BasicEMAC_IAR4_30-1_2\AT91SAM7 #
# X256-BasicEmac\compil\RAM_Debug\Obj\Cstartup_SAM7.r7 #
# 9 #
# #
# #
##############################################################################
E:\arm\at91sam7x\software\at91sam7x256_iar\AT91_SAM7X256-IAR\AT91SAM7X256-BasicEMAC_IAR4_30-1_2\AT91SAM7X256-BasicEmac\compil\SrcIAR\Cstartup_SAM7.c
1 //*----------------------------------------------------------------------------
2 //* ATMEL Microcontroller Software Support - ROUSSET -
3 //*----------------------------------------------------------------------------
4 //* The software is delivered "AS IS" without warranty or condition of any
5 //* kind, either express, implied or statutory. This includes without
6 //* limitation any warranty or condition with respect to merchantability or
7 //* fitness for any particular purpose, or against the infringements of
8 //* intellectual property rights of others.
9 //*----------------------------------------------------------------------------
10 //* File Name : Cstartup_SAM7.c
11 //* Object : Low level initializations written in C for IAR
12 //* tools
13 //* 1.0 08/Sep/04 JPP : Creation
14 //* 1.10 10/Sep/04 JPP : Update AT91C_CKGR_PLLCOUNT filed
15 //*----------------------------------------------------------------------------
16
17 // Include the board file description
18 #include "Board.h"
19 #include <string.h>
20
21 extern void AT91F_DBGU_Printk(char *);
22 // The following functions must be write in ARM mode this function called directly
23 // by exception vector
24 extern void AT91F_Spurious_handler(void);
25 extern void AT91F_Default_IRQ_handler(void);
26 extern void AT91F_Default_FIQ_handler(void);
27
28
29 //*----------------------------------------------------------------------------
30 //* \fn AT91F_LowLevelInit
31 //* \brief This function performs very low level HW initialization
32 //* this function can be use a Stack, depending the compilation
33 //* optimization mode
34 //*----------------------------------------------------------------------------
\ In segment ICODE, align 4, keep-with-next
35 void AT91F_LowLevelInit( void) @ "ICODE"
36 {
\ AT91F_LowLevelInit:
\ 00000000 10B5 PUSH {R4,LR}
37 int i;
38 AT91PS_PMC pPMC = AT91C_BASE_PMC;
\ 00000002 1A4A LDR R2,??AT91F_LowLevelInit_0 ;; 0xfffffffffffffc00
\ 00000004 1100 MOVS R1,R2
39
40 // Set Flash Waite sate
41 // Single Cycle Access at Up to 30 MHz, or 40
42 // if MCK = 47923200 I have 75 Cycle for 1.5 useconde ( flied MC_FMR->FMCN
43 AT91C_BASE_MC->MC_FMR = ((AT91C_MC_FMCN)&(75 <<16)) | AT91C_MC_FWS_1FWS ;
\ 00000006 9F22 MOVS R2,#+159
\ 00000008 D243 MVNS R2,R2 ;; #-160
\ 0000000A 194B LDR R3,??AT91F_LowLevelInit_0+0x4 ;; 0x4b0100
\ 0000000C 1360 STR R3,[R2, #+0]
44
45 // Watchdog Disable
46 AT91C_BASE_WDTC->WDTC_WDMR= AT91C_WDTC_WDDIS;
\ 0000000E 194A LDR R2,??AT91F_LowLevelInit_0+0x8 ;; 0xfffffffffffffd44
\ 00000010 8023 MOVS R3,#+128
\ 00000012 1B02 LSLS R3,R3,#+8 ;; #+32768
\ 00000014 1360 STR R3,[R2, #+0]
47
48 // Set MCK at 47 923 200
49
50 // 1 Enabling the Main Oscillator:
51 // SCK = 1/32768 = 30.51 uSeconde
52 // Start up time = 8 * 6 / SCK = 56 * 30.51 = 1,46484375 ms
53 pPMC->PMC_MOR = (( AT91C_CKGR_OSCOUNT & (0x06 <<8) | AT91C_CKGR_MOSCEN ));
\ 00000016 184A LDR R2,??AT91F_LowLevelInit_0+0xC ;; 0x601
\ 00000018 0A62 STR R2,[R1, #+32]
54
55 // Wait the startup time
56 while(!(pPMC->PMC_SR & AT91C_PMC_MOSCS));
\ ??AT91F_LowLevelInit_1:
\ 0000001A 8A6E LDR R2,[R1, #+104]
\ 0000001C D207 LSLS R2,R2,#+31
\ 0000001E FCD5 BPL ??AT91F_LowLevelInit_1
57
58 // 2 Checking the Main Oscillator Frequency (Optional)
59
60 // 3 Setting PLL and divider:
61 // - div by 5 Fin = 3,6864 =(18,432 / 5)
62 // - Mul 25+1: Fout = 95,8464 =(3,6864 *26)
63 // for 96 MHz the erroe is 0.16%
64 //eld out NOT USED = 0 Fi
65 pPMC->PMC_PLLR = ((AT91C_CKGR_DIV & 5) |
66 (AT91C_CKGR_PLLCOUNT & (28<<8)) |
67 (AT91C_CKGR_MUL & (25<<16)));
\ 00000020 164A LDR R2,??AT91F_LowLevelInit_0+0x10 ;; 0x191c05
\ 00000022 CA62 STR R2,[R1, #+44]
68
69 // Wait the startup time
70 while(!(pPMC->PMC_SR & AT91C_PMC_LOCK));
\ ??AT91F_LowLevelInit_2:
\ 00000024 8A6E LDR R2,[R1, #+104]
\ 00000026 5207 LSLS R2,R2,#+29
\ 00000028 FCD5 BPL ??AT91F_LowLevelInit_2
71
72 // 4. Selection of Master Clock and Processor Clock
73 // select the PLL clock divided by 2
74 pPMC->PMC_MCKR = AT91C_PMC_PRES_CLK_2 ;
\ 0000002A 0422 MOVS R2,#+4
\ 0000002C 0A63 STR R2,[R1, #+48]
75 while(!(pPMC->PMC_SR & AT91C_PMC_MCKRDY));
\ ??AT91F_LowLevelInit_3:
\ 0000002E 8A6E LDR R2,[R1, #+104]
\ 00000030 1207 LSLS R2,R2,#+28
\ 00000032 FCD5 BPL ??AT91F_LowLevelInit_3
76
77 pPMC->PMC_MCKR |= AT91C_PMC_CSS_PLL_CLK ;
\ 00000034 0A6B LDR R2,[R1, #+48]
\ 00000036 0323 MOVS R3,#+3
\ 00000038 1343 ORRS R3,R3,R2
\ 0000003A 0B63 STR R3,[R1, #+48]
78 while(!(pPMC->PMC_SR & AT91C_PMC_MCKRDY));
\ ??AT91F_LowLevelInit_4:
\ 0000003C 8A6E LDR R2,[R1, #+104]
\ 0000003E 1207 LSLS R2,R2,#+28
\ 00000040 FCD5 BPL ??AT91F_LowLevelInit_4
79
80 // Set up the default interrupts handler vectors
81 AT91C_BASE_AIC->AIC_SVR[0] = (int) AT91F_Default_FIQ_handler ;
\ 00000042 0F4A LDR R2,??AT91F_LowLevelInit_0+0x14 ;; 0xfffffffffffff080
\ 00000044 0F4B LDR R3,??AT91F_LowLevelInit_0+0x18 ;; AT91F_Default_FIQ_handler
\ 00000046 1360 STR R3,[R2, #+0]
82 for (i=1;i < 31; i++)
\ 00000048 0122 MOVS R2,#+1
\ 0000004A 1000 MOVS R0,R2
\ ??AT91F_LowLevelInit_5:
\ 0000004C 1F28 CMP R0,#+31
\ 0000004E 06DA BGE ??AT91F_LowLevelInit_6
83 {
84 AT91C_BASE_AIC->AIC_SVR[i] = (int) AT91F_Default_IRQ_handler ;
\ 00000050 0422 MOVS R2,#+4
\ 00000052 4243 MULS R2,R0,R2
\ 00000054 0A4B LDR R3,??AT91F_LowLevelInit_0+0x14 ;; 0xfffffffffffff080
\ 00000056 0C4C LDR R4,??AT91F_LowLevelInit_0+0x1C ;; AT91F_Default_IRQ_handler
\ 00000058 9C50 STR R4,[R3, R2]
85 }
\ 0000005A 401C ADDS R0,R0,#+1
\ 0000005C F6E7 B ??AT91F_LowLevelInit_5
86 AT91C_BASE_AIC->AIC_SPU = (int) AT91F_Spurious_handler ;
\ ??AT91F_LowLevelInit_6:
\ 0000005E 0B4A LDR R2,??AT91F_LowLevelInit_0+0x20 ;; 0xfffffffffffff134
\ 00000060 0B4B LDR R3,??AT91F_LowLevelInit_0+0x24 ;; AT91F_Spurious_handler
\ 00000062 1360 STR R3,[R2, #+0]
87 }
\ 00000064 10BC POP {R4}
\ 00000066 01BC POP {R0}
\ 00000068 0047 BX R0 ;; return
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