syslib.c

Vxworks的bsp软件开发包(基于wrPpmc74xx)

/* sysLib.c - system-dependent library */

/* Copyright 1984-2002 Wind River Systems, Inc. */

/*
modification history
--------------------
01k,16may02,gjc  Adding AUX Timer
01j,01apr02,mil  Removed support for FXP END driver.
01i,13mar02,kab  Remove vmxExcLoad - SPR 74268
01h,04feb02,g_h  Include sysCacheLockLib.c only if INCLUDE_CACHE_SUPPORT 
                 defined.
01g,03feb02,g_h  Add support for the FXP END driver
01f,25jan02,g_h  Correct syntax error in the function documentation.
01e,12dec01,pch  Add nullVme driver
01d,23oct01,g_h  Add support for MPC7410
01c,22jun01,g_h  include sysNvRam.c
01b,08apr01,g_h	 add support for vWare II
01a,15jun98,est	 adopted from templatePpc/sysLib.c 
*/

/*

DESCRIPTION
This library provides board-specific routines.  The chip drivers included are:

    ns16550Sio.c            - SIO driver
    ppcDecTimer.c           - Decrementer Timer
    amd29LV800TMem.c        - NvRam on Flash access routines
    pciConfigLib.c          - PCI configuration library
    pciAutoConfigLib.c      - PCI Auto configuration library
    pciConfigShow.c         - PCI Show library
    sysMpc107Epic.c         - Interrrupt controller device
    sysMpc107Pci.c          - Motorola PCI Bridge/Memory Controller
    sysMpc107AuxClk.c       - MPC107 Epic timer based auxillary clock

INCLUDE FILES: sysLib.h

SEE ALSO:
.pG "Configuration"
*/

/* includes */

#include "stdio.h"
#include "vxWorks.h"
#include "vme.h"
#include "memLib.h"
#include "cacheLib.h"
#include "sysLib.h"
#include "config.h"
#include "string.h"
#include "intLib.h"
#include "esf.h"
#include "logLib.h"
#include "taskLib.h"
#include "vxLib.h"
#include "tyLib.h"
#include "arch/ppc/mmu603Lib.h"
#include "arch/ppc/vxPpcLib.h"
#include "private/vmLibP.h"
#include "drv/pci/mpc105.h"
#include "drv/pci/pciConfigLib.h"
#include "drv/pci/pciAutoConfigLib.h"
#include "sysMpc107Pci.h"
#include "wrPpmc74xx.h"
#ifdef INCLUDE_CACHE_L2
#include "sysCache.h"  
#endif /* INCLUDE_CACHE_L2 */

#if defined (INCLUDE_ALTIVEC)
#include "altivecLib.h"
#endif

IMPORT int         (* _func_altivecProbeRtn) () ;

/* defines */

#define ZERO    0

/* globals */

/*
 * sysBatDesc[] is used to initialize the block address translation (BAT)
 * registers within the PowerPC 603/604 MMU.  BAT hits take precedence
 * over Page Table Entry (PTE) hits and are faster.  Overlap of memory
 * coverage by BATs and PTEs is permitted in cases where either the IBATs
 * or the DBATs do not provide the necessary mapping (PTEs apply to both
 * instruction AND data space, without distinction).
 *
 * The primary means of memory control for VxWorks is the MMU PTE support
 * provided by vmLib and cacheLib.  Use of BAT registers will conflict
 * with vmLib support.  User's may use BAT registers for i/o mapping and
 * other purposes but are cautioned that conflicts with cacheing and mapping
 * through vmLib may arise.  Be aware that memory spaces mapped through a BAT
 * are not mapped by a PTE and any vmLib() or cacheLib() operations on such
 * areas will not be effective, nor will they report any error conditions.
 *
 * Note: BAT registers CANNOT be disabled - they are always active.
 * For example, setting them all to zero will yield four identical data
 * and instruction memory spaces starting at local address zero, each 128KB
 * in size, and each set as write-back and cache-enabled.  Hence, the BAT regs
 * MUST be configured carefully.
 *
 * With this in mind, it is recommended that the BAT registers be used
 * to map LARGE memory areas external to the processor if possible.
 * If not possible, map sections of high RAM and/or PROM space where
 * fine grained control of memory access is not needed.  This has the
 * beneficial effects of reducing PTE table size (8 bytes per 4k page)
 * and increasing the speed of access to the largest possible memory space.
 * Use the PTE table only for memory which needs fine grained (4KB pages)
 * control or which is too small to be mapped by the BAT regs.
 *
 * The BAT configuration for 4xx/6xx-based PPC boards is as follows:
 * All BATs point to PROM/FLASH memory so that end customer may configure
 * them as required.
 *
 * [Ref: chapter 7, PowerPC Microprocessor Family: The Programming Environments]
 */

UINT32 sysBatDesc [2 * (_MMU_NUM_IBAT + _MMU_NUM_DBAT)] = 
    {
    /* I BAT 0 - 4MB Flash*/
    ((FLASH_BASE_ADRS & _MMU_UBAT_BEPI_MASK) | _MMU_UBAT_BL_4M | _MMU_UBAT_VS | _MMU_UBAT_VP),
    ((FLASH_BASE_ADRS & _MMU_LBAT_BRPN_MASK) | _MMU_LBAT_PP_RW | _MMU_LBAT_CACHE_INHIBIT),

    /* I BAT 1 */
    ((ROM_BASE_ADRS & _MMU_UBAT_BEPI_MASK) | _MMU_UBAT_BL_1M | _MMU_UBAT_VS | _MMU_UBAT_VP),
    ((ROM_BASE_ADRS & _MMU_LBAT_BRPN_MASK) | _MMU_LBAT_PP_RW | _MMU_LBAT_CACHE_INHIBIT),

/* Contrary to the misguided comments above, the other IBATS are being disabled here.... */

    0, 0, /* I BAT 2 */

    0, 0, /* I BAT 3 */

    /* D BAT 0 - 4MB Flash */
    ((FLASH_BASE_ADRS & _MMU_UBAT_BEPI_MASK) | _MMU_UBAT_BL_4M | _MMU_UBAT_VS | _MMU_UBAT_VP),
    ((FLASH_BASE_ADRS & _MMU_LBAT_BRPN_MASK) | _MMU_LBAT_PP_RW  | _MMU_LBAT_CACHE_INHIBIT),

    /* D BAT 1 - PCI prefetchable memory + non-prefetchable memory  = 512MB */
    ((CPU_PCI_MEM_ADRS & _MMU_UBAT_BEPI_MASK) | _MMU_UBAT_BL_512M | _MMU_UBAT_VS | _MMU_UBAT_VP),
    ((CPU_PCI_MEM_ADRS & _MMU_LBAT_BRPN_MASK) | _MMU_LBAT_PP_RW | _MMU_LBAT_CACHE_INHIBIT | _MMU_LBAT_GUARDED),

    /* D BAT 2 - PCI plag & play memory */
    ((CPU_PCI_CNFG_ADRS & _MMU_UBAT_BEPI_MASK) | _MMU_UBAT_BL_32M | _MMU_UBAT_VS | _MMU_UBAT_VP),
    ((CPU_PCI_CNFG_ADRS & _MMU_LBAT_BRPN_MASK) | _MMU_LBAT_PP_RW  | _MMU_LBAT_CACHE_INHIBIT | _MMU_LBAT_GUARDED),

    /* D BAT 3 - PCI IO space */
    ((CPU_PCI_IO_ADRS & _MMU_UBAT_BEPI_MASK) | _MMU_UBAT_BL_16M | _MMU_UBAT_VS | _MMU_UBAT_VP),
    ((CPU_PCI_IO_ADRS & _MMU_LBAT_BRPN_MASK) | _MMU_LBAT_PP_RW  | _MMU_LBAT_CACHE_INHIBIT | _MMU_LBAT_GUARDED),
    };


#ifdef INCLUDE_MMU
/*
 * sysPhysMemDesc[] is used to initialize the Page Table Entry (PTE) array
 * used by the MMU to translate addresses with single page (4k) granularity.
 * PTE memory space should not, in general, overlap BAT memory space but
 * may be allowed if only Data or Instruction access is mapped via BAT.
 *
 * Address translations for local RAM, memory mapped PCI bus, memory mapped
 * VME A16 space and local PROM/FLASH are set here.
 *
 * PTEs are held, strangely enough, in a Page Table.  Page Table sizes are
 * integer powers of two based on amount of memory to be mapped and a
 * minimum size of 64 kbytes.  The MINIMUM recommended Page Table sizes
 * for 32-bit PowerPCs are:
 *
 * Total mapped memory		Page Table size
 * -------------------		---------------
 *        8 Meg			     64 K
 *       16 Meg			    128 K
 *       32 Meg			    256 K
 *       64 Meg			    512 K
 *      128 Meg			      1 Meg
 * 	.				.
 * 	.				.
 * 	.				.
 *
 * [Ref: chapter 7, PowerPC Microprocessor Family: The Programming Environments]
 */

PHYS_MEM_DESC sysPhysMemDesc [] =
{
    {
        /* Vector Table and Interrupt Stack */
        (void *) LOCAL_MEM_LOCAL_ADRS,
        (void *) LOCAL_MEM_LOCAL_ADRS,
        RAM_LOW_ADRS,
        VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE | VM_STATE_MASK_MEM_COHERENCY,
        VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE      | VM_STATE_MEM_COHERENCY
    },

    {
        /* Local SDRAM  */
        (void *) RAM_LOW_ADRS,
        (void *) RAM_LOW_ADRS,
        LOCAL_MEM_SIZE -  RAM_LOW_ADRS,
        VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE | VM_STATE_MASK_MEM_COHERENCY,
        VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE      | VM_STATE_MEM_COHERENCY
    },

    {
        /* NS16550 UART Reg */
        (void *) NS16550_BASE_ADRS,
        (void *) NS16550_BASE_ADRS,
        NS16550_REG_SIZE,
        VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE |VM_STATE_MASK_MEM_COHERENCY | VM_STATE_MASK_GUARDED,
        VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT  |VM_STATE_MEM_COHERENCY      | VM_STATE_GUARDED
    },

    {
        /* User LED Reg */
        (void *) USR_LED_BASE_ADRS,
        (void *) USR_LED_BASE_ADRS,
        USR_LED_REG_SIZE,
        VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE |VM_STATE_MASK_MEM_COHERENCY | VM_STATE_MASK_GUARDED,
        VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT  |VM_STATE_MEM_COHERENCY      | VM_STATE_GUARDED
    },

    {
        /* MailBox Reg */
        (void *) MAILBOX_BASE_ADRS,
        (void *) MAILBOX_BASE_ADRS,
        MAILBOX_REG_SIZE,
        VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE |VM_STATE_MASK_MEM_COHERENCY | VM_STATE_MASK_GUARDED,
        VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT  |VM_STATE_MEM_COHERENCY      | VM_STATE_GUARDED
    },

    {

        /* EUMB Reg */
        (void *) EUMB_BASE_ADRS,
        (void *) EUMB_BASE_ADRS,
        EUMB_REG_SIZE,
        VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE |VM_STATE_MASK_MEM_COHERENCY | VM_STATE_MASK_GUARDED,
        VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT  |VM_STATE_MEM_COHERENCY      | VM_STATE_GUARDED
    }
};

int sysPhysMemDescNumEnt = NELEMENTS (sysPhysMemDesc);

#endif /* INCLUDE_MMU */

int   sysBus      = BUS_TYPE;       /* system bus type */
int   sysCpu      = CPU;            /* system CPU type */
char *sysBootLine = BOOT_LINE_ADRS; /* address of boot line */
char *sysExcMsg   = EXC_MSG_ADRS;   /* catastrophic message area */
int   sysProcNum = 0;               /* processor number of this CPU */
int   sysFlags;                     /* boot flags */
char  sysBootHost [BOOT_FIELD_LEN]; /* name of host from which we booted */
char  sysBootFile [BOOT_FIELD_LEN]; /* name of file from which we booted */

/* locals */

LOCAL char sysModelStr[80];
LOCAL char wrongCpuMsg[] = WRONG_CPU_MSG; 

/* forward declarations */

void    sysCpuCheck (void);
char    *sysPhysMemTop (void);

/* externals */

IMPORT void  sysOutByte (ULONG, UCHAR);
IMPORT UCHAR sysInByte (ULONG);
IMPORT void  sysClearBATsInvalidateTLBs(void);

IMPORT VOIDFUNCPTR _pSysL2CacheInvFunc;
IMPORT VOIDFUNCPTR _pSysL2CacheEnable;
IMPORT VOIDFUNCPTR _pSysL2CacheDisable;
IMPORT VOIDFUNCPTR _pSysL2CacheFlush;

/* BSP DRIVERS */

#if (NV_RAM_SIZE == NONE)
#include "mem/nullNvRam.c"
#else
#include "sysNvRam.c"
#endif	

#include "vme/nullVme.c"
#include "timer/ppcDecTimer.c" 
#include "sysMpc107Pci.c"       /* PCI config space access */
#include "pci/pciConfigLib.c"   /* PCI config space access */

#ifdef INCLUDE_SHOW_ROUTINES
  #include "pci/pciConfigShow.c"    /* display of PCI config space */
#endif

#ifdef INCLUDE_PCI_AUTOCONF
#include "pci/pciAutoConfigLib.c"   /* Auto discovery/config */
#endif /* INCLUDE_PCI_AUTOCONF */

#ifdef INCLUDE_PCI_AUTOCONF
#include "sysPciAutoConfig.c"
#endif /* INCLUDE_PCI_AUTOCONF */

#include "sysSerial.c"              /* local    */
#include "sysMpc107Epic.c"

#ifdef INCLUDE_CACHE_SUPPORT
#include "sysCacheLockLib.c"        /* Cache Lock/unlock library */
#endif /* INCLUDE_CACHE_SUPPORT */

#include "abortSw.c"

/* network driver */
#ifdef INCLUDE_NETWORK
    #ifdef INCLUDE_END
        #ifdef INCLUDE_FEI82557END
        #include "sysFei82557End.c"
        #endif /* INCLUDE_FEI82557END */
    #endif /* INCLUDE_END */
    #include "sysNet.c"
#endif /* INCLUDE_NETWORK */

#ifdef INCLUDE_VWARE_LAUNCH
#include "sysVware.c"
#endif /* INCLUDE_VWARE_LAUNCH */

#ifdef INCLUDE_AUX_CLK
#include "sysMpc107AuxClk.c"     /* mpc107 Epic Aux Clk support */
#endif
#if     defined (INCLUDE_ALTIVEC)
/***************************************************************************    
*
* sysAltivecProbe - Check if the CPU has ALTIVEC unit.
*
* This routine returns OK it the CPU has an ALTIVEC unit in it.
* Presently it checks for 7400
* RETURNS: OK  -  for 7400 Processor type
*          ERROR - otherwise.
*/

int sysAltivecProbe 
    (
    void
    )
    {
    ULONG regVal;
    int altivecUnitPresent = ERROR;

    /* The CPU type is indicated in the Processor Version Register (PVR) */

    regVal = CPU_TYPE;

    switch (regVal)
        {
        case CPU_TYPE_7400:
        case CPU_TYPE_7410:
            altivecUnitPresent = OK;
            break;
        default:
            altivecUnitPresent = ERROR; 
            break;
        }      /* switch  */

    return(altivecUnitPresent);
    }
#endif  /* INCLUDE_ALTIVEC */

/***************************************************************************    
*
* sysModel - return the model name of the CPU board
*
* This routine returns the model name of the CPU board.  The returned string
* depends on the board model and CPU version being used.
*
* RETURNS: A pointer to the string.
*/

char * sysModel 
    (
    void
    )
    {

    UINT cpu;
    char cpuStr[80];

    /* Determine CPU type and build display string */

    cpu = CPU_TYPE;
    switch (cpu)
        {
        case CPU_TYPE_750:
            sprintf(cpuStr, "750");
            break;
        case CPU_TYPE_755:
            sprintf(cpuStr, "755");
            break;
        case CPU_TYPE_7400:
            sprintf(cpuStr, "7400");
            break;
        case CPU_TYPE_7410:
            sprintf(cpuStr, "7410");
            break;
        default:
            sprintf (cpuStr, "7xx");
            break;
        }

    sprintf (sysModelStr, "Motorola PowerPC %s - Wind River PPMC%s Board", cpuStr, cpuStr);

    return(sysModelStr);
    }

/***************************************************************************    
*
* sysBspRev - return the BSP version and revision number
*
* This routine returns a pointer to a BSP version and revision number, for
* example, 1.2/0. BSP_REV is concatenated to BSP_VERSION and returned.
*
* RETURNS: A pointer to the BSP version/revision string.
*/