📄 mpc107def.h
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/* mpc107Def.h - Motorola MPC107 definitions *//* Copyright 1984-2001 Wind River Systems, Inc. *//*modification history--------------------01b,25oct01,g_h Cleaning01a,05mar98,est created*//*DESCRIPTION:Contains structure typedefs for the Motorola MPC107*/#ifndef __INCmpc107Defh#define __INCmpc107Defh#ifdef __cplusplusextern "C" {#endif/* HI/LOW Adjust Macros; generic, tool vendor neutral. */#define HI_HALF(value) ((value >> 16) & 0x0000FFFF)#define LO_HALF(value) (value & 0x0000FFFF)/* PCI Command Register. */#define PCICMD_ADDR 0x04#define PCICMD_FAST_B2B (1 << 9)#define PCICMD_SERR (1 << 8)#define PCICMD_PER (1 << 6)#define PCICMD_MEM_W_INV (1 << 4)#define PCICMD_SPECIAL_CYC (1 << 3)#define PCICMD_BUS_MASTER (1 << 2)#define PCICMD_MEM_SPACE (1 << 1)#define PCICMD_IO_SPACE (1 << 0)#define PCICMD_RSVD_MASK 0xFCA0/* PCI Status Register */#define PCISTATUS_ADDR 0x06#define PCISTATUS_DET_PE (1 << 15)#define PCISTATUS_SIG_SI (1 << 14)#define PCISTATUS_RCV_MA (1 << 13)#define PCISTATUS_RCV_TA (1 << 12)#define PCISTATUS_SIG_TA (1 << 11)#define PCISTATUS_DEVSEL_TIME (3 << 9)#define PCISTATUS_DATA_PE (1 << 8)#define PCISTATUS_FAST_B2BC (1 << 7)#define PCISTATUS_66MHZ_CAP (1 << 5)#define PCISTATUS_RSVD_MASK 0xFF4F/* Power Management Configuration Register 1 */#define PMCR1_ADDR 0x70#define PMCR1_NO_NAP_MSG (1 << 15)#define PMCR1_NO_SLEEP_MSG (1 << 15)#define PMCR1_SLEEP_MSG_TYPE (1 << 13)#define PMCR1_LP_REF_EN (1 << 12)#define PMCR1_NO_604_RUN (1 << 11)#define PMCR1_601_NEED_QREQ (1 << 10)#define PMCR1_SUSP_QACK (1 << 9)#define PMCR1_PM (1 << 7)#define PMCR1_DOZE (1 << 5)#define PMCR1_NAP (1 << 4)#define PMCR1_SLEEP (1 << 3)#define PMCR1_CKO_MODE (3 << 1)#define PMCR1_BR1_WAKE (1 << 0)#define PMCR1_MASK 0xFF5F/* Power Management Configuration Register 2 */#define PMCR2_ADDR 0x72#define PMCR2_SHARED_MCP (1 << 0)#define PMCR2_MASK 0xFE/* Error Enable Register 1 */#define EER1_ADDR 0xC0#define EER1_PCI_RCV_TAE (1 << 7)#define EER1_PCI_TGT_PERR_ENB (1 << 6)#define EER1_MEM_SLCT_ERR_ENB (1 << 5)#define EER1_MEM_RFRSH_OFL_ENB (1 << 4)#define EER1_PCI_MSTR_PERR_ENB (1 << 3)#define EER1_PCI_PAR_ECC_ENB (1 << 2)#define EER1_PCI_PCI_MA_ENB (1 << 1)#define EER1_60X_BUS_ERR_ENB (1 << 0)/* Error Enable Register 1 */#define EER2_ADDR 0xC4#define EER2_PCI_ADDR_PE_ENB (1 << 7)#define EER2_ILLEGAL_L2_CB_ERR_ENB (1 << 5)#define EER2_L2_PARITY_ERR_ENB (1 << 4)#define EER2_ECC_MB_ERR_ENB (1 << 3)#define EER2_FLASH_ROM_WRITE_ERR_ENB (1 << 0)#define EER2_RSVD_MASK 0x46/* Error Detection Register 1 */#define EDR1_ADDR 0xC1#define EDR1_PCI_SERR (1 << 7)#define EDR1_PCI_TGT_PERR (1 << 6)#define EDR1_MEM_SELECT_ERR (1 << 5)#define EDR1_MEM_RFRSH_ERR (1 << 4)#define EDR1_60X_PCI_CYCL_ERR (1 << 3)#define EDR1_MEM_READ_PERR (1 << 2)#define EDR1_UNSPT_BUS_CYCL_ERR (3 << 0)/* Error Detection Register 2 */#define EDR2_ADDR 0xC5#define EDR2_INVALID_ERR_ADDR (1 << 7)#define EDR2_ILLEGAL_L2_CB_ERR (1 << 5)#define EDR2_L2_PARITY_ERR (1 << 4)#define EDR2_ECC_MB_ERR (1 << 3)#define EDR2_FLASH_ROM_WR_ERR (1 << 0)#define EDR2_RSVD_MASK 0x46/* PCI Bus Error Status Register */#define PCI_BERR_SR_ADDR 0xC7#define PCI_BERR_SR_MPC106_MT_STATUS (1 << 4)#define PCI_BERR_SR_C_BE_3_0 (0xF << 0)#define PCI_BERR_SR_RSV_MASK 0xE0/* Memory Control Registers and Macros * * Note that these macros will take a full 32 bit address * and translate it into the correct bit position for the * Memory Control Registers, but they do not check to see * if alignment/boundries are correct; they will simply * round down to the nearest 1 Mb boundry. */#define MEMCTL_0_3_START_ADDR 0x80#define MEMCTL_4_7_START_ADDR 0x84#define MEMCTL_0_3_START_EXT_ADDR 0x88#define MEMCTL_4_7_START_EXT_ADDR 0x8C#define MEMCTL_0_3_END_ADDR 0x90#define MEMCTL_4_7_END_ADDR 0x94#define MEMCTL_0_3_END_EXT_ADDR 0x98#define MEMCTL_4_7_END_EXT_ADDR 0x9C#define MEMCTL_EXT_ADDR_MASK 0xFCFCFCFC#define MEMCTL_B0_START_ADDR(addr) ((addr & 0x0FF00000) >> 20)#define MEMCTL_B0_EXT_START_ADDR(addr) ((addr & 0x30000000) >> 28)#define MEMCTL_B1_START_ADDR(addr) ((addr & 0x0FF00000) >> 12)#define MEMCTL_B1_EXT_START_ADDR(addr) ((addr & 0x30000000) >> 20)#define MEMCTL_B2_START_ADDR(addr) ((addr & 0x0FF00000) >> 4)#define MEMCTL_B2_EXT_START_ADDR(addr) ((addr & 0x30000000) >> 12)#define MEMCTL_B3_START_ADDR(addr) ((addr & 0x0FF00000) << 4)#define MEMCTL_B3_EXT_START_ADDR(addr) ((addr & 0x30000000) >> 4)#define MEMCTL_B4_START_ADDR(addr) ((addr & 0x0FF00000) >> 20)#define MEMCTL_B4_EXT_START_ADDR(addr) ((addr & 0x30000000) >> 28)#define MEMCTL_B5_START_ADDR(addr) ((addr & 0x0FF00000) >> 12)#define MEMCTL_B5_EXT_START_ADDR(addr) ((addr & 0x30000000) >> 20)#define MEMCTL_B6_START_ADDR(addr) ((addr & 0x0FF00000) >> 4)#define MEMCTL_B6_EXT_START_ADDR(addr) ((addr & 0x30000000) >> 12)#define MEMCTL_B7_START_ADDR(addr) ((addr & 0x0FF00000) << 4)#define MEMCTL_B7_EXT_START_ADDR(addr) ((addr & 0x30000000) >> 4)#define MEMCTL_B0_END_ADDR(addrE) (((addrE - 1) & 0x0FF00000) >> 20)#define MEMCTL_B0_EXT_END_ADDR(addrE) (((addrE - 1) & 0x30000000) >> 28)#define MEMCTL_B1_END_ADDR(addrE) (((addrE - 1) & 0x0FF00000) >> 12)#define MEMCTL_B1_EXT_END_ADDR(addrE) (((addrE - 1) & 0x30000000) >> 20)#define MEMCTL_B2_END_ADDR(addrE) (((addrE - 1) & 0x0FF00000) >> 4)#define MEMCTL_B2_EXT_END_ADDR(addrE) (((addrE - 1) & 0x30000000) >> 12)#define MEMCTL_B3_END_ADDR(addrE) (((addrE - 1) & 0x0FF00000) << 4)#define MEMCTL_B3_EXT_END_ADDR(addrE) (((addrE - 1) & 0x30000000) >> 4)#define MEMCTL_B4_END_ADDR(addrE) (((addrE - 1) & 0x0FF00000) >> 20)#define MEMCTL_B4_EXT_END_ADDR(addrE) (((addrE - 1) & 0x30000000) >> 28)#define MEMCTL_B5_END_ADDR(addrE) (((addrE - 1) & 0x0FF00000) >> 12)#define MEMCTL_B5_EXT_END_ADDR(addrE) (((addrE - 1) & 0x30000000) >> 20)#define MEMCTL_B6_END_ADDR(addrE) (((addrE - 1) & 0x0FF00000) >> 4)#define MEMCTL_B6_EXT_END_ADDR(addrE) (((addrE - 1) & 0x30000000) >> 12)#define MEMCTL_B7_END_ADDR(addrE) (((addrE - 1) & 0x0FF00000) << 4)#define MEMCTL_B7_EXT_END_ADDR(addrE) (((addrE - 1) & 0x30000000) >> 4)#define MEM_BANK_ENABLE_ADDR 0xA0#define MEM_BANK_ENABLE_0 (1 << 0)#define MEM_BANK_ENABLE_1 (1 << 1)#define MEM_BANK_ENABLE_2 (1 << 2)#define MEM_BANK_ENABLE_3 (1 << 3)#define MEM_BANK_ENABLE_4 (1 << 4)#define MEM_BANK_ENABLE_5 (1 << 5)#define MEM_BANK_ENABLE_6 (1 << 6)#define MEM_BANK_ENABLE_7 (1 << 7)#define MEM_PGMAX_ADDR 0xA3#define MCCR1_ADDR 0xF0#define MCCR1_ROMNAL(time) ((time & 0x0F) << 28)#define MCCR1_ROMFAL(time) ((time & 0x1F) << 23)#define MCCR1_8N64 (1 << 21)#define MCCR1_BURST (1 << 20)#define MCCR1_MEMGO (1 << 19)#define MCCR1_SREN (1 << 18)#define MCCR1_RAM_TYPE (1 << 17)#define MCCR1_PCKEN (1 << 16)#define MCCR1_BANK7_ROW(row) ((row & 0x03) << 14)#define MCCR1_BANK6_ROW(row) ((row & 0x03) << 12)#define MCCR1_BANK5_ROW(row) ((row & 0x03) << 10)#define MCCR1_BANK4_ROW(row) ((row & 0x03) << 8)#define MCCR1_BANK3_ROW(row) ((row & 0x03) << 6)#define MCCR1_BANK2_ROW(row) ((row & 0x03) << 4)#define MCCR1_BANK1_ROW(row) ((row & 0x03) << 2)#define MCCR1_BANK0_ROW(row) ((row & 0x03) << 0)#define MCCR1_RSVD_MASK 0x00100000#define MCCR2_ADDR 0xF4#define MCCR2_ECC_EN (1 << 17)#define MCCR2_EDO (1 << 16)#define MCCR2_REFRESH_INT(rate) ((rate & 0x3FFF) << 2)#define MCCR2_BUF_MODE (1 << 1)#define MCCR2_RMW_PAR (1 << 0)#define MCCR2_RSVD_MASK 0xFFFC0000#define MCCR3_ADDR 0xF8#define MCCR4_ADDR 0xFC#define MCCR4_RSVD_MASK 0x00C00000/* Procesor Interface Configuration Register 1 */#define PICR1_ADDR 0xA8#define PICR1_CF_CBA_MASK(mask) ((mask & 0x0FF) << 24)#define PICR1_CF_BREAD_WS(bread) ((bread & 0x03) << 22)#define PICR1_CF_CACHE_1G (1 << 21)#define PICR1_RCS0 (1 << 20)#define PICR1_XIO_MODE (1 << 19)#define PICR1_PROC_TYPE_601 (0 << 17)#define PICR1_PROC_TYPE_603 (2 << 17)#define PICR1_PROC_TYPE_604 (3 << 17)#define PICR1_ADDRESS_MAP (1 << 16)#define PICR1_CF_MP_MASK (3 << 14)#define PICR1_CF_LBA_EN (1 << 13)#define PICR1_FLASH_WR_EN (1 << 12)#define PICR1_MCP_EN (1 << 11)#define PICR1_TEA_EN (1 << 10)#define PICR1_CF_DPARK (1 << 9)#define PICR1_CF_EXTERNAL_L2 (1 << 8)#define PICR1_NO_PORT_REGS (1 << 7)#define PICR1_ST_GATH_EN (1 << 6)#define PICR1_ST_LE_MODE (1 << 5)#define PICR1_CF_LOOP_SNOOP (1 << 4)#define PICR1_CF_APARK (1 << 3)#define PICR1_SPECULATIVE_PCI_RD (1 << 2)#define PICR1_CF_L2_MP(config) (config & 0x03)/* Procesor Interface Configuration Register 2 */#define PICR2_ADDR 0xAC#define PICR2_L2_UPDATE_EN (1 << 31)#define PICR2_L2_EN (1 << 30)#define PICR2_NO_SERIAL_CFG (1 << 29)#define PICR2_CF_FLUSH_L2 (1 << 28)#define PICR2_NO_SNOOP_EN (1 << 27)#define PICR2_FF0_LOCAL (1 << 26)#define PICR2_FLASH_WR_LOCKOUT (1 << 25)#define PICR2_CF_FAST_L2_MODE (1 << 24)#define PICR2_CF_DATA_RAM_TYPE(ramType) ((ramType & 0x03) << 22)#define PICR2_CF_WMODE(mode) ((mode & 0x03) << 20)#define PICR2_CF_SNOOP_WS(waitStates) ((waitStates & 0x03) << 18)#define PICR2_CF_MOD_HIGH (1 << 17)#define PICR2_CF_HIT_HIGH (1 << 16)#define PICR2_CF_ADDR_ONLY_DISABLE (1 << 14)#define PICR2_CF_HOLD (1 << 13)#define PICR2_CF_INV_MODE (1 << 12)#define PICR2_CF_RWITM_FILL (1 << 11)#define PICR2_CF_L2_HIT_DELAY(hit) ((hit & 0x03) << 9)#define PICR2_CF_TWO_BANKS (1 << 8)#define PICR2_CF_FAST_CASOUT (1 << 7)#define PICR2_CF_TOE_WIDTH (1 << 6)#define PICR2_CF_L2_SIZE(l2Size) ((l2Size & 0x03) << 4)#define PICR2_CF_APHASE_WS(aPhaseWS) ((aPhaseWS & 0x03) << 2)#define PICR2_CF_DOE (1 << 1)#define PICR2_CF_WDATA (1 << 0)#define PICR2_RSVD_MASK 0x00008000/* Alternate OS-Visable Parameter Register 1 */#define AOSVPR1_ADDR 0xBA#define AOSVPR1_RX_SERR_EN (1 << 5)#define AOSVPR1_XIO_MODE (1 << 2)#define AOSVPR1_TEA_EN (1 << 1)#define AOSVPR1_MCP_EN (1 << 0)#define AOSVPR1_RSVD_MASK 0xD8/* Alternate OS-Visable Parameter Register 2 */#define AOSVPR2_ADDR 0xBB#define AOSVPR1_FLASH_WR_EN (1 << 0)#define AOSVPR2_RSVD_MASK 0xFE#ifdef __cplusplus}#endif#endif /* __INCmpc107Defh */⌨️ 快捷键说明
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