sysmpc107epic.h

Vxworks的bsp软件开发包(基于wrPpmc74xx)

/* sysMpc107Epic.h - Motorola MPC107 EPIC definitions */

/* Copyright 1984-2001 Wind River Systems, Inc. */

/*
modification history
--------------------
01a,12may01,g_h  created
*/

/*
Description:

Contains structure typedefs for the Motorola MPC107 EPIC
*/


#ifndef	__INCsysMpc107Epich
#define	__INCsysMpc107Epich

#ifdef __cplusplus
extern "C" {
#endif

/* includes */

/* structures */
typedef struct intHandlerDesc           /* interrupt handler desciption */
    {
    VOIDFUNCPTR                 vec;    /* interrupt vector */
    int                         arg;    /* interrupt handler argument */
    struct intHandlerDesc *     next;   /* next interrupt handler & argument */
    } INT_HANDLER_DESC;


/* macros */
#define VECTOR_MASK		0x000000ff


#ifndef	_ASMLANGUAGE

/* interrupt Vector/Priority masks */
#define EPIC_INT_MASK       0x80000000
#define EPIC_INT_ACT        0x40000000
#define EPIC_INT_POLARITY   0x00800000
#define EPIC_INT_SENSE      0x00400000

/* interrupt vector assignments */
#define INT_VEC_NONE   0x7F 
#define INT_VEC_SPURIOUS   0xFF 
#define INT_VEC_IRQ0	0x00
#define INT_VEC_IRQ1	0x01
#define INT_VEC_IRQ2	0x02
#define INT_VEC_IRQ3	0x03
#define INT_VEC_IRQ4	0x04
#define INT_VEC_TMR0	0x10
#define INT_VEC_TMR1	0x11
#define INT_VEC_TMR2	0x12
#define INT_VEC_TMR3	0x13
#define INT_VEC_DMA0	0x20
#define INT_VEC_DMA1	0x21
#define INT_VEC_I2C	0x22
#define INT_VEC_I2O	0x23

/* interrupt priority assignments */

#define INT_PRI(x)	((x) << 16)

#define INT_PRI_NONE	INT_PRI(0)
#define INT_PRI_IRQ0	INT_PRI(0x0e)
#define INT_PRI_IRQ1	INT_PRI(0x0d)
#define INT_PRI_IRQ2	INT_PRI(0x0c)
#define INT_PRI_IRQ3	INT_PRI(0x0b)
#define INT_PRI_IRQ4	INT_PRI(0x0a)
#define INT_PRI_TMR0	INT_PRI(0x09)
#define INT_PRI_TMR1	INT_PRI(0x08)
#define INT_PRI_TMR2	INT_PRI(0x07)
#define INT_PRI_TMR3	INT_PRI(0x06)
#define INT_PRI_DMA0	INT_PRI(0x05)
#define INT_PRI_DMA1	INT_PRI(0x04)
#define INT_PRI_I2C	INT_PRI(0x03)
#define INT_PRI_I2O	INT_PRI(0x02)


/* MPC107 Emmbedded Utilities Base Address Register(EUMBBAR) offset */
/* Embedded Utilities Memory Block  */
#define EUMB    	    EUMB_BASE_ADRS
#define EUMB_LEN    	0x00080000  

/*  Embedded Programmable Interrupt Control registers */
#define EPIC_OFS	0x40000   /* offset of EPIC with EUMB */

#define EPIC_FEATURE	((UINT32 *)(EUMB_BASE_ADRS+0x41000))  
#define EPIC_GCR	((UINT32 *)(EUMB_BASE_ADRS+0x41020)) 
#define EPIC_EICR	((UINT32 *)(EUMB_BASE_ADRS+0x41030)) 
#define EPIC_EPIC_ID	((UINT32 *)(EUMB_BASE_ADRS+0x41080)) 
#define EPIC_PROC_IN	((UINT32 *)(EUMB_BASE_ADRS+0x41090)) 
#define EPIC_S_VECTOR	((UINT32 *)(EUMB_BASE_ADRS+0x410E0))
#define EPIC_TFREQ	((UINT32 *)(EUMB_BASE_ADRS+0x410F0)) 
#define EPIC_GTCC0	((UINT32 *)(EUMB_BASE_ADRS+0x41100)) 
#define EPIC_GTBC0	((UINT32 *)(EUMB_BASE_ADRS+0x41110))
#define EPIC_GTVR0	((UINT32 *)(EUMB_BASE_ADRS+0x41120)) 
#define EPIC_GTD0	((UINT32 *)(EUMB_BASE_ADRS+0x41130))  
#define EPIC_GTCC1	((UINT32 *)(EUMB_BASE_ADRS+0x41140)) 
#define EPIC_GTBC1	((UINT32 *)(EUMB_BASE_ADRS+0x41150)) 
#define EPIC_GTVR1	((UINT32 *)(EUMB_BASE_ADRS+0x41160)) 
#define EPIC_GTD1	((UINT32 *)(EUMB_BASE_ADRS+0x41170)) 
#define EPIC_GTCC2	((UINT32 *)(EUMB_BASE_ADRS+0x41180))  
#define EPIC_GTBC2	((UINT32 *)(EUMB_BASE_ADRS+0x41190))  
#define EPIC_GTVR2	((UINT32 *)(EUMB_BASE_ADRS+0x411A0))  
#define EPIC_GTD2	((UINT32 *)(EUMB_BASE_ADRS+0x411B0))  
#define EPIC_GTCC3	((UINT32 *)(EUMB_BASE_ADRS+0x411C0))  
#define EPIC_GTBC3	((UINT32 *)(EUMB_BASE_ADRS+0x411D0))  
#define EPIC_GTVR3	((UINT32 *)(EUMB_BASE_ADRS+0x411E0))  
#define EPIC_GTD3	((UINT32 *)(EUMB_BASE_ADRS+0x411F0))  
#define EPIC_EISVP0	((UINT32 *)(EUMB_BASE_ADRS+0x50200)) 
#define EPIC_EISD0	((UINT32 *)(EUMB_BASE_ADRS+0x50210))  
#define EPIC_EISVP1	((UINT32 *)(EUMB_BASE_ADRS+0x50220)) 
#define EPIC_EISD1	((UINT32 *)(EUMB_BASE_ADRS+0x50230))  
#define EPIC_EISVP2	((UINT32 *)(EUMB_BASE_ADRS+0x50240)) 
#define EPIC_EISD2	((UINT32 *)(EUMB_BASE_ADRS+0x50250))  
#define EPIC_EISVP3	((UINT32 *)(EUMB_BASE_ADRS+0x50260)) 
#define EPIC_EISD3	((UINT32 *)(EUMB_BASE_ADRS+0x50270))  
#define EPIC_EISVP4	((UINT32 *)(EUMB_BASE_ADRS+0x50280)) 
#define EPIC_EISD4	((UINT32 *)(EUMB_BASE_ADRS+0x50290))  
#define EPIC_SISVP0	((UINT32 *)(EUMB_BASE_ADRS+0x50200)) 
#define EPIC_SISD0	((UINT32 *)(EUMB_BASE_ADRS+0x50210))  
#define EPIC_SISVP1	((UINT32 *)(EUMB_BASE_ADRS+0x50220))  
#define EPIC_SISD1	((UINT32 *)(EUMB_BASE_ADRS+0x50230))  
#define EPIC_SISVP2	((UINT32 *)(EUMB_BASE_ADRS+0x50240)) 
#define EPIC_SISD2	((UINT32 *)(EUMB_BASE_ADRS+0x50250)) 
#define EPIC_SISVP3	((UINT32 *)(EUMB_BASE_ADRS+0x50260))  
#define EPIC_SISD3	((UINT32 *)(EUMB_BASE_ADRS+0x50270))  
#define EPIC_SISVP4	((UINT32 *)(EUMB_BASE_ADRS+0x50280)) 
#define EPIC_SISD4	((UINT32 *)(EUMB_BASE_ADRS+0x50290))  
#define EPIC_SISVP5	((UINT32 *)(EUMB_BASE_ADRS+0x502A0)) 
#define EPIC_SISD5	((UINT32 *)(EUMB_BASE_ADRS+0x502B0)) 
#define EPIC_SISVP6	((UINT32 *)(EUMB_BASE_ADRS+0x502C0)) 
#define EPIC_SISD6	((UINT32 *)(EUMB_BASE_ADRS+0x502D0)) 
#define EPIC_SISVP7	((UINT32 *)(EUMB_BASE_ADRS+0x502E0))  
#define EPIC_SISD7	((UINT32 *)(EUMB_BASE_ADRS+0x502F0))  
#define EPIC_SISVP8	((UINT32 *)(EUMB_BASE_ADRS+0x50300)) 
#define EPIC_SISD8	((UINT32 *)(EUMB_BASE_ADRS+0x50310)) 
#define EPIC_SISVP9	((UINT32 *)(EUMB_BASE_ADRS+0x50320)) 
#define EPIC_SISD9	((UINT32 *)(EUMB_BASE_ADRS+0x50330)) 
#define EPIC_SISVP10	((UINT32 *)(EUMB_BASE_ADRS+0x50340)) 
#define EPIC_SISD10	((UINT32 *)(EUMB_BASE_ADRS+0x50350)) 
#define EPIC_SISVP11	((UINT32 *)(EUMB_BASE_ADRS+0x50360)) 
#define EPIC_SISD11	((UINT32 *)(EUMB_BASE_ADRS+0x50370))  
#define EPIC_SISVP12	((UINT32 *)(EUMB_BASE_ADRS+0x50380))  
#define EPIC_SISD12	((UINT32 *)(EUMB_BASE_ADRS+0x50390)) 
#define EPIC_SISVP13	((UINT32 *)(EUMB_BASE_ADRS+0x503A0)) 
#define EPIC_SISD13	((UINT32 *)(EUMB_BASE_ADRS+0x503B0))  
#define EPIC_SISVP14	((UINT32 *)(EUMB_BASE_ADRS+0x503C0)) 
#define EPIC_SISD14	((UINT32 *)(EUMB_BASE_ADRS+0x503D0)) 
#define EPIC_SISVP15	((UINT32 *)(EUMB_BASE_ADRS+0x503E0))  
#define EPIC_SISD15	((UINT32 *)(EUMB_BASE_ADRS+0x503F0)) 
#define EPIC_I2C_VR	((UINT32 *)(EUMB_BASE_ADRS+0x51020)) 
#define EPIC_I2C_DR	((UINT32 *)(EUMB_BASE_ADRS+0x51030)) 
#define EPIC_DMA0_VR	((UINT32 *)(EUMB_BASE_ADRS+0x51040)) 
#define EPIC_DMA0_DR	((UINT32 *)(EUMB_BASE_ADRS+0x51050)) 
#define EPIC_DMA1_VR	((UINT32 *)(EUMB_BASE_ADRS+0x51060)) 
#define EPIC_DMA1_DR	((UINT32 *)(EUMB_BASE_ADRS+0x51070)) 
#define EPIC_I2O_VR	((UINT32 *)(EUMB_BASE_ADRS+0x510C0)) 
#define EPIC_I2O_DR	((UINT32 *)(EUMB_BASE_ADRS+0x510D0)) 
#define EPIC_PCTP	((UINT32 *)(EUMB_BASE_ADRS+0x60080))  
#define EPIC_PIACK	((UINT32 *)(EUMB_BASE_ADRS+0x600A0)) 
#define EPIC_PEOI	((UINT32 *)(EUMB_BASE_ADRS+0x600B0))

#endif	/* _ASMLANGUAGE */

#ifdef __cplusplus
}
#endif

#endif	/* __INCsysMpc107Epich */