rominit.s

Vxworks的bsp软件开发包(基于wrPpmc74xx)

/* romInit.s - Wind River PPMC74xx ROM initialization module */

/* Copyright 1984-2002 Wind River Systems, Inc. */

/*
modification history
--------------------
01e,04apr02,pch  SPR 74348: Machine Check cleanup
01d,20dec01,kab  Fix for diab
01c,23oct01,g_h  Cleaning for T2.2
01d,21may01,kab  .ascii directives fail to compile
01c,08dec98,est	 ported from yk603 to est603
*/

/*

DESCRIPTION
This module contains the entry code for VxWorks images that start
running from ROM, such as 'bootrom' and 'vxWorks_rom'.
The entry point, romInit(), is the first code executed on power-up.
It performs the minimal setup needed to call
the generic C routine romStart() with parameter BOOT_COLD.

RomInit() typically masks interrupts in the processor, sets the initial
stack pointer (to STACK_ADRS which is defined in configAll.h), and
readies system memory by configuring the DRAM controller if necessary.
Other hardware and device initialization is performed later in the
BSP's sysHwInit() routine.

A second entry point in romInit.s is called romInitWarm(). It is called
by sysToMonitor() in sysLib.c to perform a warm boot.
The warm-start entry point must be written to allow a parameter on
the stack to be passed to romStart().

WARNING:
This code must be Position Independent Code (PIC).  This means that it
should not contain any absolute address references.  If an absolute address
must be used, it must be relocated by the macro ROM_ADRS(x).  This macro
will convert the absolute reference to the appropriate address within
ROM space no matter how the boot code was linked. (For PPC, ROM_ADRS does
not work.  You must subtract _romInit and add ROM_TEXT_ADRS to each
absolute address). (NOTE: ROM_ADRS(x) macro does not work for current
PPC compiler).

This code should not call out to subroutines declared in other modules,
specifically sysLib.o, and sysALib.o.  If an outside module is absolutely
necessary, it can be linked into the system by adding the module 
to the makefile variable BOOT_EXTRA.  If the same module is referenced by
other BSP code, then that module must be added to MACH_EXTRA as well.
Note that some C compilers can generate code with absolute addresses.
Such code should not be called from this module.  If absolute addresses
cannot be avoided, then only ROM resident code can be generated from this
module.  Compressed and uncompressed bootroms or VxWorks images will not
work if absolute addresses are not processed by the macro ROM_ADRS.

WARNING:
The most common mistake in BSP development is to attempt to do too much
in romInit.s.  This is not the main hardware initialization routine.
Only do enough device initialization to get memory functioning.  All other
device setup should be done in sysLib.c, as part of sysHwInit().

Unlike other RTOS systems, VxWorks does not use a single linear device
initialization phase.  It is common for inexperienced BSP writers to take
a BSP from another RTOS, extract the assembly language hardware setup
code and try to paste it into this file.  Because VxWorks provides 3
different memory configurations, compressed, uncompressed, and rom-resident,
this strategy will usually not work successfully.

WARNING:
The second most common mistake made by BSP writers is to assume that
hardware or CPU setup functions done by romInit.o do not need to be
repeated in sysALib.s or sysLib.c.  A vxWorks image needs only the following
from a boot program: The startType code, and the boot parameters string
in memory.  Each VxWorks image will completely reset the CPU and all
hardware upon startup.  The image should not rely on the boot program to
initialize any part of the system (it may assume that the memory controller
is initialized).

This means that all initialization done by romInit.s must be repeated in
either sysALib.s or sysLib.c.  The only exception here could be the
memory controller.  However, in most cases even that can be
reinitialized without harm.

Failure to follow this rule may require users to rebuild bootrom's for
minor changes in configuration.  It is WRS policy that bootroms and vxWorks
images should not be linked in this manner.
*/

#define	_ASMLANGUAGE
#include "vxWorks.h"
#include "sysLib.h"
#include "asm.h"
#include "config.h"
#include "regs.h"
#include "mpc107Def.h"	
#include "wrPpmc74xx.h"

        /* globals */

	FUNC_EXPORT(_romInit)     /* start of system code */
	FUNC_EXPORT(romInit)      /* start of system code */
	FUNC_EXPORT(_romInitWarm) /* start of system code */
	FUNC_EXPORT(romInitWarm)  /* start of system code */

        /* externals */
	FUNC_IMPORT(romStart)     /* system initialization routine */

        _WRS_TEXT_SEG_START

/***************************************************************************
*
* romInit - entry point for VxWorks in ROM
*
* SYNOPSIS
* \ss
* romInit
*     (
*     int startType     /@ only used by 2nd entry point @/
*     )
* \se
*/

FUNC_BEGIN(_romInit)
FUNC_BEGIN(romInit)

	/* This is the cold boot entry (ROM_TEXT_ADRS) */
	bl	cold
        nop                     /* byte align to an 8 byte boundary */
	bl	_warmstart

	/* copyright notice appears at beginning of ROM (in TEXT segment) */
	.ascii   "Copyright 1984-2002 Wind River Systems, Inc."
	.align 2

cold:
	/* Setup memory controller */
	lis	r4, HI(MPC107_CONFIG_ADDR)		
	ori	r4, r4, LO(MPC107_CONFIG_ADDR)
	lis	r5, HI(MPC107_CONFIG_DATA)		
	ori	r5, r5, LO(MPC107_CONFIG_DATA)

	/* Configure PICR1 */
	lis	r3,HI( MPC107_REG_ADDR_BASE )
	ori	r3,r3,PICR1_ADDR
	stwbrx	r3,0,r4
	addis	r3,r0,0xFF14
	ori	r3,r3,0x1CC8 
	stwbrx	r3,0,r5
	sync
	lwbrx	r3,0,r5
	sync

	/* Configure PICR2 */
	lis	r3,HI( MPC107_REG_ADDR_BASE )
	ori	r3,r3,PICR2_ADDR
	stwbrx	r3,0,r4
	addis	r3,r0,0x0000
	ori	r3,r3,0x0000
	stwbrx	r3,0,r5
	sync
	lwbrx	r3,0,r5
	sync

	/*  Configure MCCR1	*/
	lis	r3,HI( MPC107_REG_ADDR_BASE )
	ori	r3,r3,MCCR1_ADDR
	stwbrx	r3,0,r4
	addis	r3,r0,0xFFC0 /* Don't set MEMGO now ! */
	ori	r3,r3,0x0000
	stwbrx	r3,0,r5
	sync
	lwbrx	r3,0,r5
	sync

	/*  Configure MCCR2 */
	lis	r3,HI( MPC107_REG_ADDR_BASE )
	ori	r3,r3,MCCR2_ADDR
	stwbrx	r3,0,r4
	addis	r3,r0,0x0000
	ori	r3,r3,0x020C
	stwbrx	r3,0,r5
	sync
	lwbrx	r3,0,r5
	sync

	/*  Configure MCCR3	 */
	lis	r3,HI( MPC107_REG_ADDR_BASE )
	ori	r3,r3,MCCR3_ADDR
	stwbrx	r3,0,r4
	addis	r3,r0,0x0230
	ori	r3,r3,0x0000
	stwbrx	r3,0,r5
	sync
	lwbrx	r3,0,r5
	sync

	/*  Configure MCCR4  */
	lis	r3,HI( MPC107_REG_ADDR_BASE )
	ori	r3,r3,MCCR4_ADDR
	stwbrx	r3,0,r4
	addis	r3,r0,0x2532
	ori	r3,r3,0x2220
	stwbrx	r3,0,r5
	sync
	lwbrx	r3,0,r5
	sync

	addis	r3,r0,0x8000	/* ADDR_80 */
	ori	r3,r3,0x0080	/* SMEMADD1 */
	stwbrx	r3,0,r4
	addis	r3,r0,0xFFFF
	ori	r3,r3,0x4000
	stwbrx	r3,0,r5
	sync
	lwbrx	r3,0,r5
	sync

	addis	r3,r0,0x8000	/* ADDR_84 */
	ori	r3,r3,0x0084	/* SMEMADD2 */
	stwbrx	r3,0,r4
	addis	r3,r0,0xFFFF
	ori	r3,r3,0xFFFF
	stwbrx	r3,0,r5
	sync
	lwbrx	r3,0,r5
	sync

	addis	r3,r0,0x8000	/* ADDR_88 */
	ori	r3,r3,0x0088	/* EXTSMEM1 */
	stwbrx	r3,0,r4
	addis	r3,r0,0x0303
	ori	r3,r3,0x0000
	stwbrx	r3,0,r5
	sync
	lwbrx	r3,0,r5
	sync

	addis	r3,r0,0x8000	/* ADDR_8C */
	ori	r3,r3,0x008c	/* EXTSMEM2 */
	stwbrx	r3,0,r4
	addis	r3,r0,0x0303
	ori	r3,r3,0x0303
	stwbrx	r3,0,r5
	sync
	lwbrx	r3,0,r5
	sync

	addis	r3,r0,0x8000	/* ADDR_90 */
	ori	r3,r3,0x0090	/* EMEMADD1 */
	stwbrx	r3,0,r4
	addis	r3,r0,0xFFFF
	ori	r3,r3,0x7F3F
	stwbrx	r3,0,r5
	sync
	lwbrx	r3,0,r5
	sync

	addis	r3,r0,0x8000	/* ADDR_94 */
	ori	r3,r3,0x0094	/* EMEMADD2 */
	stwbrx	r3,0,r4
	addis	r3,r0,0xFFFF
	ori	r3,r3,0xFFFF
	stwbrx	r3,0,r5
	sync
	lwbrx	r3,0,r5
	sync

	addis	r3,r0,0x8000	/* ADDR_98 */
	ori	r3,r3,0x0098	/* EXTEMEM1 */
	stwbrx	r3,0,r4
	addis	r3,r0,0x0303
	ori	r3,r3,0x0000
	stwbrx	r3,0,r5
	sync
	lwbrx	r3,0,r5
	sync

	addis	r3,r0,0x8000	/* ADDR_9C */
	ori	r3,r3,0x009c	/* EXTEMEM2 */
	stwbrx	r3,0,r4
	addis	r3,r0,0x0303
	ori	r3,r3,0x0303
	stwbrx	r3,0,r5
	sync
	lwbrx	r3,0,r5
	sync

	addis	r3,r0,0x8000	/* ADDR_A0 */
	ori	r3,r3,0x00a0	/* MEMBNKEN */
	stwbrx	r3,0,r4
	addis	r3,r0,0x0000
	ori	r3,r3,0x0003
	stwbrx	r3,0,r5
	sync
	lwbrx	r3,0,r5
	sync

	/* Must wait at least 100us after HRESET to issue a MEMGO */
	lis	r0,1
	mtctr	r0
memStartWait:
	bdnz	memStartWait

	/*  Enable RAM Operations through MCCR1 (MEMGO)	 */
	lis	r3,0x8000
	ori	r3,r3,0x00f0
	stwbrx	r3,r0,r4
	sync
	lwbrx	r3,0,r5
	lis	r1,0x0008
	or	r3,r1,r3
	stwbrx	r3,0,r5
	sync

	/*  Delay to let SDRAM go through 
	 *  several initialization/refresh cycles.
	*/
	lis	r3, 2
	ori	r3,r3,0xFFFF
	mtctr	r3
memStartWait_1:
	bdnz	memStartWait_1

	sync
	eieio

	li	r11, BOOT_COLD
	bl	start	/* skip over next instruction */

	.long 0x12345678 /* DEBUG */

_warmstart:
	or	r11, r3, r3	/* startType to r11 */

start:
	/* Zero-out registers: r0 & SPRGs */
	xor     r0,r0,r0
	isync
	mtspr   SPRG0,r0
	mtspr   SPRG1,r0
	mtspr   SPRG2,r0
	mtspr   SPRG3,r0

	/* Turn on FP */
	xor	r3, r3, r3
	sync
	ori     r3, r3, _PPC_MSR_FP
	sync
	mtmsr   r3
	isync

	/* Init the floating point control/status register */
	mtfsfi  7,0x0
	mtfsfi  6,0x0
	mtfsfi  5,0x0
	mtfsfi  4,0x0
	mtfsfi  3,0x0
	mtfsfi  2,0x0
	mtfsfi  1,0x0
	mtfsfi  0,0x0
	isync
	
	/* Initialize the floating point data registers to a known state */
	mfspr   r3,8
	lfs     f0,0(r3)
	lfs     f1,0(r3)
	lfs     f2,0(r3)