sysalib.s

Vxworks的bsp软件开发包(基于wrPpmc74xx)

FUNC_END(sysClearBATs)

/***************************************************************************
*
* sysInvalidateTLBs - invalidate all the BAT's register
*
* This routine will invalidate the BAT's register.
*
* SYNOPSIS
* \ss
* void sysInvalidateTLBs
*     (
*     void
*     )
* \se
*
* SEE ALSO: sysClearBATs(), sysClearBATsInvalidateTLBs(), sysMinimumBATsInit()
*
* RETURNS: N/A
*/

FUNC_BEGIN(sysInvalidateTLBs)

	isync
	/* invalidate entries within both TLBs */
	li	r3,128
	mtctr	r3		/* CTR = 32  */
	xor	r3,r3,r3	/* r3 = 0    */
	isync			/* context sync req'd before tlbie */
tlbloop:
	tlbie	r3
	addi	r3,r3,0x1000	/* increment bits 15-19 */
	bdnz	tlbloop		/* decrement CTR, branch if CTR != 0 */
	sync			/* sync instr req'd after tlbie      */
	isync			/* context sync req'd before tlbie */
	blr
FUNC_END(sysInvalidateTLBs)

/***************************************************************************
*
* sysMinimumBATsInit - initialize the minimum BAT's register
*
* This routine will initialize the minimum BAT's register.
*
* SYNOPSIS
* \ss
* void sysMinimumBATsInit
*     (
*     void
*     )
* \se
*
* NOTE: When the MMU is disabled, the processor is said to be in Real Addressing 
*       Mode. In this mode, all memory accesses are governed by a default set of 
*       bit values for the WIMG attribute bits. For data accesses, the default 
*       WIMG = 0011 and for instruction fetches default WIMG=0001. In both cases, 
*       the guarded (G) bit is set and the cache-inhibit (I) bit is clear. In 
*       other words, in real addressing mode, the entire address space of the 
*       processor is cacheable ("NOT cache-inhibited") and guarded -- independent 
*       of whether the caches are enabled or not.
*
*       The guarded attribute merely prevents out-of-order and speculative 
*       *loads*. More details are avalible in section 5.2.1.5 of the PowerPC 
*       programming environments manual for a more complete explanation of the 
*       guarded attribute. While guarded is a necessary condition for those 
*       memory spaces in which devices reside, it is not a sufficient condition. 
*       Memory accesses to devices must be both guarded and cache inhibited. 
*       Physically disabling the data cache does not provide this second, 
*       equally necessary, condition.
*
*       Above, I used the term "NOT cache-inhibited" to draw attention to an 
*       important distinction between cache-inhibited memory accesses and 
*       cacheable memory accesses that are made while the cache itself is 
*       disabled. A naive interpretation of "cacheability" holds that these two 
*       concepts are equivalent -- they are not. To prevent out-of-order 
*       *stores* to devices, we must mark the memory addresses at which those 
*       devices reside as cache inhibited. The only way to do this is to enable 
*       the MMU. So it holds that in order to enforce in-order loads AND stores, 
*       we must enable the MMU and mark the appropriate memory regions as CI & G.
*
* SEE ALSO: sysClearBATs(), sysInvalidateTLBs(), sysClearBATsInvalidateTLBs()
*
* RETURNS: N/A
*/

FUNC_BEGIN(sysMinimumBATsInit)

	lis     r3, HI(0x00000032)
	ori     r3, r3, LO(0x00000032)
	sync
	mtspr	DBAT0L,r3		
	isync

	lis     r3, HI(0x000007FF)	/* SDRAM (64M block) */ 
	ori     r3, r3, LO(0x000007FF)
	sync
	mtspr	DBAT0U,r3		
	isync

	lis     r3, HI(0xF000002A)		
	ori     r3, r3, LO(0xF000002A)
	sync
	mtspr	DBAT1L,r3		
	isync

	lis     r3, HI(0xF0001FFF)	/* Pheripherals (256M block) */
	ori     r3, r3, LO(0xF0001FFF)	/* (eeprom,serial,ictrl)    */
	sync				/* (PCI register space)     */
	mtspr	DBAT1U,r3		
	isync

	lis     r3, HI(0x8000002A)		
	ori     r3, r3, LO(0x8000002A)
	sync
	mtspr	DBAT2L,r3		
	isync

	lis     r3, HI(0x80001FFF)	/* 0x80000000 (256M block) */
	ori     r3, r3, LO(0x80001FFF)
	sync
	mtspr	DBAT2U,r3		
	isync

	lis     r3, HI(0x7000002A)		
	ori     r3, r3, LO(0x7000002A)
	sync
	mtspr	DBAT3L,r3		
	isync

	lis     r3, HI(0x70001FFF)	/* 0x70000000 (256M block) */
	ori     r3, r3, LO(0x70001FFF)
	sync
	mtspr	DBAT3U,r3		
	isync

	/* Turn on Data Relocation */
	sync
	mfmsr	r3
	ori     r3, r3, _PPC_MSR_DR
	sync
	mtmsr   r3
	isync
	blr
FUNC_END(sysMinimumBATsInit)

/**********************************************************************
* General system Input/Output ASM Routines
*
* If  INCLUDE_C_IO_ROUTINES is not defined, then it is assumed these 
* routines are supplied in assembler code ( typically in sysALib.s ).
*
*/

#ifndef INCLUDE_C_IO_ROUTINES
/*****************************************************************************
*
* sysInByte - reads a byte from an io address.
*
* This function reads a byte from a specified io address.
*
* SYNOPSIS
* \ss
* UCHAR sysInByte
*     (
*     ULONG address
*     )
* \se
*
* RETURNS: byte from address.
*/

FUNC_BEGIN(sysInByte)
	lbzx	r4,r0,r3	/* Read byte from PCI space */
	eieio			    /* Sync I/O operation */
	or	r3,r4,r4	    /* Move data read to return register */
	bclr	20,0		/* Return to caller */
FUNC_END(sysInByte)

/******************************************************************************
*
* sysOutByte - writes a byte to an io address.
*
* This function writes a byte to a specified io address.
*
* SYNOPSIS
* \ss
* void sysOutByte
*     (
*     ULONG address
*     UCHAR data
*     )
* \se
*
* RETURNS: N/A
*/

FUNC_BEGIN(sysOutByte)
	stbx	r4,r0,r3	/* Write a byte to PCI space */
	eieio			/* Sync I/O operation */
	bclr	20,0		/* Return to caller */
FUNC_END(sysOutByte)

/*****************************************************************************
*
* sysInWord - reads a word from an address, swapping the bytes.
*
* This function reads a swapped word from a specified 
* address.
*
* SYNOPSIS
* \ss
* USHORT sysInWord
*     (
*     ULONG address
*     )
* \se
*
* RETURNS: swapped 16 bit data from the specified address.
*/

FUNC_BEGIN(sysInWord)
    lhbrx   r4,r0,r3	/* Read and swap */
	eieio			/* Sync I/O operation */
	sync
	or	r3,r4,r4	    /* Move data read to return register */
    bclr    20,0		/* Return to caller */
FUNC_END(sysInWord)


/*****************************************************************************
*
* sysOutWord - writes a word to an address swapping the bytes.
*
* This function writes a swapped word to a specified 
* address.
*
* SYNOPSIS
* \ss
* void sysOutWord
*     (
*     ULONG  address
*     USHORT data
*     )
* \se
*
* RETURNS: N/A
*/

FUNC_BEGIN(sysOutWord)
    sthbrx  r4,r0,r3	/* Write with swap to address */
	eieio			    /* Sync I/O operation */
	sync
    bclr    20,0		/* Return to caller */
FUNC_END(sysOutWord)

/*****************************************************************************
*
* sysInLong - reads a long from an address.
*
* This function reads a long from a specified PCI Config Space (little-endian)
* address.
*
* SYNOPSIS
* \ss
* ULONG sysInLong
*     (
*     ULONG  address
*     )
* \se
*
* RETURNS: 32 bit data from the specified register.  Note that for PCI systems
*          if no target responds, the data returned to the CPU will be 0xffffffff.
*/

FUNC_BEGIN(sysInLong)
    lwbrx   r4,r0,r3	/* Read and swap from address */
	eieio			    /* Sync I/O operation */
	sync
	or	r3,r4,r4	    /* Move data read to return register */
    bclr    20,0		/* Return to caller */
FUNC_END(sysInLong)

/******************************************************************************
*
* sysOutLong - write a swapped long to address.
*
* This routine will store a 32-bit data item (input as big-endian)
* into an address in little-endian mode.
*
* SYNOPSIS
* \ss
* void sysOutLong
*     (
*     ULONG  address
*     ULONG  data
*     )
* \se
*
* RETURNS: N/A
*/

FUNC_BEGIN(sysOutLong)
    stwbrx  r4,r0,r3	/* store data as little-endian */
	eieio			    /* Sync I/O operation */
	sync
    bclr    20,0
FUNC_END(sysOutLong)

#endif /* INCLUDE_C_IO_ROUTINES */

/*******************************************************************************
*
* sysMemProbeSup - sysBusProbe support routine
*
* This routine is called to try to read byte, word, or long, as specified
* by length, from the specified source to the specified destination.
*
* SYNOPSIS
* \ss
* STATUS sysMemProbeSup
*     (
*     int    length,
*     char * src,
*     char * dest
*     )
* \se
*
* RETURNS: OK if successful probe, else ERROR
*/

FUNC_BEGIN(sysMemProbeSup)
	addi	p7, r4, 0	/* save length to p7 */
	xor 	r4, r4, r4	/* set return status */
	cmpwi	p7, 1		/* check for byte access */
	bne 	sbpShort	/* no, go check for short word access */
	lbz 	p6, 0(r3)	/* load byte from source */
	stb 	p6, 0(p2)	/* store byte to destination */
	isync			/* enforce for immediate exception handling */
	blr
sbpShort:
	cmpwi	p7, 2		/* check for short word access */
	bne 	sbpWord 	/* no, check for word access */
	lhz 	p6, 0(r3)	/* load half word from source */
	sth 	p6, 0(p2)	/* store half word to destination */
	isync			/* enforce for immediate exception handling */
	blr
sbpWord:
	cmpwi	p7, 4		/* check for short word access */
	bne 	sysProbeExc 	/* no, check for double word access */
	lwz 	p6, 0(r3)	/* load half word from source */
	stw 	p6, 0(p2)	/* store half word to destination */
	isync			/* enforce for immediate exception handling */
	blr
sysProbeExc:
	li	r4, -1		/* shouldn't ever get here, but... */
	blr
FUNC_END(sysMemProbeSup)

#ifdef INCLUDE_VWARE_LAUNCH
#include "sysPpcAVware.s"
#endif /* INCLUDE_VWARE_LAUNCH */

#ifdef INCLUDE_CACHE_SUPPORT
#include "sysACache.s"
#include "sysCacheLockALib.s"
#endif /* INCLUDE_CACHE_SUPPORT */