wrppmc74xx.h

Vxworks的bsp软件开发包(基于wrPpmc74xx)

/* wrPpmc74xx.h - board header */

/* Copyright 1984-2002 Wind River Systems, Inc. */

/*
modification history
--------------------
01e,16may02,gjc  Adding AUX Timer
01d,04feb02,g_h  Move L2 cache macros to sysCache.h
01c,23oct01,g_h  Cleaning for T2.2
01b,16sep01,dat  Use of WRS_ASM macro
01a,12may01,g_h  create from ppmc7xx.h rev 01b
*/

/*
This file contains I/O addresses and related constants for the board.
*/

#ifndef __INCwrPpmc74xxh
#define __INCwrPpmc74xxh

#ifdef __cplusplus
extern "C" {
#endif

/* Local I/O address map */

#define SDRAM_BASE_ADS          0x00000000
#define USR_LED_BASE_ADRS       0x78000000
#define USR_LED_REG_SIZE        0x00001000
#define NS16550_BASE_ADRS       0x7C000000
#define NS16550_REG_SIZE        0x00001000
#define EUMB_BASE_ADRS          0xFCE00000
#define EUMB_REG_SIZE           0x00080000
#define FLASH_BASE_ADRS         0xFFC00000
#define FLASH_MEM_SIZE          0x00400000
#define MAILBOX_BASE_ADRS       0xFF000000
#define MAILBOX_REG_SIZE        0x00010000

#define BUS_TYPE        BUS_TYPE_PCI    /* board bus interface  */

/* Timer constants */

#define	SYS_CLK_RATE_MIN    3    /* minimum system clock rate */
#define	SYS_CLK_RATE_MAX    5000 /* maximum system clock rate */
#define	AUX_CLK_RATE_MIN    3    /* minimum auxiliary clock rate */
#define	AUX_CLK_RATE_MAX    5000 /* maximum auxiliary clock rate */

/* create a single macro INCLUDE_MMU */

#if defined(INCLUDE_MMU_BASIC) || defined(INCLUDE_MMU_FULL)
#define INCLUDE_MMU
#endif

/* Only one can be selected, FULL overrides BASIC */

#ifdef INCLUDE_MMU_FULL
#   undef INCLUDE_MMU_BASIC
#endif

/* serial ports (COM1,COM2) */

#define N_SIO_CHANNELS          1 /* Number of serial I/O channels */
#define N_UART_CHANNELS         N_SIO_CHANNELS
#define COM1_BASE_ADR           NS16550_BASE_ADRS
#define COM1_INT_VEC            4
#define COM1_INT_LVL            4
#define UART_XTAL_FREQ          3686400
#define DEFAULT_BAUD_RATE       9600
#define UART_REG_ADDR_INTERVAL  8

/* Embedded Utilities Memory Block  */

#define EUMBBAR         0x0078  /* offest of EUMBBAR in PCI config space */

/*
 * PCI part 
 */

#if (_BYTE_ORDER == _BIG_ENDIAN)
#define PCISWAP(x)              LONGSWAP(x) /* processor big endian */
#define BYTE_SWAP_16_BIT(x)     ((LSB(x) << 8) | MSB(x))
#else
#define PCISWAP(x)              (x) /* processor little endian */
#define BYTE_SWAP_16_BIT(x)     (x)
#endif /* _BYTE_ORDER == _BIG_ENDIAN */

/*
 * mpc107 PCI Configuration Defines
 */
#define HOST_BRIDGE_NUM         0
#define HOST_BRIDGE_IDSEL       19

#define PCI_ADDRESS_REGISTER    0xFEC00000 /* PCI Address Register  */
#define PCI_DATA_REGISTER       0xFEE00000 /* PCI Data Register     */
#define PCI_IO_BASE             0xFE000000 /* PCI IO Start Address  */
#define PCI_IO_SIZE             0x00C00000 /* PCI IO Size	      */
#define PCI_MEM_BASE            0x80000000 /* PCI MEM Start Address */
#define PCI_MEM_SIZE            0x7D000000 /* PCI MEM Size	      */

#define PCI_IO_END          (PCI_IO_BASE + PCI_IO_SIZE - 1)
#define PCI_MEM_END         (PCI_MEM_BASE + PCI_MEM_SIZE - 1)

#define MPC107_CONFIG_ADDR      PCI_ADDRESS_REGISTER
#define MPC107_CONFIG_DATA      PCI_DATA_REGISTER
#define MPC107_REG_ADDR_BASE    PCI_MEM_BASE

/*
 * BRD_PCIMEM_CPU2PCI(addr, bridge)
 *     mapping the PCI memory address from CPU view to PCI view
 *
 * BRD_PCIIO_CPU2PCI(addr, bridge)
 *     mapping the PCI IO address from CPU view to PCI view
 *
 * BRD_PCIIO_PCI2CPU(addr, bridge)
 *     mapping the PCI IO address from PCI view to CPU view
 *
 * BRD_PCIMEM_PCI2CPU(addr, bridge)
 *     mapping the PCI memory address from PCI view to CPU view
 */
#define BRD_PCIIO_CPU2PCI(addr, bridge)  ((ULONG)addr & 0x00ffffff)
#define BRD_PCIIO_PCI2CPU(addr, bridge)  ((ULONG)addr | PCI_IO_BASE)
#define BRD_PCIMEM_CPU2PCI(addr, bridge) ((ULONG)addr)
#define BRD_PCIMEM_PCI2CPU(addr, bridge) ((ULONG)addr)

#define CPU2DEV_ADDR(x)     PCISWAP( (BRD_PCIMEM_CPU2PCI(x,0)) )
#define DEV2CPU_ADDR(x)     (void*)BRD_PCIMEM_PCI2CPU(PCISWAP((x)),0)

/*
 * PCI Autoconfig Configuration Defines - Mandatory stuff that must be defined in
 * order to use vWare's PCI Autoconfig.
 */
#define PCI_MAX_DEV         30
#define PCI_MAX_BUS         255
#define PCI_MAX_FUNC        8

#define PCI_PP_MEM_START    0x80000000 /* PCI Auto Config Memory Start Address */
#define PCI_PP_MEM_SIZE     0x20000000 /* PCI Auto Config Memory Size	     */
#define PCI_PP_IO_START     0xFE800000 /* PCI Auto Config IO Start Address     */
#define PCI_PP_IO_SIZE      0x00200000 /* PCI Auto Config IO Size 2MB          */
#define PCI_PP_IO16_START   0xFE008000
#define PCI_PP_IO16_SIZE    (0xFE010000-PCI_PP_IO16_START) /* 64KB */


#define CPU_PCI_MEM_ADRS        PCI_PP_MEM_START /* 32 bit prefetchable memory base addres of PCI mem */
#define CPU_PCI_MEM_SIZE        PCI_PP_MEM_SIZE  /* 32 bit prefetchable memory size  */
#define CPU_PCI_CNFG_ADRS       0xF0000000       /* 32 bit PCI plag & play memory base addres of PCI conf */
#define CPU_PCI_CNFG_SIZE       0x02000000       /* 32 bit PCI plag & play memory size  */
#define CPU_PCI_IO_ADRS         PCI_IO_BASE      /* base addres of PCI IO */
#define CPU_PCI_IO_SIZE         0x01000000  

#define PCI_MSTR_MEMIO_LOCAL    PCI_PP_MEM_START /* CPU to PCI memio */
#define PCI_MSTR_MEMIO_BUS      PCI_PP_MEM_START /* PCI bus view */
#define PCI_SLV_MEM_LOCAL       0x00000000 

/* PCI (non-prefetchable) memory adrs to CPU (60x bus) adrs */

#define PCI_MEMIO2LOCAL(x)        ((int)(x)+PCI_MSTR_MEMIO_LOCAL-PCI_MSTR_MEMIO_BUS)


/* 60x bus adrs to PCI (non-prefetchable) memory address */

#define LOCAL2PCI_MEMIO(x)        ((int)(x) + PCI_SLV_MEM_LOCAL)

#define MPC107PCI_BRIDGE            0
#define INTEL21154PCI_BRIDGE        1

#define PCI_INTA_MPC107_IRQ0        0
#define PCI_INTB_MPC107_IRQ1        1 
#define PCI_INTC_MPC107_IRQ2        2
#define PCI_INTD_MPC107_IRQ3        3

#define EXPANTION_BOARD_1PCI_SLOT 12   
#define EXPANTION_BOARD_2PCI_SLOT 13
#define EXPANTION_BOARD_3PCI_SLOT 14
#define EXPANTION_BOARD_4PCI_SLOT 15

/* Define if the PCI interrupt on the expantion board taid */

#define INT_ON_EXPANTION_BOARD_TAID

/* NvRam on FLASH macros */

#define ONE_K                   1024
#define FLASH_SECTOR_SIZE       (128 * ONE_K * 2)

/* Osillator macros */

#define OSCILLATOR_166MHZ        166000000 /* Bus Speeds */
#define OSCILLATOR_99MHZ          99000000
#define OSCILLATOR_66MHZ          66000000
#define OSCILLATOR_33MHZ          33000000

#define SYS_CPU_FREQ              OSCILLATOR_99MHZ 
#define MPC107_CLK_RATE           OSCILLATOR_99MHZ  /* ppmc 750/755/7400 User's Guide*/

/* decrementer constants */

#define DEC_CLOCK_FREQ          SYS_CPU_FREQ/2
#define DEC_CLK_TO_INC          2

#define SYS_CLK_TICKS_PER_SECOND  60      /* default 60 ticks/second */

#define DELTA(a,b)              (abs((int)a - (int)b))

/* PCI Bus Frequency */
#define DEFAULT_BUS_CLK_FREQ    33000000 /* 33.00 Mhz  */

/*
 * Miscellaneous definitions go here. For example, macro definitions
 * for various devices.
 */

#if CPU==PPC603
#define WRONG_CPU_MSG "PPC603 VxWorks image cannot run on a PPC604!\n";
#else
#define WRONG_CPU_MSG "Unsupported processor type for this board.\n";
#endif

#define CPU_TYPE            ((vxPvrGet() >> 12) & 0xffff)
#define CPU_TYPE_750        0x80 /* PPC 750 CPU */
#define CPU_TYPE_755        0x83 /* PPC 755 CPU */
#define CPU_TYPE_7400       0xC0 /* PPC 7400 Altivec */
#define CPU_TYPE_7410       0xC1 /* PPC 7410 Altivec */

/* MPC74xx (Max) Support */

/* Max SPRs */

#define VRSAVE                    256  /* VMX Save register */
#define UBAMR                     935  /* Performance monitor mask */
#define UMMCR2                    928  /* Performance monitor control */
#define BAMR                      951  /* Performance monitor mask */
#define MMCR2                     944  /* Performance monitor control */
#define MSSCR0                    1014 /* Memory Subsystem control */
#define MSSCR1                    1015 /* Memory Subsystem debug */
#define PIR                       1023 /* Processor ID register */

/* Max HID0 bit definitions */

#define _PPC_HID0_NOPDST          0x2  /* Nop dst, dstt, dstst, &dststt*/
#define _PPC_HID0_NOPTI           0x1  /* Nop dcbt and dbtst */

/* AltiVec Exceptions */

#define _EXC_VMX_UNAVAIL          0x0f20 /* VMX Unavailable Exception */
#define _EXC_VMX_ASSIST           0x1600 /* VMX Assist Exception */
#define SIZEOF_EXCEPTION          0x0030 /* VxWorks Exc is 48 bytes Max*/

/* Extra 4 IBAT register for the MPC755 */

#define IBAT4U              560 /* instruction BAT register */
#define IBAT4L              561 /* instruction BAT register */
#define IBAT5U              562 /* instruction BAT register */
#define IBAT5L              563 /* instruction BAT register */
#define IBAT6U              564 /* instruction BAT register */
#define IBAT6L              565 /* instruction BAT register */
#define IBAT7U              566 /* instruction BAT register */
#define IBAT7L              567 /* instruction BAT register */

/* Extra 4 DBAT register for the MPC755 */

#define DBAT4U              568 /* data BAT register */
#define DBAT4L              569 /* data BAT register */
#define DBAT5U              570 /* data BAT register */
#define DBAT5L              571 /* data BAT register */
#define DBAT6U              572 /* data BAT register */
#define DBAT6L              573 /* data BAT register */
#define DBAT7U              574 /* data BAT register */
#define DBAT7L              575 /* data BAT register */

#ifndef _MMU_UBAT_BL_512M
#define _MMU_UBAT_BL_512M       0x00003ffc      /* block size 512M          */
#endif  _MMU_UBAT_BL_512M

/* General */

#undef  EIEIO_SYNC
#define EIEIO_SYNC                WRS_ASM (" eieio; sync")

#undef  EIEIO
#define EIEIO                     WRS_ASM (" eieio")

#define REG_8BIT  1
#define REG_16BIT 2
#define REG_32BIT 4

#endif  /* __INCwrPpmc74xxh */