syslib.c

vxworks的bsp开发包(基于POWERPC的PRPMC800)

/* sysLib.c - Motorola PrPMC800 board series system-dependent library */

/* Copyright 1984-2001 Wind River Systems, Inc. */
/* Copyright 1996-2001 Motorola, Inc. All Rights Reserved */

/*
modification history
--------------------
02f,17jul02,dtr  Change INCLUDE_HARRIER_AUXCLK to INCLUDE_AUX_CLK.
02e,13may02,dtr  Update for SM for Tornado 2.2. SPR 73457.
02d,31jan02,kab  Remove obsolete vmxExcLoad
02c,17jan02,dtr  Fixing diab warnings.
02b,05dec01,dtr  Wrapping dec2155x functions with ifdef.
02a,25nov01,dtr  Tidy up.
01z,16nov01,scb  Shared memory fixes using mcpn765 as carrier.
01y,10oct01,scb  Fixes for shared memory support.
01x,28sep01,srr  Removed sysEnd.c and cleaned up #include alignment.
01w,17sep01,srr  Removed erroneous INCLUDE_SHOW_ROUTINES.
01v,31jul01,srr  Added 82543 Gigabit Ethernet support.
01u,02jul01,scb  Fix bugs in sysBusToLocalAdrs() and sysLocalToBusAdrs().
01t,18jun01,srr  Added Harrier DMA support.
01s,14jun01,srr  Change address for Slave to wait on host to be volatile.
01r,12jun01,srr  Updated routine for Slave to wait on host enumeration.
01q,17may01,blk  Add support for harrier II.
01p,07dec00,krp  Added support for Watchdog Timer
01o,17nov00,dmw  Added slave Ethernet support.
01n,14nov00,dmw  Added slave PCI initialization.
01m.27oct00,dmw  Added Xport MMU support and fixed sysSysconAsserted.
01l,16oct00,dmw  Enabled PCI bridge init functions.
01k,10oct00,dmw  Added Nitro IDs.
01j,09oct00,dmw  Changed sysPhysMemDesc for MMU support.
01i,08oct00,dmw  Stubbed sysHarrierPhbInit for board bring up.
01h,18sep00,dmw  Removed dependancy on PRPMC800 define.
01g,18sep00,krp  Added support for Harrier MPIC support
01f,12sep00,dmw  Corrected board fail bit.
01e,11sep00,dmw  Changed sense of sysSysconAsserted (for Harrier).
01d,08sep00,dmw  Added dual-address I2C EEPROM accesses.
01c,07sep00,dmw  Updated I2C access function names.
01b,01aug00,dmw  Removed calls to sysNetHwInit and sysNetHwInit2.
01a,01aug00,dmw  Written (from version 01g of mcpn765/sysLib.c).
*/

/*
DESCRIPTION
This library provides board-specific routines.  The chip drivers included are:

    i8250Sio.c      - Intel 8250 UART driver 
    ppcDecTimer.c   - PowerPC decrementer timer library (system clock)
    byteNvRam.c     - byte-oriented generic non-volatile RAM library
    pciConfigLib.c  - PCI configuration library
    dec2155xCpci.c  - Dec/Intel non-transparent PCI-to-PCI bridge library
    HarrierAuxClk.c - Harrier timer library (auxiliary clock)
    ataDrv.o        - ATA/EIDE interface driver
    sysMpic.c       - Mpic Interrupt Controller

INCLUDE FILES: sysLib.h

SEE ALSO:
.pG "Configuration"
*/

/* includes */

#include "vxWorks.h"
#include "pci.h"
#include "memLib.h"
#include "cacheLib.h"
#include "sysLib.h"
#include "config.h"
#include "string.h"
#include "intLib.h"
#include "esf.h"
#include "excLib.h"
#include "logLib.h"
#include "taskLib.h"
#include "vxLib.h"
#include "tyLib.h"
#include "arch/ppc/archPpc.h"
#include "arch/ppc/mmu603Lib.h"
#include "arch/ppc/vxPpcLib.h"
#include "arch/ppc/excPpcLib.h"
#include "private/vmLibP.h"
#include "drv/pci/pciConfigLib.h"
#include "harrier.h"

#ifdef INCLUDE_DEC2155X
#   include "dec2155xCpci.h"
#endif

#include "drv/pci/pciAutoConfigLib.h"

#include "end.h"
#ifdef INCLUDE_ALTIVEC
#include "altivecLib.h"
IMPORT int       (* _func_altivecProbeRtn) () ;
#endif /* INCLUDE_ALTIVEC */

/* defines */

#define ZERO    0

#define DEFAULT_TAS_CHECKS    10        /* rechecks for soft tas */
#define TAS_CONST             0x80

#ifdef INCLUDE_BPE

#   define _PPC_HID0_DBP _PPC_HID0_ECPC

#endif /* INCLUDE_BPE */

#ifdef INCLUDE_DPM    /* dynamic power management */

#   define _PPC_HID0_BIT_DPM    11 /* dynamic power management bit */
#   define _PPC_HID0_DPM        (1<<(31-_PPC_HID0_BIT_DPM))

#endif /* INCLUDE_DPM */

#define MONARCH_HARRIER_PCI_BUS_NUMBER		0
#define MONARCH_HARRIER_PCI_DEV_NUMBER		0
#define MONARCH_HARRIER_PCI_FCN_NUMBER		0

#define HARRIER_RDWR_ENA        (CPU2PCI_ATTR_REN | CPU2PCI_ATTR_WEN)

#define SYS_DECS_DRAM_INDEX     1

/* structures */

typedef struct mailboxInfo
    {
    BOOL    connected;
    FUNCPTR routine;
    int     arg;
    } MAILBOX_INFO;

typedef struct harrierWinStruct
    {
    UINT32 winType;   /* mem or i/o */
    UINT32 winBase;   /* start of window */
    UINT32 winLimit;  /* end of window */
    } HARRIER_WIN_STRUCT;

typedef struct harrierOffsetsOutbound
    {
    UINT32 range;
    UINT32 offset;
    UINT32 attr;
    } HARRIER_OFFSETS_OUTBOUND;

typedef struct harrierOffsetsInbound
    {
    UINT32 base;
    UINT32 size;
    UINT32 offset;
    UINT32 attr;
    } HARRIER_OFFSETS_INBOUND;

HARRIER_OFFSETS_OUTBOUND    sysHarrierCpuWinOff [] =
    {
        {
        (HARRIER_OUTBOUND_TRANSLATION_ADDR_0_REG),
        (HARRIER_OUTBOUND_TRANSLATION_ADDR_0_REG + 
                     HARRIER_OUTBOUND_TRANSLATION_OFFSETINFO_OFFSET),
        (HARRIER_OUTBOUND_TRANSLATION_ADDR_0_REG +
                     HARRIER_OUTBOUND_TRANSLATION_ATTRIBUTE_OFFSET)
        },

        {
        (HARRIER_OUTBOUND_TRANSLATION_ADDR_1_REG),
        (HARRIER_OUTBOUND_TRANSLATION_ADDR_1_REG +
                     HARRIER_OUTBOUND_TRANSLATION_OFFSETINFO_OFFSET),
        (HARRIER_OUTBOUND_TRANSLATION_ADDR_1_REG + 
                     HARRIER_OUTBOUND_TRANSLATION_ATTRIBUTE_OFFSET)
        },
    
        {
        (HARRIER_OUTBOUND_TRANSLATION_ADDR_2_REG),
        (HARRIER_OUTBOUND_TRANSLATION_ADDR_2_REG +
                     HARRIER_OUTBOUND_TRANSLATION_OFFSETINFO_OFFSET),
        (HARRIER_OUTBOUND_TRANSLATION_ADDR_2_REG +
                     HARRIER_OUTBOUND_TRANSLATION_ATTRIBUTE_OFFSET)
        },
    
        {
        (HARRIER_OUTBOUND_TRANSLATION_ADDR_3_REG),
        (HARRIER_OUTBOUND_TRANSLATION_ADDR_3_REG + 
                     HARRIER_OUTBOUND_TRANSLATION_OFFSETINFO_OFFSET),
        (HARRIER_OUTBOUND_TRANSLATION_ADDR_3_REG +
                     HARRIER_OUTBOUND_TRANSLATION_ATTRIBUTE_OFFSET)
        }

    };

HARRIER_OFFSETS_INBOUND    sysHarrierPciWinOff [] =
    {

        {
        (HARRIER_INBOUND_TRANSLATION_BASE_ADDRESS_0), 
        (HARRIER_INBOUND_TRANSLATION_SIZE_0_REG), 
        (HARRIER_INBOUND_TRANSLATION_OFFSET_0_REG), 
        (HARRIER_INBOUND_TRANSLATION_ATTRIBUTE_0)
        },

        {
        (HARRIER_INBOUND_TRANSLATION_BASE_ADDRESS_1), 
        (HARRIER_INBOUND_TRANSLATION_SIZE_1_REG), 
        (HARRIER_INBOUND_TRANSLATION_OFFSET_1_REG), 
        (HARRIER_INBOUND_TRANSLATION_ATTRIBUTE_1)
        },

        {
        (HARRIER_INBOUND_TRANSLATION_BASE_ADDRESS_2), 
        (HARRIER_INBOUND_TRANSLATION_SIZE_2_REG), 
        (HARRIER_INBOUND_TRANSLATION_OFFSET_2_REG), 
        (HARRIER_INBOUND_TRANSLATION_ATTRIBUTE_2)
        },

        {
        (HARRIER_INBOUND_TRANSLATION_BASE_ADDRESS_3), 
        (HARRIER_INBOUND_TRANSLATION_SIZE_3_REG), 
        (HARRIER_INBOUND_TRANSLATION_OFFSET_3_REG), 
        (HARRIER_INBOUND_TRANSLATION_ATTRIBUTE_3)
        }
    };

#define HARRIER_CPU_WIN_CNT \
        (sizeof (sysHarrierCpuWinOff)/ sizeof (HARRIER_OFFSETS_OUTBOUND))
#define HARRIER_PCI_WIN_CNT \
        (sizeof (sysHarrierPciWinOff)/ sizeof (HARRIER_OFFSETS_INBOUND))
#define HARRIER_WIN_CNT (HARRIER_CPU_WIN_CNT + HARRIER_PCI_WIN_CNT)

/* globals */

UINT    mpicBaseAdrs;
static char * sysPhysMemSize = NULL;    /* ptr to top of mem + 1 */

/*
 * sysBatDesc[] is used to initialize the block address translation (BAT)
 * registers within the PowerPC 603/604 MMU.  BAT hits take precedence
 * over Page Table Entry (PTE) hits and are faster.  Overlap of memory
 * coverage by BATs and PTEs is permitted in cases where either the IBATs
 * or the DBATs do not provide the necessary mapping (PTEs apply to both
 * instruction AND data space, without distinction).
 *
 * The primary means of memory control for VxWorks is the MMU PTE support
 * provided by vmLib and cacheLib.  Use of BAT registers will conflict
 * with vmLib support.  User's may use BAT registers for i/o mapping and
 * other purposes but are cautioned that conflicts with cacheing and mapping
 * through vmLib may arise.  Be aware that memory spaces mapped through a BAT
 * are not mapped by a PTE and any vmLib() or cacheLib() operations on such
 * areas will not be effective, nor will they report any error conditions.
 *
 * Note: BAT registers can be disabled if the VS and VP bits are both clear
 * in the upper BAT register of each pair.  In the default configuration
 * (coded below) the VS and VP bits are cleared and thus the BAT registers
 * are disabled.  To enable the BAT registers, change the construct coded
 * below the upper BAT register:
 *
 *.CS
 *          & ~(_MMU_UBAT_VS | _MMU_UBAT_VP)),
 *          which clears VS and VP
 *                to
 *          | (_MMU_UBAT_VS | _MMU_UBAT_VP)),
 *          which sets VS and VP
 *.CE
 *
 * With this in mind, it is recommended that the BAT registers be used
 * to map LARGE memory areas external to the processor if possible.
 * If not possible, map sections of high RAM and/or PROM space where
 * fine grained control of memory access is not needed.  This has the
 * beneficial effects of reducing PTE table size (8 bytes per 4k page)
 * and increasing the speed of access to the largest possible memory space.
 * Use the PTE table only for memory which needs fine grained (4KB pages)
 * control or which is too small to be mapped by the BAT regs.
 *
 * The BAT configuration for 4xx/6xx-based PPC boards is as follows:
 * All BATs point to PROM/FLASH memory so that end customer may configure
 * them as required.
 *
 * [Ref: chapter 7, PowerPC Microprocessor Family: The Programming Environments]
 */

UINT32 sysBatDesc [2 * (_MMU_NUM_IBAT + _MMU_NUM_DBAT)] =
    {
    /* I BAT 0 */

    ((ROM_BASE_ADRS & _MMU_UBAT_BEPI_MASK) | (_MMU_UBAT_BL_1M &
    ~(_MMU_UBAT_VS & _MMU_UBAT_VP))),
    ((ROM_BASE_ADRS & _MMU_LBAT_BRPN_MASK) | _MMU_LBAT_PP_RW |
    _MMU_LBAT_CACHE_INHIBIT),

    /* I BAT 1 */

    0, 0,

    /* I BAT 2 */

    0, 0,

    /* I BAT 3 */

    0, 0,

    /* D BAT 0 */

    0, 0,

    /* D BAT 1 */

    0, 0,

    /* D BAT 2 */

    0, 0,

    /* D BAT 3 */

    0, 0
    };

/*
 * sysPhysMemDesc[] is used to initialize the Page Table Entry (PTE) array
 * used by the MMU to translate addresses with single page (4k) granularity.
 * PTE memory space should not, in general, overlap BAT memory space but
 * may be allowed if only Data or Instruction access is mapped via BAT.
 *
 * Address translations for local RAM, memory mapped PCI bus and local
 * PROM/FLASH are set here.
 *
 * PTEs are held, strangely enough, in a Page Table.  Page Table sizes are
 * integer powers of two based on amount of memory to be mapped and a
 * minimum size of 64 kbytes.  The MINIMUM recommended Page Table sizes
 * for 32-bit PowerPCs are:
 *
 *.CS
 * Total mapped memory        Page Table size
 * -------------------        ---------------
 *        8 Meg                 64 K
 *       16 Meg                128 K
 *       32 Meg                256 K
 *       64 Meg                512 K
 *      128 Meg                  1 Meg
 *     .                .
 *     .                .
 *     .                .
 *
 * [Ref: chapter 7, PowerPC Microprocessor Family: The Programming Environments]
 *.CE
 *
 */

PHYS_MEM_DESC sysPhysMemDesc [] =
    {
    {
    /* Vector Table and Interrupt Stack */

    (void *) LOCAL_MEM_LOCAL_ADRS,
    (void *) LOCAL_MEM_LOCAL_ADRS,
    RAM_LOW_ADRS,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE |
    VM_STATE_MASK_MEM_COHERENCY,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE |
    VM_STATE_MEM_COHERENCY
    },

    {
    /* 
     * Local DRAM - Must be SYS_DECS_DRAM_INDEX entry in sysPhysMemDesc for 
     * Auto Sizing 
     */

    (void *) RAM_LOW_ADRS,
    (void *) RAM_LOW_ADRS,
    LOCAL_MEM_SIZE -  RAM_LOW_ADRS,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE |
    VM_STATE_MASK_MEM_COHERENCY,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE |
    VM_STATE_MEM_COHERENCY
    },

    /*
     * Access to PCI ISA memory space.
     */

    {
    (void *) PCI_MSTR_MEMIO_LOCAL,
    (void *) PCI_MSTR_MEMIO_LOCAL,
    PCI_MSTR_MEMIO_SIZE,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE |
    VM_STATE_MASK_GUARDED,
    VM_STATE_VALID    | VM_STATE_WRITABLE     | VM_STATE_CACHEABLE_NOT |
    VM_STATE_GUARDED
    },

    /*
     * Access to PCI memory space.
     * Note: Guarding should not be required since
     * memory is well-behaved (no side-effects on read or write)
     */

    {
    (void *) PCI_MSTR_MEM_LOCAL,
    (void *) PCI_MSTR_MEM_LOCAL,
    PCI_MSTR_MEM_SIZE,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
    VM_STATE_VALID    | VM_STATE_WRITABLE     | VM_STATE_CACHEABLE_NOT
    },

    /*
     * Access to PCI memory space at PCI address zero.
     * This will allow the PrPMC to access DRAM on the processor board
     * on which the PrPMC is mounted if that processor board maps its
     * DRAM to PCI address zero.
     * Note: Guarding should not be required since
     * memory is well-behaved (no side-effects on read or write)
     */

    {
    (void *) (PCI_MSTR_ZERO_LOCAL),
    (void *) (PCI_MSTR_ZERO_LOCAL),
    PCI_MSTR_ZERO_SIZE,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
    VM_STATE_VALID    | VM_STATE_WRITABLE     | VM_STATE_CACHEABLE_NOT
    },

    {
    (void *) PRPMC800_XPORT0_ADDR,
    (void *) PRPMC800_XPORT0_ADDR,
    PRPMC800_XPORT0_SIZE,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT
    },

    {
    (void *) PRPMC800_XPORT1_ADDR,
    (void *) PRPMC800_XPORT1_ADDR,
    PRPMC800_XPORT1_SIZE,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT
    },

#ifdef  INCLUDE_PRPMC800XT    
    {
    (void *) PRPMC800_XPORT2_ADDR,
    (void *) PRPMC800_XPORT2_ADDR,
    PRPMC800_XPORT2_SIZE,
    VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE | VM_STATE_MASK_CACHEABLE,
    VM_STATE_VALID      | VM_STATE_WRITABLE      | VM_STATE_CACHEABLE_NOT
    },