harrierdma.c

vxworks的bsp开发包(基于POWERPC的PRPMC800)

/* harrierDma.c - Support for the Harrier's DMA Controller */

/* Copyright 2001 Motorola, Inc., All Rights Reserved */

/*
modification history
--------------------
01a,14jun01,srr  Initial Creation.
*/


/*
DESCRIPTION
The Harrier DMA driver will support multiple Harriers and consist of the
following seven routines:
	
harrierDmaInit   - Initialize DMA and attach DMA Interrupt Handler.
harrierDmaIntr   - Clear the interrupt and capture completion status.
harrierDmaStart  - Configure and start the DMA controller.
harrierDmaStatus - Read and return the DMA status register.
harrierDmaAbort  - Initiate an abort of the current DMA operation.
harrierDmaPause  - Initiate a pause of the current DMA operation.
harrierDmaResume - Resume a previously paused DMA operation.
	
Harrier has a single channel DMA Controller that facilitates the transfer of
large blocks of data without processor intervention.  This driver supports
both the Direct and Linked-List Modes of operation.  It also covers the six
directions for data movement in a DMA transfer:
   PowerPC to PCI, PCI to PowerPC, PowerPC to PowerPC, PCI to PCI,
   Data Pattern to PowerPC, Data Pattern to PCI.

Harrier does not snoop the PowerPC bus for data held within the DMA FIFO,
therefore caution should be exercised when using the DMA controller to move
data within coherent memory space.

The Harrier DMA driver must be initialized for each Harrier it will be executed
on.  This will usually be configured in sysHwInit2 with separate commands to
harrierDmaInit for each Harrier instance.  The customer will configure DMA
Descriptor Lists according to the description below and pass the address of
the first as a parameter to the harrierDmaStart routine.

The user has three options for being notified of the completion of a DMA
transaction depending on the contents of the userHandler parameter of
harrierDmaStart.  The first is to have the DMA start routine wait for the
done interrupt which will return the contents of the DMA status register
(userHandler == WAIT_FOREVER).  The second is to provide a routine for the
DMA interrupt handler to call upon completion which must follow the rules
for executing inside an ISR by not calling waits, prints, etc
(userHander == user routine).  The third is to have DMA start return
immediately so the user task can proceed with its execution and then call
harrierDmaStatus later to get the results (userHandler == 0).

The DMA Descriptor List contains six fields which must be cache-line aligned
and is described here in detail.  If the Descriptor List Next Link Address
(DNLA) entry is 0, the Harrier DMA driver will configure the transfer for
Direct Mode.

.CS
                        ------------------------------------------
                        |            Bit Positions               |
             -----------------------------------------------------
             | Offset   |0               31|32                 63|
             -----------------------------------------------------
             |  0x00    |      DSAD        |         DSAT        |
             -----------------------------------------------------
             |  0x08    |      DDAD        |         DDAT        |
             -----------------------------------------------------
             |  0x10    |      DNLA        |         DCNT        |
             -----------------------------------------------------
.CE

DSAD bits 0:31
    This contains the 32-bit DMA transfer source address.
    This is either a PCI address, PowerPC address or a data pattern.
    If it is a byte data pattern, the byte is in bit positions 24 thru 31.


.CS
DSAT bits  2:3  Type
             7  No Increment (NIN)
             15 Pattern Size (PSZ)
          20:23 PCI Read Command (PRC)
             29 Cache-Line Read Invalidate (CRI)
             31 Global (GBL)
.CE

    This contains the source attributes for a DMA transfer.

    Type - Indicates type of source for a transfer:
.CS
                                 ---------------------------------
                                 |       Applicable Fields       |
             -----------------------------------------------------
             | Type | DMA Source |  NIN  |  PSZ  |  CRI  |  GBL  |
             -----------------------------------------------------
             |  00  | PowerPC bus|       |       |   X   |   X   |
             -----------------------------------------------------
             |  01  |   PCI bus  |   X   |       |       |       |
             -----------------------------------------------------
             |  1x  |Data Pattern|   X   |   X   |       |       |
             -----------------------------------------------------

    NIN - If set, source increment will be disabled.
    PSZ - If set, data pattern transfers will be bytes.
    PRC - If Type is set to PCI bus (01), the command used
          during PCI read cycles is:
             -----------------------------------------------------
             |  PRC  |             PCI Command                   |
             -----------------------------------------------------
             | 0010  |               IO Read                     |
             -----------------------------------------------------
             | 0110  |             Memory Read                   |
             -----------------------------------------------------
             | 1100  |         Memory Read Multiple              |
             -----------------------------------------------------
             | 1110  |           Memory Read Line                |
             -----------------------------------------------------

    CRI - If set, DMA will use "Read-with-intent-to-modify" during
          PowerPC read cycles.  Else "Read" transfer type will be used
          which will retain cached data in the E and S states.

    GBL - If set, DMA will assert GBL_ pin during PowerPC read cycles to
          allow the processor to snoop DMA.
.CE


DDAD bits 0:31
    This contains the 32-bit DMA transfer destination address.
    This is either a PCI or PowerPC address.


.CS
DDAT bits    3  Type
             7  No Increment (NIN)
          20:23 PCI Write Command (PWC)
             30 Cache-Line Write Flush (CWF)
             31 Global (GBL)
.CE

    This contains the destination attributes for a DMA transfer.

    Type - Indicates type of source for a transfer:
.CS
                                 ---------------------------------
                                 |       Applicable Fields       |
             -----------------------------------------------------
             | Type | DMA Source |  NIN  |       |  CFW  |  GBL  |
             -----------------------------------------------------
             |   0  | PowerPC bus|       |       |   X   |   X   |
             -----------------------------------------------------
             |   1  |   PCI bus  |   X   |       |       |       |
             -----------------------------------------------------

    NIN - If set, destination increment will be disabled.
    PWC - If Type is set to PCI bus (01), the command used
          during PCI write cycles is:
             -----------------------------------------------------
             |  PRC  |             PCI Command                   |
             -----------------------------------------------------
             | 0011  |               IO Write                    |
             -----------------------------------------------------
             | 0111  |             Memory Write                  |
             -----------------------------------------------------
             | 1111  |       Memory Write and Invalidate         |
             -----------------------------------------------------

    CWF - If set, DMA will use "Write-with-flush" during PowerPC burst
          write cycles to force copyback writes during snoop hits.
          Else "Write-with-kill" transfer type will be used to force
          cache entries to be invalidated during snoop hits.

    GBL - If set, DMA will assert GBL_ pin during PowerPC
          write cycles to allow the processor to snoop DMA.
.CE


.CS
DNLA bits  0:26 Next Link Address (NLA)
             31 Last Link Address (LLA)
.CE

    This contains the 27-bit Most significant bits of the next Linked-List
    Mode Descriptor.  If the Descriptor List Next Link Address (DNLA) entry
    is 0, the Harrier DMA driver will configure the transfer for Direct Mode.

    NLA - The next descriptor address in 32-byte cache-line resolution.

    LLA - If set, this is the last descriptor in the list.


DCNT bits 0:31
    This contains the byte count for the DMA transfer.


Here is the format of the DMA Status Register:

.CS
DSTA bits 0  Signalled Master Abort (SMA)
          1  Received Target Abort (RTA)
          2  Maximum Retry Count (MRC)
          3  PowerPC Bus Time-out (XBT)
          4  Abort (ABT)
          5  Pause (PAU)
          6  Done (DON)
          7  Busy (BSY)
.CE
*/


/* includes */

#include "vxWorks.h"
#include "config.h"
#include "harrierDma.h"

/* defines */

/* typedefs */

typedef struct harrierDmaDrvCtrl
    {
    UINT32 * pHarrierBaseAdrs;		/* Base address of Harrier */
    UINT32   (*userHandler)(int);	/* Address of user Interrupt Handler */
    SEM_ID   semDrvId;			/* Driver access semaphore */
    SEM_ID   semIntId;			/* Interrupt interface semaphore */
    } HARRIER_DMA_DRV_CTRL;

/* globals */

/* locals */

/* THIS ARRAY INITIALIZATION MAY NEED ADJUSTMENT FOR MULTIPLE HARRIERS???? */

LOCAL HARRIER_DMA_DRV_CTRL harrierDmaCtrl [HARRIER_MAX_DEV] = {{0, 0, 0, 0}};

/* forward declarations */

LOCAL void harrierDmaIntr (UINT32);
int harrierDmaStart (UINT32, UINT32 (*)(), HARRIER_DMA_DESCRIPTOR *);
STATUS harrierDmaStatus (UINT32, UINT32 *);
STATUS harrierDmaAbort (UINT32);
STATUS harrierDmaPause (UINT32);
STATUS harrierDmaResume (UINT32);

/* external references */

/******************************************************************************
*
* harrierDmaInit - Initialize DMA and attach DMA Interrupt Handler.
*
* This routine configures the DMA driver for the specific Harrier instance.
* This routine must be called once for the Harrier DMA capability to be
* properly initialized before it can be used. 
*
* RETURNS: OK if initialization succeeded or ERROR if an error occured.
*/

STATUS harrierDmaInit
    (
    UINT32   devInstance,		/* Instance of Harrier */
    UINT32 * pHarrierBaseAdrs		/* Base address of Harrier */
    )
    {
    HARRIER_DMA_DRV_CTRL * pHarrierDmaCtrl;


    /* Validate Device index */

    if (devInstance >= HARRIER_MAX_DEV)
	return(ERROR);

    /* Setup pointer to DMA Driver control structure */

    pHarrierDmaCtrl = &harrierDmaCtrl[devInstance];

    /* Verify the driver has not been previously initialized. */

    if (pHarrierDmaCtrl->pHarrierBaseAdrs != 0)
	return(ERROR);

    /* Store Harrier Base Adddress for instance of driver */

    pHarrierDmaCtrl->pHarrierBaseAdrs = pHarrierBaseAdrs;

    /* Disable DMA interrupt. */

/*
 * THE HARRIER MACROS ARE ONLY SET FOR A ONE HARRIER SYSTEM.
 * THIS MUST BE CHANGED TO HANDLE MULTIPLE HARRIERS!!!!
 */

    *(UINT16 *)HARRIER_EXCEPTION_ENABLE_REG &= ~HARRIER_FEEN_DMA;

    /* Clear any pending DMA interrupt by writing to FECL. */

    *(UINT16 *)HARRIER_EXCEPTION_CLEAR_REG = HARRIER_FECL_DMA;

    /* Setup DMA Control Register default values. */

    *(UINT32 *)HARRIER_DMA_CONTROL_REG = (HARRIER_DCTL_XTH_256BYTES |
                                          HARRIER_DCTL_PBT_0_CLKS |
                                          HARRIER_DCTL_CSE |
                                          HARRIER_DCTL_CRI |
                                          HARRIER_DCTL_GBL);

    /* Create a semaphore for access to the device instance. */

    pHarrierDmaCtrl->semDrvId = semBCreate(SEM_Q_PRIORITY, SEM_FULL);

    /* Create binary semaphore for synchronization with DMA start. */

    pHarrierDmaCtrl->semIntId = semBCreate(SEM_Q_FIFO, SEM_EMPTY);

    /* Connect the interrupt handler to HARR_FUNC_INT_VEC. */

    if (intConnect (INUM_TO_IVEC(HARR_FUNC_INT_VEC), harrierDmaIntr,
                    (int)devInstance) == ERROR)
	return (ERROR);

    /* Enable the interrupt to the processor in the MPIC. */

    intEnable (HARR_FUNC_INT_LVL);

    /* Clear the DMA interrupt mask by writing to FEMA. */

    *(UINT16 *)HARRIER_EXCEPTION_MASK_REG = HARRIER_FEST_DMA;

    /* Enable the DMA interrupt by writing to FEEN. */

    *(UINT16 *)HARRIER_EXCEPTION_ENABLE_REG |= HARRIER_FEEN_DMA;

    return (OK);
    }


/******************************************************************************
*
* harrierDmaIntr - Clear the interrupt and capture completion status.
*
* This routine cleans up after the DMA controller interrupt.
* It gives a semaphore to the DMA start routine if wait is set to -1.
* It executes a user routine if wait is set to something other than 0 or -1.
*
* RETURNS: N/A
*/