sysgei82543end.c

vxworks的bsp开发包(基于POWERPC的PRPMC800)

/* sysGei82543End.c - Intel Pro1000 F/T Adapter END driver support routines */

/* Copyright 1989-2001 Wind River Systems, Inc.  */
/* Copyright 2001 Motorola, Inc. All Rights Reserved */

#include "copyright_wrs.h"

/*
modification history
--------------------
01e,10jul02,dtr  SPR 79571. Slight API change to an unused function 
                 sys543IntEnable/Disable.
01d,28nov01,dtr  Tidy up.
01c,25Nov01,dtr  Modified sys543LocalToPciBus etc for new PCI configuration.
01b,31jul01,srr  Added support for PrPMC-G.
01a,08Jan01,jln  written based on sysNetif.c.
*/

/*
This module is BSP support for Intel PRO1000 F/T adaptors. 

SEE ALSO: ifLib,
.I "RS82543GC GIGABIT ETHERNET CONTROLLER NETWORKING SILICON DEVELOPER'S MANUAL"
*/

#include "vxWorks.h"
#include "taskLib.h"
#include "sysLib.h"
#include "config.h"
#include "end.h"
#include "vmLib.h"
#include "drv/pci/pciIntLib.h"
#include "drv/end/gei82543End.h"

#if (defined(INCLUDE_GEI_END) && defined (INCLUDE_NETWORK)	\
     && defined (INCLUDE_END))

#ifdef I82543_DEBUG
#   undef    LOCAL
#   define    LOCAL
#endif    /* I82543_DEBUG */

/* include PCI Library */

#ifndef INCLUDE_PCI
#define INCLUDE_PCI
#endif /* INCLUDE_PCI */

/* PCI configuration type */
 
#ifndef PCI_CFG_TYPE
#define PCI_CFG_TYPE               PCI_CFG_NONE
#endif

/* Default RX descriptor  */

#ifndef GEI_RXDES_NUM
#define GEI_RXDES_NUM              GEI_DEFAULT_RXDES_NUM
#endif

/* Default TX descriptor  */

#ifndef GEI_TXDES_NUM
#define GEI_TXDES_NUM              GEI_DEFAULT_TXDES_NUM
#endif

/* Default User's flags  */

#ifndef GEI_USR_FLAG
#define GEI_USR_FLAG               GEI_DEFAULT_USR_FLAG
#endif

#define GEI0_MEMBASE0_LOW           0xfd000000    /* mem base for CSR */
#define GEI0_MEMBASE0_HIGH          0x00000000    /* mem base for CSR */
#define GEI0_MEMSIZE0               0x20000       /* mem size - CSR,128KB */
#define GEI0_MEMBASE1               0xfd100000    /* mem base - Flash */
#define GEI0_MEMSIZE1               0x00080000    /* mem size - Flash,512KB */
#define GEI0_INT_LVL                0x0b          /* IRQ 11 */
#define GEI0_INIT_STATE_MASK        (VM_STATE_MASK_FOR_ALL)
#define GEI0_INIT_STATE             (VM_STATE_FOR_PCI)
#define GEI0_SHMEM_BASE             NONE
#define GEI0_SHMEM_SIZE             0
#define GEI0_RXDES_NUM              GEI_RXDES_NUM
#define GEI0_TXDES_NUM              GEI_TXDES_NUM
#define GEI0_USR_FLAG               GEI_USR_FLAG

#define GEI1_MEMBASE0_LOW           0xfd200000    /* mem base for CSR */
#define GEI1_MEMBASE0_HIGH          0x00000000    /* mem base for CSR */
#define GEI1_MEMSIZE0               0x20000       /* mem size - CSR,128KB */
#define GEI1_MEMBASE1               0xfd300000    /* mem base for Flash */
#define GEI1_MEMSIZE1               0x00080000    /* mem size - Flash,512KB */
#define GEI1_INT_LVL                0x05          /* IRQ 5 */
#define GEI1_INIT_STATE_MASK        (VM_STATE_MASK_FOR_ALL)
#define GEI1_INIT_STATE             (VM_STATE_FOR_PCI)
#define GEI1_SHMEM_BASE             NONE
#define GEI1_SHMEM_SIZE             0
#define GEI1_RXDES_NUM              GEI_RXDES_NUM
#define GEI1_TXDES_NUM              GEI_TXDES_NUM
#define GEI1_USR_FLAG               GEI_USR_FLAG

#define GEI2_MEMBASE0_LOW           0xfd400000    /* mem base - CSR */
#define GEI2_MEMBASE0_HIGH          0x00000000    /* mem base - CSR */
#define GEI2_MEMSIZE0               0x20000       /* mem size - CSR, 128KB */
#define GEI2_MEMBASE1               0xfd500000    /* mem base - Flash */
#define GEI2_MEMSIZE1               0x00080000    /* mem size - Flash,512KB */
#define GEI2_INT_LVL                0x0c          /* IRQ 12 */
#define GEI2_INIT_STATE_MASK        (VM_STATE_MASK_FOR_ALL)
#define GEI2_INIT_STATE             (VM_STATE_FOR_PCI)
#define GEI2_SHMEM_BASE             NONE
#define GEI2_SHMEM_SIZE             0
#define GEI2_RXDES_NUM              GEI_RXDES_NUM
#define GEI2_TXDES_NUM              GEI_TXDES_NUM
#define GEI2_USR_FLAG               GEI_USR_FLAG

#define GEI3_MEMBASE0_LOW           0xfd600000   /* mem base - CSR */
#define GEI3_MEMBASE0_HIGH          0x00000000   /* mem base - CSR */
#define GEI3_MEMSIZE0               0x20000      /* mem size - CSR,128KB */
#define GEI3_MEMBASE1               0xfd700000   /* mem base - Flash */
#define GEI3_MEMSIZE1               0x00080000   /* mem size - Flash,512KB */
#define GEI3_INT_LVL                0x09         /* IRQ 9 */
#define GEI3_INIT_STATE_MASK        (VM_STATE_MASK_FOR_ALL)
#define GEI3_INIT_STATE             (VM_STATE_FOR_PCI)
#define GEI3_SHMEM_BASE             NONE
#define GEI3_SHMEM_SIZE             0
#define GEI3_RXDES_NUM              GEI_RXDES_NUM
#define GEI3_TXDES_NUM              GEI_TXDES_NUM
#define GEI3_USR_FLAG               GEI_USR_FLAG

#define GEI82543_LOAD_FUNC          gei82543EndLoad
#define GEI_X86_OFFSET_VALUE        0x0 

/* Alaska PHY's information */

#define MARVELL_OUI_ID              0x5043
#define MARVELL_ALASKA_88E1000      0x5
#define MARVELL_ALASKA_88E1000S     0x4
#define ALASKA_PHY_SPEC_CTRL_REG        0x10
#define ALASKA_PHY_SPEC_STAT_REG        0x11
#define ALASKA_INT_ENABLE_REG           0x12
#define ALASKA_INT_STATUS_REG           0x13
#define ALASKA_EXT_PHY_SPEC_CTRL_REG    0x14
#define ALASKA_RX_ERROR_COUNTER         0x15
#define ALASKA_LED_CTRL_REG             0x18

#define ALASKA_PSCR_ASSERT_CRS_ON_TX    0x0800
#define ALASKA_EPSCR_TX_CLK_25          0x0070

#define ALASKA_PSCR_AUTO_X_1000T        0x0040
#define ALASKA_PSCR_AUTO_X_MODE         0x0060

#define ALASKA_PSSR_DPLX                0x2000
#define ALASKA_PSSR_SPEED               0xC000
#define ALASKA_PSSR_10MBS               0x0000
#define ALASKA_PSSR_100MBS              0x4000
#define ALASKA_PSSR_1000MBS             0x8000

/* assuming 1:1 mapping for virtual:physical address */

#if (_BYTE_ORDER == _BIG_ENDIAN)
#   define GEI_SYS_WRITE_REG(unit, reg, value)     \
        ((*(volatile UINT32 *)(PCI_MEMIO2LOCAL(geiResources[(unit)].memBaseLow) + (reg))) = \
         (UINT32) LONGSWAP(value))

#   define GEI_SYS_READ_REG(unit, reg)             \
        (LONGSWAP( *(volatile UINT32 *)(PCI_MEMIO2LOCAL(geiResources[(unit)].memBaseLow) + (reg))) )
#else /* (_BYTE_ORDER != _BIG_ENDIAN) */
#   define GEI_SYS_WRITE_REG(unit, reg, value)     \
        ((*(volatile UINT32 *)(PCI_MEMIO2LOCAL(geiResources[(unit)].memBaseLow) + (reg))) = \
         (UINT32)(value))

#   define GEI_SYS_READ_REG(unit, reg)             \
        (*(volatile UINT32 *)(PCI_MEMIO2LOCAL(geiResources[(unit)].memBaseLow) + (reg)))
#endif /* (_BYTE_ORDER == _BIG_ENDIAN) */

/* externs */

IMPORT END_TBL_ENTRY    endDevTbl[];    /* end device table */
IMPORT void     sysUsDelay (UINT32);

/* typedefs */
#define PPC_PAGE_SIZE       0x0001000
#define ENET_BUF_ALIGN(addr)                         \
        (((UINT32)(addr)+PPC_PAGE_SIZE) & ~(PPC_PAGE_SIZE-1))

#define EEPROM_ENABLE_BITS              9
#define EEPROM_WRITE_DIS_OPCODE         ((0x4 << 6) | (0x0 << 4))
#define EEPROM_WRITE_EN_OPCODE          ((0x4 << 6) | (0x3 << 4))
#define EEPROM_WRITE_ALL_OPCODE         ((0x4 << 6) | (0x1 << 4))
#define EEPROM_ERASE_ALL_OPCODE         ((0x4 << 6) | (0x2 << 4))

typedef struct geiResource        /* GEI_RESOURCE */
    {
    UINT32 memBaseLow;            /* Base Address LOW */
    UINT32 memBaseHigh;           /* Base Address HIGH */
    UINT32 flashBase;             /* Base Address for FLASH */
    char   irq;                   /* Interrupt Request Level */
    BOOL   adr64;                 /* Indicator for 64-bit support */
    int    boardType;             /* type of LAN board this unit is */
    int    pciBus;                /* PCI Bus number */
    int    pciDevice;             /* PCI Device number */
    int    pciFunc;               /* PCI Function number */
    UINT   memLength;             /* required memory size */
    UINT   initialStateMask;      /* mask parameter to vmStateSet */
    UINT   initialState;          /* state parameter to vmStateSet */
    UINT16 eeprom_icw1;           /* EEPROM initialization control word 1 */
    UINT16 eeprom_icw2;           /* EEPROM initialization control word 2 */
    UCHAR  enetAddr[6];           /* MAC address for this adaptor */
    STATUS iniStatus;             /* initialization perform status */
    UINT32 shMemBase;             /* Share memory address if any */
    UINT32 shMemSize;             /* Share memory size if any */
    UINT32 rxDesNum;              /* RX descriptor for this unit */
    UINT32 txDesNum;              /* TX descriptor for this unit */
    UINT32 usrFlags;              /* user flags for this unit */
    } GEI_RESOURCE;

/* locals */

LOCAL UINT32 sys543LocalToPciBusAdrs (int unit, UINT32 adrs);
LOCAL UINT32 sys543PciBusToLocalAdrs (int unit, UINT32 adrs);
LOCAL UINT32 geiUnits;     /* number of GEIs we found */

UCHAR lowMemBufGei[0xa0000 + PPC_PAGE_SIZE];

LOCAL GEI_RESOURCE geiResources [] =
    {
    {GEI0_MEMBASE0_LOW,GEI0_MEMBASE0_HIGH, GEI0_MEMBASE1, GEI0_INT_LVL, 
     UNKNOWN, UNKNOWN, UNKNOWN, UNKNOWN, UNKNOWN, 
     GEI0_MEMSIZE0, GEI0_INIT_STATE_MASK, GEI0_INIT_STATE, 0, 0, {UNKNOWN},
     ERROR, GEI0_SHMEM_BASE, GEI0_SHMEM_SIZE, GEI0_RXDES_NUM, GEI0_TXDES_NUM, 
     GEI0_USR_FLAG},
    {GEI1_MEMBASE0_LOW, GEI1_MEMBASE0_HIGH, GEI1_MEMBASE1, GEI1_INT_LVL, 
     UNKNOWN, UNKNOWN, UNKNOWN, UNKNOWN, UNKNOWN, 
     GEI1_MEMSIZE0, GEI1_INIT_STATE_MASK, GEI1_INIT_STATE, 0, 0, {UNKNOWN},
     ERROR, GEI1_SHMEM_BASE, GEI1_SHMEM_SIZE, GEI1_RXDES_NUM, GEI1_TXDES_NUM, 
     GEI1_USR_FLAG},
    {GEI2_MEMBASE0_LOW, GEI2_MEMBASE0_HIGH, GEI2_MEMBASE1, GEI2_INT_LVL, 
     UNKNOWN,UNKNOWN, UNKNOWN, UNKNOWN, UNKNOWN,
     GEI2_MEMSIZE0, GEI2_INIT_STATE_MASK, GEI2_INIT_STATE, 0, 0, {UNKNOWN},
     ERROR,GEI2_SHMEM_BASE, GEI2_SHMEM_SIZE, GEI2_RXDES_NUM, GEI2_TXDES_NUM, 
     GEI2_USR_FLAG},
    {GEI3_MEMBASE0_LOW,GEI3_MEMBASE0_HIGH, GEI3_MEMBASE1, GEI3_INT_LVL, 
     UNKNOWN, UNKNOWN, UNKNOWN, UNKNOWN, UNKNOWN, 
     GEI3_MEMSIZE0, GEI3_INIT_STATE_MASK, GEI3_INIT_STATE, 0, 0, {UNKNOWN},
     ERROR,GEI3_SHMEM_BASE, GEI3_SHMEM_SIZE, GEI3_RXDES_NUM, GEI3_TXDES_NUM, 
     GEI3_USR_FLAG},
     };

/* globals */
 
/*
 * NOTE: Each GEI device will need it's own lowMemBuf.
 * Since the PrPMC-G only has one GEI, this is all that is needed for now.
 */
                                              /* i82543 buffer in low memory */


/* forward declarations */

LOCAL int       sys543IntEnable  (int unit);
LOCAL int       sys543IntDisable (int unit);
LOCAL int       sys543IntAck     (int unit);
LOCAL void      sys543LoadStrCompose (int unit);
LOCAL STATUS    sys543eepromCheckSum (int unit);
LOCAL UINT16    sys543eepromReadWord (int unit,UINT32);
LOCAL STATUS    sys543EtherAdrGet (int unit);
LOCAL void      sys543PhySpecRegsInit(PHY_INFO *, UINT8);
LOCAL void      sys1000NsDelay (void);

LOCAL UINT32    localDramSize;
/*****************************************************************************
*
* sys543PciInit - Initialize and get the PCI configuration for 82543 Chips
*
* This routine finds out PCI device, and maps its memory and IO address.
* It must be done prior to initializing of 82543 chips.  Also
* must be done prior to MMU initialization, usrMmuInit().
*
* RETURNS: N/A
*/

STATUS sys543PciInit (void)
    {
    GEI_RESOURCE *pReso;         /* chip resources */
    int pciBus;                  /* PCI bus number */
    int pciDevice;               /* PCI device number */
    int pciFunc;                 /* PCI function number */
    int unit;                    /* unit number */
    int pro1000TDevUnit=0;       /* count of Intel Pro1000T */
    int pro1000DevUnit =0;       /* count of Intel Pro1000F/T */
    BOOL duplicate;              /* BOOL flag for duplicate chip */
    UINT32 bar0;                 /* PCI BAR_0 */
    UINT32 memBaseLow;           /* mem base low */
    UINT32 memBaseHigh;          /* mem base High */
    UINT32 flashBase;            /* flash base */
    UINT16 boardId =0;           /* adaptor Id */
    char   irq;                  /* irq number */
    int    ix;                   /* index */


    localDramSize = sysDramSize();

    geiResources [0].shMemBase = ENET_BUF_ALIGN (lowMemBufGei);
    geiResources [0].shMemSize = sizeof(lowMemBufGei) -
                                 (ENET_BUF_ALIGN (lowMemBufGei) 
     				  - (UINT32)(lowMemBufGei));

    for (unit = 0; unit < NELEMENTS(geiResources); unit++)
        {      
        boardId = UNKNOWN;

        /* 
         * The following PCI information is based on adapters (T/F) 
         * from Intel. 
         * PCI Device ID    SUB-SYSTEM ID    ADAPTOR
         *  0x1001           0x1003          INTEL PRO1000 F
         *  0x1001           0x1004          INTEL PRO1000 T
         *  0x1004             X             INTEL PRO1000 T
         */        

        if (pciFindDevice (PRO1000_PCI_VENDOR_ID, PRO1000T_PCI_DEVICE_ID, 
                           pro1000TDevUnit, &pciBus, &pciDevice, &pciFunc) 
                           == OK)
            {
            pro1000TDevUnit++;

            boardId = PRO1000T_BOARD;
            }

        /* Detect possible PRO1000T/F adaptors */

        else if (pciFindDevice (PRO1000_PCI_VENDOR_ID, PRO1000_PCI_DEVICE_ID, 
                                pro1000DevUnit, &pciBus, &pciDevice, 
                                &pciFunc) == OK)
            {  
            pro1000DevUnit++;

            /* Distinguish Pro1000T and Pro1000F adapter by SUB_SYSTEM_ID */

            pciConfigInWord(pciBus, pciDevice, pciFunc, 
                            PCI_CFG_SUB_SYSTEM_ID, &boardId);

	    /* PrPMC-G board uses PRO1000 T */

            boardId = PRO1000T_BOARD;     
            }
        else
            break;        
     
        /* check the duplicate */

        pReso     = &geiResources [0];
        duplicate = FALSE;

        for (ix = 0; ix < NELEMENTS(geiResources); ix++, pReso++)
            {
            if ((ix != unit) && (pReso->pciBus == pciBus) &&
               (pReso->pciDevice == pciDevice) && (pReso->pciFunc == pciFunc))
                duplicate = TRUE;
            }

        if (duplicate)
            continue;

        /* we found the right one */

        pReso = &geiResources [unit];
        pReso->boardType = boardId;
        pReso->pciBus    = pciBus;
        pReso->pciDevice = pciDevice;
        pReso->pciFunc   = pciFunc;


        /* 
         * BAR0: [32:17]: memory base
         *       [16:4] : read as "0"; 
         *       [3]    : 0 - device is not prefetchable
         *       [2:1]  : 00b - 32-bit address space, or
         *                01b - 64-bit address space
         *       [0]    : 0 - memory map decoded
         *
         * BAR1: if BAR0[2:1] == 00b, optional flash memory base
         *       if BAR0[2:1] == 01b, high portion of memory base 
         *                            for 64-bit address space        
         *
         * BAR2: if BAR0[2:1] == 01b, optional flash memory base
         *       if BAR0[2:1] == 00b, behaves as BAR-1 when BAR-0 is 
         *                            a 32-bit value 
         */

        pciConfigInLong (pReso->pciBus, pReso->pciDevice, pReso->pciFunc,
                          PCI_CFG_BASE_ADDRESS_0, &bar0);

        pReso->adr64 = ((bar0 & BAR0_64_BIT) == BAR0_64_BIT)? TRUE : FALSE;
        
        /* If configured, set the PCI Configuration manually */

        if (PCI_CFG_TYPE == PCI_CFG_FORCE) 
            {
            pciConfigOutLong (pReso->pciBus, pReso->pciDevice, pReso->pciFunc,
                              PCI_CFG_BASE_ADDRESS_0, pReso->memBaseLow);
            if (pReso->adr64)
                {
                pciConfigOutLong (pReso->pciBus, pReso->pciDevice, 
                                  pReso->pciFunc,PCI_CFG_BASE_ADDRESS_1, 
                                  pReso->memBaseHigh);

                pciConfigOutLong (pReso->pciBus, pReso->pciDevice, 
                                  pReso->pciFunc, PCI_CFG_BASE_ADDRESS_2, 
                                  pReso->flashBase);
                }
            else
                {
                pciConfigOutLong (pReso->pciBus, pReso->pciDevice, 
                                  pReso->pciFunc, PCI_CFG_BASE_ADDRESS_1, 
                                  pReso->flashBase);

                pciConfigOutLong (pReso->pciBus, pReso->pciDevice, 
                                  pReso->pciFunc, PCI_CFG_BASE_ADDRESS_2, 
                                  pReso->flashBase);
                }

            pciConfigOutByte (pReso->pciBus, pReso->pciDevice, pReso->pciFunc,
                              PCI_CFG_DEV_INT_LINE, pReso->irq);