rominit.s

vxworks的bsp开发包(基于POWERPC的PRPMC800)

/* romInit.s - Motorola PrPMC800 ROM initialization module */

/* Copyright 1984-2001 Wind River Systems, Inc. */
/* Copyright 1996-2001 Motorola, Inc. All Rights Reserved */
    .data
    .globl  copyright_wind_river
    .long   copyright_wind_river

/*
modification history
--------------------
01l,11mar02,dtr  Adding option for disabling exceptions for bus parity errors.
01k,10oct01,scb  Clear PCI_AUTOCONFIG_FLAG.
01j,09jan01,dmw  Modified ECC code to set/clear ECC enable bit.
01i,05jan01,krp  Fixed compiler warning out of range value
01h,21dec00,krp  Enable COM2 port on the PrPMC800XT board
01g,14nov00,dmw  Cleaned up hardcodes.
01f,27oct00,dmw  Added code to load the Harrier registers base during mem init.
01e,16oct00,dmw  Removed PCI bridge initialization.  Now done in harrierPhb.c.
01d,12oct00,dmw  Moved PCI I/O to 0xFD000000.
01c,09oct00,dmw  Fixed outbound translation register.
01b,08oct00,dmw  Added Nitro support.
01a,09aug00,dmw  Written (from version 01g of mcpn765/romInit.s
*/

/*
DESCRIPTION
This module contains the entry code for the VxWorks bootrom.
The entry point romInit, is the first code executed on power-up.
It sets the BOOT_COLD parameter to be passed to the generic
romStart() routine.

The routine sysToMonitor() jumps to the location 4 bytes
past the beginning of romInit, to perform a "warm boot".
This entry point allows a parameter to be passed to romStart().

This code is intended to be generic across PowerPC 603/604 boards.
Hardware that requires special register setting or memory
mapping to be done immediately, may do so here.
*/

#define    _ASMLANGUAGE
#include "vxWorks.h"
#include "sysLib.h"
#include "asm.h"
#include "config.h"
#include "regs.h"    
#include "harrier.h"    

#include "arch/ppc/mmu603Lib.h"

#define CACHE_STACK_SIZE    (8*1024)
#define MEMSSCR1        0x00040000  /* Memory SubSystem Control Reg 1 */
                                    /* bit 13 for Nitro errata 1 */

    /* Exported internal functions */

    FUNC_EXPORT(_romInit)       /* start of system code */
    FUNC_EXPORT(romInit)        /* start of system code */

    /* externals */

    /* system initialization routine */

    FUNC_IMPORT(romStart)         

    /* harrier memory parameter initialization */

    FUNC_IMPORT(sysHarrierParamConfig)    

    /* harrier memory register save area offsets */

    .set sdramBlkAddrA,0                  /* Base Addressing Block A */
    .set sdramBlkAddrB,sdramBlkAddrA+4    /* Base Addressing Block B */
    .set sdramBlkAddrC,sdramBlkAddrB+4    /* Base Addressing Block C */
    .set sdramBlkAddrD,sdramBlkAddrC+4    /* Base Addressing Block D */
    .set sdramBlkAddrE,sdramBlkAddrD+4    /* Base Addressing Block E */
    .set sdramBlkAddrF,sdramBlkAddrE+4    /* Base Addressing Block F */
    .set sdramBlkAddrG,sdramBlkAddrF+4    /* Base Addressing Block G */
    .set sdramBlkAddrH,sdramBlkAddrG+4    /* Base Addressing Block H */
    .set sdramGeneralControl,sdramBlkAddrH+4     /* SDRAM Gen Cntrl settings */
    .set sdramTimingControl,sdramGeneralControl+4 /* Timing Cntrl settings */
    .set clkFrequency,sdramTimingControl+4        /* Operating clck freq */
    
    _WRS_TEXT_SEG_START

        
/******************************************************************************
*
* romInit - entry point for VxWorks in ROM
*
* romInit
*     (
*     int startType    /@ only used by 2nd entry point @/
*     )
*/

FUNC_LABEL(_romInit)
FUNC_BEGIN(romInit)
    isync            /* required for Max errata 2 */

    bl    cold
    
    bl    warm

    /* copyright notice appears at beginning of ROM (in TEXT segment) */

    .ascii   "Copyright 1984-1999 Wind River Systems, Inc."
    .balign _PPC_TEXT_SEG_ALIGN

cold:
    li    r31, BOOT_COLD
    bl    start          /* skip over next instruction */

            
warm:
    or    r31, r3, r3    /* startType to r31 */

start:
    /* Zero-out registers: r0 & SPRGs */

    xor     r0,r0,r0
    mtspr   272,r0
    mtspr   273,r0
    mtspr   274,r0
    mtspr   275,r0

    /* initialize the stack pointer */

    lis     sp, HI(STACK_ADRS)
    ori     sp, sp, LO(STACK_ADRS)

    /*
     *    Set HID0 to a known state
     *    Enable machine check input pin (EMCP)
     *    Disable instruction and data caches
     */

    addis   r3,r0,0x8000
    ori     r3,r3,0x0000
    sync             /* required before changing DCE */
    isync            /* required before chaning ICE */
    mtspr   HID0, r3

    /*
     *    Set MPU/MSR to a known state
     *    Turn on FP
     */

    andi.  r3, r3, 0
    ori    r3, r3, 0x2000
    sync
    mtmsr  r3
    isync

    /* Init the floating point control/status register */

    mtfsfi  7,0x0
    mtfsfi  6,0x0
    mtfsfi  5,0x0
    mtfsfi  4,0x0
    mtfsfi  3,0x0
    mtfsfi  2,0x0
    mtfsfi  1,0x0
    mtfsfi  0,0x0
    isync

    /* Initialize the floating point data regsiters to a known state */

    bl    ifpdr_value
    .long    0x3f800000    /* 1.0 */
ifpdr_value:
    mfspr    r3,8
    lfs    f0,0(r3)
    lfs    f1,0(r3)
    lfs    f2,0(r3)
    lfs    f3,0(r3)
    lfs    f4,0(r3)
    lfs    f5,0(r3)
    lfs    f6,0(r3)
    lfs    f7,0(r3)
    lfs    f8,0(r3)
    lfs    f9,0(r3)
    lfs    f10,0(r3)
    lfs    f11,0(r3)
    lfs    f12,0(r3)
    lfs    f13,0(r3)
    lfs    f14,0(r3)
    lfs    f15,0(r3)
    lfs    f16,0(r3)
    lfs    f17,0(r3)
    lfs    f18,0(r3)
    lfs    f19,0(r3)
    lfs    f20,0(r3)
    lfs    f21,0(r3)
    lfs    f22,0(r3)
    lfs    f23,0(r3)
    lfs    f24,0(r3)
    lfs    f25,0(r3)
    lfs    f26,0(r3)
    lfs    f27,0(r3)
    lfs    f28,0(r3)
    lfs    f29,0(r3)
    lfs    f30,0(r3)
    lfs    f31,0(r3)

    /*
     *    Set MPU/MSR to a known state
     *    Turn off FP
     */

    andi.    r3, r3, 0
    sync
    mtmsr    r3
    isync

    /* Init the Segment registers */

    andi.   r3, r3, 0
    isync
    mtsr    0,r3
    isync
    mtsr    1,r3
    isync
    mtsr    2,r3
    isync
    mtsr    3,r3
    isync
    mtsr    4,r3
    isync
    mtsr    5,r3
    isync
    mtsr    6,r3
    isync
    mtsr    7,r3
    isync
    mtsr    8,r3
    isync
    mtsr    9,r3
    isync
    mtsr    10,r3
    isync
    mtsr    11,r3
    isync
    mtsr    12,r3
    isync
    mtsr    13,r3
    isync
    mtsr    14,r3
    isync
    mtsr    15,r3
    isync

    /* 
     * Disable Harrier's Watchdog Timers.
     *
     * Note: Both of Harrier's Watchdog timers must be disabled at powerup.
     * Otherwise Watchdog Timer 1 will time out in 512 msec and interrupt the 
     * board, Watchdog Timer 2 will time out in 576 msec and reset the board.
     */

    lis     r3,HI(HARRIER_XCSR_BASE)
    ori     r3,r3,LO(HARRIER_XCSR_BASE)

    addis   r4,r0,0x0000            /* disable Watchdog Timers */
    ori     r4,r4,0x0055            /* load PATTERN_1 */
    isync                           /* synchronize */

    /* arm Watchdog Timer 1 (WDT1CNTL) */

    stb     r4,HARRIER_WTCHDG_CNTR0_OFFSET(r3)

    eieio                           /* synchronize */
    sync                            /* synchronize */

    addis   r4,r0,0xAA0F            /* load PATTERN_2 */
    ori     r4,r4,0xFFFF
    isync                           /* synchronize */

    /* disable Timer 1 w max resolution */

    stw     r4,HARRIER_WTCHDG_CNTR0_OFFSET(r3)

    eieio                           /* synchronize */
    sync                            /* synchronize */

    addis   r4,r0,0x0000            /* load PATTERN_1 */
    ori r4,r4,0x0055
    isync                           /* synchronize */

    /* arm Watchdog Timer 2 (WDT2CNTL) */

    stb r4,HARRIER_WTCHDG_CNTR1_OFFSET(r3)

    eieio                           /* synchronize */
    sync                            /* synchronize */

    addis   r4,r0,0xAA0F            /* load PATTERN_2 */
    ori r4,r4,0xFFFF
    isync                           /* synchronize */

    /* disable Timer2 w max resolution */

    stw r4,HARRIER_WTCHDG_CNTR1_OFFSET(r3)
    eieio                           /* synchronize */
    sync                            /* synchronize */

    /* disable PCI bridge configuration cycles */

    addis   r4,r0,HI(HARRIER_BPCS_XCSR_CSH)
    ori r4,r4,LO(HARRIER_BPCS_XCSR_CSH)
    isync                           /* synchronize */

    /* set configuration space hold off */

    stw r4,HARRIER_PCI_CS_REG_OFFSET(r3)
    eieio                           /* synchronize */
    sync                            /* synchronize */
   
    /* Clear the RomStartup error flags.  */

    xor    r4,r4,r4
    stw    r4,HARRIER_GP0_OFFSET(r3)
    eieio                           /* synchronize */
    sync                            /* synchronize */
    stw    r4,HARRIER_GP1_OFFSET(r3)
    eieio                           /* synchronize */
    sync                            /* synchronize */
    stw    r4,HARRIER_GP2_OFFSET(r3)
    eieio                           /* synchronize */
    sync                            /* synchronize */
    stw    r4,HARRIER_GP3_OFFSET(r3)
    eieio                           /* synchronize */
    sync                            /* synchronize */

    /* Get cpu type */

    mfspr   r28, PVR
    rlwinm  r28, r28, 16, 16, 31

    cmpli   0, 0, r28, CPU_TYPE_NITRO
    bne     cpuNotNitro

    /* Nitro errata 1 work-around.  */

    li      r2,0x0
    mtspr   1014,r2                 /* MSSCR0 */

    lis     r2,HI(MEMSSCR1)
    ori     r2,r2,LO(MEMSSCR1)      /* MSSCR1: Nitro Errata 1 */
    mtspr   1015,r2

cpuNotNitro:
    /* invalidate the MPU's data/instruction caches */

    cmpli   0, 0, r28, CPU_TYPE_750
    beq     cpuIs750
    cmpli   0, 0, r28, CPU_TYPE_NITRO
    beq     cpuIs750
    cmpli   0, 0, r28, CPU_TYPE_MAX
    beq     cpuIs750
    b    cacheEnableDone

cpuIs750:
#ifdef USER_I_CACHE_ENABLE
    mfspr   r3,HID0
    rlwinm  r3,r3,0,19,17         /* clear ILOCK (bit 18) */
    ori     r3,r3,(_PPC_HID0_ICFI | _PPC_HID0_ICE)
    isync                         /* required before changing ICE */
    mtspr   HID0,r3               /* set ICFI (bit 20) and ICE (bit 16) */
#endif
cacheEnableDone:

    /* disable the DBATs */

    xor     r0,r0,r0
    mtspr   DBAT0U,r0
    mtspr   DBAT1U,r0
    mtspr   DBAT2U,r0
    mtspr   DBAT3U,r0
    sync

    xor    r0,r0,r0        /* insure r0 is zero */

    lis     r3,HI(HARRIER_XCSR_BASE)    /* load Harrier's base address */
    ori     r3,r3,LO(HARRIER_XCSR_BASE) /* load Harrier's base address */

    /*
     * Initialize the PPC Clock Frequency Register(XCFR) to 100MHz
     * This is used as the prescale counter for the memory refresher/scrubber.
     */

    addis   r9,r0,0x6400            /* CLK=0x64(100MHZ) */
    ori     r9,r9,0x0000            /* CLK=0x64(100MHZ) */

    /* XCFR: PPC CLK frequency register */

    stw     r9,H_PPCCLKFRQ_OFST(r3)
    eieio
    sync

    lis     r4,0x1200           /* set SDRAM timing to default */
    ori     r4,r4,0x0000        /* MXRR=01,DREF=0,DERC=1,RWCB=0,ENRV=0,SWVT=0 */
    stw     r4,0x0100(r3)
    eieio
    sync

    lis     r4,0x0005           /* enable SDRAM bank A, size=16Mx8 (128MB) */
    ori     r4,r4,0100
    stw     r4,0x0110(r3)
    eieio
    sync

    addi    r4,r0,0x01
    stb     r4,0x112(r3)       /* write DRAM enable bit(disable) */
    eieio
    sync

    /* create an ABI stack frame in data cache */

    stwu    sp,-40(sp)      

    addi    r3,sp,8         /* point to register image area (r3) */
    or      r14,r3,r3       /* save register image address */
    bl      sysHarrierParamConfig  /* calculate hawk smc parameters */
    or      r15,r3,r3       /* save memory size */

    lbz     r4,clkFrequency(r14)          /* load the Clock Frequency */
    lwz     r5,sdramTimingControl(r14)    /* load the Sdram timing control */
    lwz     r6,sdramGeneralControl(r14)   /* load the general control */
    lwz     r7,sdramBlkAddrH(r14)         /* load Base Data Block H */
    lwz     r8,sdramBlkAddrG(r14)         /* load Base Data Block G */
    lwz     r9,sdramBlkAddrF(r14)         /* load Base Data Block F */
    lwz     r10,sdramBlkAddrE(r14)        /* load Base Data Block E */
    lwz     r11,sdramBlkAddrD(r14)        /* load Base Data Block D */
    lwz     r12,sdramBlkAddrC(r14)        /* load Base Data Block C */
    lwz     r13,sdramBlkAddrB(r14)        /* load Base Data Block B */
    lwz     r14,sdramBlkAddrA(r14)        /* load Base Data Block A */

    /* remove ABI stack frame */

    addi    sp,sp,40        

    /*
     * Set the Clock Frequency register and the SDRAM attributes register