config.h

vxworks的bsp开发包(基于POWERPC的PRPMC800)

#ifdef  INCLUDE_SM_NET
#define INCLUDE_SM_COMMON
#define INCLUDE_SM_OBJ
#endif  /* INCLUDE_SM_NET */

/*
 * The following defines are used when generating or receiving shared memory
 * bus interrupts. Depending on configuration, the bus interrupt may be
 * generated using the Dec21554 (to drive a cPCI bus interrupt) or may be
 * generated by the CPU1 portion of the MPIC Inter-Processor Interrupt mechanism
 * (to drive a local PCI bus interrupt). For convenience, the same vector
 * number is used in both environments. Note that the same IPI vector (0-3)
 * cannot be used for both in-bound and out-bound interrupts simultaneously.
 * This constraint is driven by the MPIC IPI implementation which shares a
 * common enable bit for both Processor 0 and Process 1 interrupts.
 */

/*
 * The following defines are used by the Monarch to control PCI Bus interrupts
 * generated by non-Monarch PrPMCs. The default values configure IPI3
 * as the shared memory bus interrupt.
 *
 * NOTE: In this case, interrupt level (0x27) does not equal interrupt vector
 * (0x60).
 */

#define SM_BUS_INT_LVL		    IPI3_INT_LVL
#define SM_BUS_INT_VEC		    DEC2155X_MAILBOX_INT_VEC

/*
 * The following defines are used by non-Monarch PrPMCs to control in-bound
 * shared memory mailbox interrupts. The default values configure IPI0
 * as the in-bound shared memory mailbox interrupt with a priority level of 7.
 */

#define SM_MAILBOX_INT_LVL	IPI0_INT_LVL
#define SM_MAILBOX_INT_PRIORITY	PRIORITY_LVL7

/* Local and backplane bus numbers - see SYS_SM_BUS_NUMBER */

#define SYS_LOCAL_PCI_BUS_NUMBER 	0
#define SYS_BACKPLANE_BUS_NUMBER    	1 

#if defined(INCLUDE_SM_COMMON)

#   define STANDALONE_NET
#   define INCLUDE_NET_SHOW
#   define INCLUDE_BSD

#   define SM_OFF_BOARD		TRUE       /* Memory pool is off-board */

   /* 
    * When shared memory anchor polling is enabled, the following defines the
    * PCI bus number on which to poll devices for the shared memory anchor.
    * If the PrPCM800 must cross over the backplane bus to access the anchor,
    * then #define  SYS_SM_BUS_NUMBER SYS_BACKPLANE_BUS_NUMBER .
    * If the PrPMC800 can stay on the local PCI bus to reach the anchor
    * then #define  SYS_SM_BUS_NUMBER SYS_LOCAL_PCI_BUS_NUMBER .
    */

#    define SYS_SM_BUS_NUMBER	SYS_BACKPLANE_BUS_NUMBER

#if (SYS_SM_BUS_NUMBER == SYS_LOCAL_PCI_BUS_NUMBER)
#   define PCI_SPACE_MEM         PCI_SPACE_MEM_PRI
#   define MSTR_MEM_BUS          LOCAL_PCI_MSTR_MEM_BUS
#else
#   define PCI_SPACE_MEM         PCI_SPACE_MEM_SEC
#   define MSTR_MEM_BUS          CPCI_MSTR_MEM_BUS
#endif                             


   /*
    * If the anchor is offboard (SM_OFF_BOARD == TRUE) then place the
    * anchor SM_ANCHOR_OFFSET at 0x4100 if the actual anchor is on an
    * MCP750 or MCPN750, or place it at 0x1100 if the actual anchor is
    * on a CPV5000.
    */

#   undef SM_ANCHOR_ADRS
#   if (SM_OFF_BOARD == TRUE)
#      undef SM_ANCHOR_OFFSET
#      define SM_ANCHOR_OFFSET 0x4100  /* define as 0x1100 for CPV5000 master */
#      define SM_ANCHOR_ADRS		(sysSmAnchorAdrs())
#      define SM_MEM_ADRS    (SM_ANCHOR_ADRS + (0x4d00 - SM_ANCHOR_OFFSET))
#   else /* (SM_OFF_BOARD == TRUE) */
#      define SM_MEM_ADRS    0x00004d00
#      define SM_ANCHOR_ADRS ((char *)(LOCAL_MEM_LOCAL_ADRS + SM_ANCHOR_OFFSET))
#   endif /* (SM_OFF_BOARD == TRUE) */

    /*
     * The following defines are only used by the master.
     * The slave only uses the "Anchor" address.
     */

#   define SM_MEM_SIZE		0x00010000
#   define SM_OBJ_MEM_ADRS	(SM_MEM_ADRS+SM_MEM_SIZE) /* SM Objects pool */

    /*
     * Finding the shared memory anchor:
     *
     * There are three ways to communicate the location of the anchor to the
     * initialization code:
     * 
     * 1) If "sm=xxxxxxxx" is specified as a boot parameter, then "xxxxxxxx"
     *    is used as the local address of the anchor.
     * 
     * 2) If case (1) above is not satisfied, then if SM_OFF_BOARD is FALSE,
     *    the address LOCAL_MEM_LOCAL_ADRS + SM_ANCHOR_OFFSET is used as the
     *    local address of the anchor.
     * 
     * 3) If neither (1) or (2) above is satisfied (that is "sm=xxxxxxxx" is
     *    NOT specified AND SM_OFF_BOARD is defined as TRUE) then the shared
     *    memory anchor is found via a polling algorithm as described below:
     *
     *    Devices on the compactPCI bus (defined by SYS_BACKPLANE_BUS_NUMBER)
     *    are queried through the first memory BAR.  Memory at offset
     *    SM_ANCHOR_OFFSET is examined to determine if the anchor is there.  
     *
     *    If SYS_SM_ANCHOR_POLL_LIST is defined then only those
     *    devices whose device/vendorID and subsystem device/vendorID
     *    are defined in this list are queried.  If SYS_SM_ANCHOR_POLL_LIST
     *    is NOT defined then ALL devices found on SYS_BACKPLANE_BUS_NUMBER
     *    are queried.
     *
     *    In addition if SYS_SM_SYSTEM_MEM_POLL is defined, the
     *    system memory (at compact PCI address CPCI_MSTR_MEM_BUS + 
     *    SM_ANCHOR_OFFSET) is also queried for a possible location for 
     *    the anchor.  If SYS_SM_SYSTEM_MEM_POLL is not defined, then 
     *    system memory is not polled.  This option would typically be 
     *    used if the anchor resided on an system slot controller and the 
     *    initialization code was running on the non-system slot controller.
     */

#   define SYS_SM_SYSTEM_MEM_POLL

#   ifndef _ASMLANGUAGE
        IMPORT  char * sysSmAnchorAdrs();
        int     sysSmIntTypeCompute (void);
        int     sysSmArg1Compute (int intType);
        int     sysSmArg2Compute (int intType);
        int     sysSmArg3Compute (void);
#   endif /* _ASMLANGUAGE */

    /* 
     * Legal settings for the following interrupt types are
     * either SM_INT_MAILBOX_1 or SM_INT_NONE
     */

#   define  SM_HOST_INT_TYPE  SM_INT_MAILBOX_1
#   define  SM_SLAVE_INT_TYPE SM_INT_MAILBOX_1

    /*
     * Because this BSP can operate in Monarch or non-Monarch mode, the
     * shared memory parameters must be calculated at run-time based on the
     * operating mode.
     */

#   define SM_INT_TYPE  (sysSmIntTypeCompute())
#   define SM_INT_ARG1  (sysSmArg1Compute(SM_INT_TYPE))
#   define SM_INT_ARG2  (sysSmArg2Compute(SM_INT_TYPE))
#   define SM_INT_ARG3  (sysSmArg3Compute())

#   define SYS_SM_ANCHOR_POLL_LIST \
	    SYS_MOT_SM_ANCHOR_POLL_LIST	/* shared memory boards ID list */

#endif /* defined(INCLUDE_SM_COMMON) */


#ifdef INCLUDE_SM_OBJ
#   define SM_OBJ_MEM_SIZE	0x00010000
#endif /* INCLUDE_SM_OBJ */

/*
 * Note: This BSP requires a modified software Test and Set algorithm.
 * SM_TAS_TYPE is set to SM_TAS_HARD despite the lack of a hardware TAS
 * mechanism to force the use of a BSP-specific software TAS algorithm. The
 * modified algorithm is required to work around a problem encountered with
 * PCI-to-PCI bridges.
 */

#undef SM_TAS_TYPE
#define SM_TAS_TYPE 	SM_TAS_HARD

/*
 * The following must be a value between 0 and 15.  It represents the 
 * bit number of the primary doorbell register used to interrupt the 
 * MCP750 for shared memory bus interrupts. 
 */

#define DEC2155X_SM_DOORBELL_BIT 0

/*
 * These defines are used to initialize the External Source
 * Vector/Priority registers in the MPIC.  The following can
 * be defined: interrupt sensitivity, polarity and interrupt priority.
 *
 * Note: by default a 1 into the sense bit(22) will set up for active
 * low (interrupt sources 1 thru 15).  A 1 into the polarity bit
 * affects only interrupt source zero and sets it up for high level
 * sensitive interrupts.
 *
 * At initialization all external interrupt sources are disabled
 * except for the Comm1 input, which is enabled in the MPIC driver.
 *
 * All currently unused interrupt sources are set to a priority of
 * 0, which will not allow them to be enabled.  If any one of these
 * levels is to be used, the priority value must be changed here.
 */

#define INIT_EXT_SRC0           ( INT_MASK_BIT | LEVEL_SENSE |\
                                  PRIORITY_LVL0 )   /* Host Bus INT0 */

#define INIT_EXT_SRC1           ( INT_MASK_BIT | LEVEL_SENSE |\
                                  PRIORITY_LVL0 )   /* not used */
 
#define INIT_EXT_SRC2           ( INT_MASK_BIT | LEVEL_SENSE |\
                                  PRIORITY_LVL8 )   /* DEBUG */
 
#define INIT_EXT_SRC3           ( INT_MASK_BIT | LEVEL_SENSE |\
                                  PRIORITY_LVL0 )   /* WDT1/WDT2 */
 
#define INIT_EXT_SRC4           ( INT_MASK_BIT | LEVEL_SENSE |\
                                  PRIORITY_LVL4 )   /* M48T37V */

#define INIT_EXT_SRC5           ( INT_MASK_BIT | LEVEL_SENSE |\
                                  PRIORITY_LVL0 )   /* not used */
 
#define INIT_EXT_SRC6           ( INT_MASK_BIT | LEVEL_SENSE |\
                                  PRIORITY_LVL14 )  /* Host Bus INT1 */
 
#define INIT_EXT_SRC7           ( INT_MASK_BIT | LEVEL_SENSE |\
                                  PRIORITY_LVL14 )  /* Host Bus INT2 */
 
#define INIT_EXT_SRC8           ( INT_MASK_BIT | LEVEL_SENSE |\
                                  PRIORITY_LVL14 )  /* Host Bus INT3 */

#define INIT_EXT_SRC9           ( INT_MASK_BIT | LEVEL_SENSE |\
                                  PRIORITY_LVL3 )   /* PMC1A || DEC21554 */
 
#define INIT_EXT_SRC10          ( INT_MASK_BIT | LEVEL_SENSE |\
                                  PRIORITY_LVL3 )   /* PMC1B || i82559 */
 
#ifdef SLAVE_OWNS_ETHERNET
#   define INIT_EXT_SRC11       ( INT_MASK_BIT | LEVEL_SENSE |\
                                  PRIORITY_LVL0 )   /* PMC1C */
 
#   if (CARRIER_TYPE == PRPMC_BASE) && defined(INCLUDE_DEC_END)
#      define INIT_EXT_SRC12    ( INT_MASK_BIT | LEVEL_SENSE |\
                                  PRIORITY_LVL3 )   /* PMC1D */
#   else
#      define INIT_EXT_SRC12    ( INT_MASK_BIT | LEVEL_SENSE |\
                                  PRIORITY_LVL0 )   /* PMC1D */
#   endif /* (CARRIER_TYPE == PRPMC_BASE) && defined(INCLUDE_DEC_END) */

#else  /* !SLAVE_OWNS_ETHERNET */
#   define INIT_EXT_SRC11       ( INT_MASK_BIT | LEVEL_SENSE |\
                                  PRIORITY_LVL3 )   /* PMC1C */
 
#   define INIT_EXT_SRC12       ( INT_MASK_BIT | LEVEL_SENSE |\
                                  PRIORITY_LVL3 )   /* PMC1D */
#endif /* SLAVE_OWNS_ETHERNET */
 
#define INIT_EXT_SRC13          ( INT_MASK_BIT | LEVEL_SENSE |\
                                  PRIORITY_LVL0 )   /* not used */
 
#define INIT_EXT_SRC14          ( INT_MASK_BIT | LEVEL_SENSE |\
                                  PRIORITY_LVL0 )   /* not used */
 
#define INIT_EXT_SRC15          ( INT_MASK_BIT | LEVEL_SENSE |\
                                  PRIORITY_LVL0 )   /* not used */

/* Internal Harrier Functional Interrupt Sources */

#define INIT_INT_SRC0           ( INT_MASK_BIT | LEVEL_SENSE |\
                                  PRIORITY_LVL8 )
#define INIT_INT_SRC1           ( INT_MASK_BIT | LEVEL_SENSE |\
                                  PRIORITY_LVL9 )

 
/* BSP-specific includes */

#include "prpmc800.h"

/* 
 * The prpmc800 has two Ethernet devices. One on-board and one on the 
 * base-board.  The following macro is to determine which is the primary 
 * Ethernet device to be used as the "boot" device.
 * Slave Ethernet support is only supported on the PrPMCBase board.
 */

#if (CARRIER_TYPE == PRPMC_BASE)
#   define PCI_IDSEL_PRI_LAN	17  /* On-board i82559 Ethernet device */
#   define PCI_IDSEL_SEC_LAN	14  /* Base board DEC21143 Ethernet device */
#   define PCI_IDSEL_SLAVE_LAN	18  /* Slave's On-board i82559 Ethernet device*/

#elif (CARRIER_TYPE == PRPMC_CARRIER_1)
#   define PCI_IDSEL_PRI_LAN	17  /* On-board i82559 Ethernet device*/
#   define PCI_IDSEL_SEC_LAN	 2  /* First i82559 on PrPMC Carrier 1*/
#   define PCI_IDSEL_TER_LAN	 5  /* Second i82559 on PrPMC Carrier1*/

#elif (CARRIER_TYPE == PRPMC_G)

    /*
     * The Primary Ethernet on the PrPMC-G is the 82543 Gigabit Ethernet.
     *
     * The Secondary Ethernet is the PrPMC800 on-board i82559 Ethernet,
     * but the Gigabit Ethernet driver doesn't use PCI_IDSEL_PRI_LAN,
     * so it is simpler to leave sysFei82557End.c alone and let it "think"
     * the i82559 is the Primary, when it is actually the Secondary Ethernet.
     */

#   define PCI_IDSEL_PRI_LAN	17  /* On-board i82559 Ethernet device*/
#   define PCI_IDSEL_SEC_LAN	PCI_IDSEL_PRI_LAN

#endif /* (CARRIER_TYPE == PRPMC_BASE) */

#ifdef __cplusplus
    }
#endif /* __cplusplus */

#if defined(PRJ_BUILD)
    #include "prjParams.h"
#endif /* PRJ_BUILD */

#endif	/* INCconfigh */