config.h

vxworks的bsp开发包(基于POWERPC的PRPMC800)

/*
 * NOTE: The following define works around a problem encountered with the
 * 21554's secondary bus arbiter. By default, the Processor Host Bridge will 
 * perform a speculative PCI request when a PCI-bound transaction has been 
 * retried due to PCI lock resolution. This behavior is not compatible with 
 * the 21554's secondary bus arbiter. To prevent arbiter lock-ups, speculative 
 * PCI bus requests should be disabled if a 21554 is used as the PCI bus 
 * arbiter.
 */ 

#define DISABLE_SPRQ	/* undef if not using 21554 as PCI bus arbiter */

/* This table describes the PrPMC800 PCI IDSEL-to-MPIC interrupt routing. */

#define INTERRUPT_ROUTING_TABLE \
static UCHAR intLine [][4] = \
    { \
        { 0xff, 0xff, 0xff, 0xff }, /* device number 0/31, PCI Host bridge */ \
        { 0xff, 0xff, 0xff, 0xff }, /* device number 1  - not available */ \
        { 0xff, 0xff, 0xff, 0xff }, /* device number 2  - not available */ \
        { 0xff, 0xff, 0xff, 0xff }, /* device number 3  - not available */ \
        { 0xff, 0xff, 0xff, 0xff }, /* device number 4  - not available */ \
        { 0xff, 0xff, 0xff, 0xff }, /* device number 5  - not available */ \
        { 0xff, 0xff, 0xff, 0xff }, /* device number 6  - not available */ \
        { 0xff, 0xff, 0xff, 0xff }, /* device number 7  - not available */ \
        { 0xff, 0xff, 0xff, 0xff }, /* device number 8  - not available */ \
        { 0xff, 0xff, 0xff, 0xff }, /* device number 9  - not available */ \
        { 0xff, 0xff, 0xff, 0xff }, /* device number 10 - not available */ \
        { 0xff, 0xff, 0xff, 0xff }, /* device number 11 */ \
        { 0xff, 0xff, 0xff, 0xff }, /* device number 12 */ \
        { 0xff, 0xff, 0xff, 0xff }, /* device number 13 */ \
        { LN2_INT_VEC,              /* device number 14, DEC 21143 Ethernet */\
          0xff,\
          0xff,\
          0xff },\
        { 0xff, 0xff, 0xff, 0xff }, /* device number 15 */ \
        { PCI_INTA_VEC,	            /* device number 16, PMC slot 1 */\
          PCI_INTB_VEC,\
          PCI_INTC_VEC,\
          PCI_INTD_VEC },\
        { LN1_INT_VEC,              /* device number 17, i82559 Ethernet */\
          0xff,\
          0xff,\
          0xff },\
        { SLV_LN1_INT_VEC,          /* device number 18, Slv i82559 Ethernet */\
          PCI_INTD_VEC,\
          PCI_INTA_VEC,\
          PCI_INTB_VEC },\
        { 0xff, 0xff, 0xff, 0xff }, /* device number 19 */ \
        { CPCI_INT_VEC,	            /* device number 20 DEC21554 */ \
          PCI_INTB_VEC,\
          PCI_INTC_VEC,\
          PCI_INTD_VEC },\
        { 0xff, 0xff, 0xff, 0xff }, /* device number 21 */ \
        { 0xff, 0xff, 0xff, 0xff }, /* device number 22 */ \
        { 0xff, 0xff, 0xff, 0xff }, /* device number 23 */ \
        { 0xff, 0xff, 0xff, 0xff }, /* device number 24 */ \
        { 0xff, 0xff, 0xff, 0xff }, /* device number 25 */ \
        { 0xff, 0xff, 0xff, 0xff }, /* device number 26 */ \
        { 0xff, 0xff, 0xff, 0xff }, /* device number 27 */ \
        { 0xff, 0xff, 0xff, 0xff }, /* device number 28 */ \
        { 0xff, 0xff, 0xff, 0xff }, /* device number 29 */ \
        { LN2_INT_VEC,              /* device number 30,PrPMC-G 82543 Gigabit*/\
          0xff,\
          0xff,\
          0xff }\
    };

/*
 * static define for ethernet chip interrupt. Only used if PCI Auto-Config
 * is disabled (debug).
 */

#define LN_INT_LVL	PCI_INT_LVL4

/* MMU and Cache options */

#define	INCLUDE_MMU_BASIC       /* bundled mmu support */

#undef	USER_D_CACHE_MODE
#define	USER_D_CACHE_MODE       (CACHE_COPYBACK | CACHE_SNOOP_ENABLE)
#undef	USER_I_CACHE_MODE
#define	USER_I_CACHE_MODE       (CACHE_COPYBACK | CACHE_SNOOP_ENABLE)

#ifdef  INCLUDE_CACHE_L2
#   define USER_L2_CACHE_ENABLE	/* enable the L2 cache */
#endif  /* INCLUDE_CACHE_L2 */

/* timestamp option not included by default;  #define to include it */

#undef  INCLUDE_TIMESTAMP

/* De-select unused (default) network drivers selected in configAll.h */

#undef  INCLUDE_EX              /* include Excelan Ethernet interface */
#undef  INCLUDE_ENP             /* include CMC Ethernet interface*/

#define	INCLUDE_END		/* Enhanced Network Driver (see configNet.h) */

/* PCI bus numbers for secondary and subordinate buses */

#define PCI_SECONDARY_BUS       1
#define PCI_SUBORD_BUS          1
#define PCI_MAX_BUS             2       /* Max. number of PCI buses in system */

/* Dec2155x (Drawbridge) configuration parameters */

#define DEC2155X_SUB_VNDR_ID_VAL    MOT_SUB_VNDR_ID_VAL
#define DEC2155X_SUB_SYS_ID_VAL     PRPMCBASE_SUB_SYS_ID_VAL

/* Harrier configuration parameters */

#define HARRIER_SUB_VNDR_ID_VAL	    PRPMC800_SUB_SYS_ID_VAL
#define HARRIER_SUB_SYS_ID_VAL      MOT_SUB_VNDR_ID_VAL

#ifdef INCLUDE_DEC2155X
#   define DEC2155X_PCI_DEV_NUMBER 0x14
#   define DEC2155X_PCI_BUS_NUMBER 0x00

    /*
     * the following define assigns all PCI arbiter inputs to the high-priority
     * group. for details, consult the 21554 user's manual.
     */

#   define DEC2155X_ARB_CTRL_VAL    DEC2155X_ARB_CTRL_MSK

    /*
     * a PCI read from the following cPCI memory address is used to flush the
     * Dec2155x write post buffer. It must be a valid location and free of
     * side effects. The default value targets location 0x00000000 in host DRAM.
     */

#   define CPCI_FLUSH_ADDR CPCI_MSTR_MEM_BUS

    /*
     * NOTE: Window sizes must be an integral power of 2 and translation
     * values must be an even multiple of the window size. To enable
     * prefetch on a memory window "or" in PCI_BAR_MEM_PREFETCH.
     */

    /* Downstream windows (for access from Compact PCI backpanel) */

    /*
     * note that downstream translation values are relative to the local PCI
     * memory map not the local processor address map. PCI_SLV_MEM_BUS is
     * the base of the local DRAM as seen from the local PCI bus (secondary
     * side of the 2155x).  The Processor Host bridge will translate this into 
     * a local DRAM address.
     */

    /* 4MB window into local DRAM (first 4KB accesses 2155x CSR reg set). */

#   define DEC2155X_CSR_AND_DS_MEM0_SIZE 0x00400000

#   define DEC2155X_CSR_AND_DS_MEM0_TYPE (PCI_BAR_SPACE_MEM | \
                                          PCI_BAR_MEM_ADDR32)

#   define DEC2155X_CSR_AND_DS_MEM0_TRANS PCI_SLV_MEM_BUS

    /* Downstream window 1 to map Harrier Message Passing (doorbell) space. */

#   define DEC2155X_DS_IO_OR_MEM1_SIZE   0x04000000	/* 64 MB */
#   define DEC2155X_DS_IO_OR_MEM1_TYPE   (PCI_BAR_SPACE_MEM | \
                                          PCI_BAR_MEM_ADDR32)
#   define DEC2155X_DS_IO_OR_MEM1_TRANS  PCI_SLV_PMEP_BUS

    /* Downstream windows 2 and 3 not used (disabled) */

#   define DEC2155X_DS_MEM2_SIZE         0x00000000
#   define DEC2155X_DS_MEM2_TYPE         (PCI_BAR_SPACE_MEM| \
                                          PCI_BAR_MEM_ADDR32 )
#   define DEC2155X_DS_MEM2_TRANS        0x00000000

#   define DEC2155X_DS_MEM3_SIZE         0x00000000
#   define DEC2155X_DS_MEM3_TYPE         (PCI_BAR_SPACE_MEM| \
                                          PCI_BAR_MEM_ADDR32 )
#   define DEC2155X_DS_MEM3_TRANS        0x00000000

    /* Upstream windows (for access to Compact PCI backpanel) */

    /*
     * note that upstream translation values are relative to the Compact PCI
     * memory map not the local processor address map. 0x00000000 is the
     * base of PCI memory space as seen from the Compact PCI bus (primary
     * side of the 2155x).
     */

    /* 4MB window into host (system slot) DRAM. */

#    define DEC2155X_US_IO_OR_MEM0_SIZE 0x00400000
#    define DEC2155X_US_IO_OR_MEM0_TYPE (PCI_BAR_SPACE_MEM | \
                                         PCI_BAR_MEM_ADDR32)

#   define DEC2155X_US_IO_OR_MEM0_TRANS CPCI_MSTR_MEM_BUS /* map to DRAM */

    /*
     * 512 MB window into Compact PCI memory space to access non-system boards
     * NOTE: this window must be large enough to cover the pci memory area
     * configured in the host for dynamic pci device allocation. the
     * translation value for this window should equal the pci memory base
     * address for this area.
     */

#   define DEC2155X_US_MEM1_SIZE 0x20000000
#   define DEC2155X_US_MEM1_TYPE (PCI_BAR_SPACE_MEM | \
                                  PCI_BAR_MEM_ADDR32)

#   define DEC2155X_US_MEM1_TRANS 0x00000000 

#   define DEC2155X_US_MEM2_PG_SZ 0x00000000 /* close window */

#endif /* INCLUDE_DEC2155X */

/*
 * Slave-Mode PrPMC Parameters
 *
 * These parameters are used by the BSP when it is operating as a PCI
 * Slave device (non-monarch mode).
 */

#define PRPMC_SLAVE_SUB_VNDR_ID_VAL	MOT_SUB_VNDR_ID_VAL
#define PRPMC_SLAVE_SUB_SYS_ID_VAL	PRPMC800_SUB_SYS_ID_VAL

/*
 * The following defines set the amount of time allowed for Slave-Mode PrPMC
 * Auto-Configuration. The value of PRPMC_SLAVE_INFINTE_TIMEOUT disables the
 * timeout, resulting in an infinite wait. The PRPMC_SLAVE_SIDE_TIMEOUT controls
 * the amount of time the Slave-Mode device will wait for configuration by the
 * PCI Host.  If an infinite timeout is not specified, the Slave will wait
 * PRPMC_SLAVE_SIDE_TIMEOUT mSecs for the PCI Host to complete the enumeration.
 */

#define PRPMC_SLAVE_INFINITE_TIMEOUT	0xffffffff
#define PRPMC_SLAVE_SIDE_TIMEOUT	PRPMC_SLAVE_INFINITE_TIMEOUT

/*
 * The following defines the amount of time allowed for system controller
 * initialization of the primary side of the Dec2155x (drawbridge) non-
 * transparent bridge.  The value of  PRPMC_DRAWBRIDGE_INFINITE_TIMEOUT 
 * disables the timeout, resulting in an infinite wait.  The 
 * PRPMC_DRAWBRIDGE_TIMEOUT controls the amount of time the PrPMC will
 * wait for the configuration of the Dec2155x drawbridge by the system
 * controller.  If an infinite timeout is not specified, the PrPMC will wait
 * PRPMC_DRAWBRIDGE_TIMEOUT mSecs for the system controller to complete
 * the drawbridge configuration and it will then proceed whether or not
 * the configuration is complete.
 */

#define PRPMC_DRAWBRIDGE_INFINITE_TIMEOUT  0xffffffff
#define PRPMC_DRAWBRIDGE_TIMEOUT	   PRPMC_DRAWBRIDGE_INFINITE_TIMEOUT

/*
 * The following define controls the interrupt routing used for generating 
 * outbound PCI bus interrupts. The default value matches the routing required
 * by the PCI Spec for a single interrupt PCI device (INTA).
 */

#define PRPMC_SLAVE_BUS_INT_ROUTE	0

/*
 * The following define sets the address space advertised for the Slave-Mode
 * in-bound mailbox and is currently not used. The default value is
 * PCI_SPACE_MEM_PRI.
 */

#define PRPMC_SLAVE_MAILBOX_SPACE       PCI_SPACE_MEM_PRI


/* End of Slave-Mode PrPMC Defines */
/* serial parameters */

#undef	NUM_TTY
#define	NUM_TTY			N_SIO_CHANNELS

/*
 * Auxiliary Clock support is an optional feature that is not supported
 * by all BSPs.  Since it requires the MPIC timers, the Auxiliary Clock
 * is only supported in MPIC mode.
 */

#if defined(INCLUDE_SPY)
#    define INCLUDE_AUX_CLK                /* specify aux clock device */
#endif /* INCLUDE_SPY */

/*
 * Local Memory definitions
 *
 * By default, the available DRAM memory is sized at bootup (LOCAL_MEM_AUTOSIZE
 * is defined).  If auto-sizing is not selected, make certain that
 * LOCAL_MEM_SIZE is set to the actual amount of memory on the board.
 * By default, it is set to the minimum memory configuration: 32 MB.
 * Failure to do so can cause unpredictable system behavior!
 */

#define	LOCAL_MEM_AUTOSIZE			/* undef for fixed size */
#define LOCAL_MEM_LOCAL_ADRS	0x00000000	/* fixed at zero */
#define LOCAL_MEM_SIZE		0x04000000	/* Default: Min memory: 64MB */

#define RAM_HIGH_ADRS		0x00800000  	/* RAM address for ROM boot */
#define RAM_LOW_ADRS		0x00100000	/* RAM address for kernel */

/* user reserved memory, see sysMemTop() */

#define USER_RESERVED_MEM	(0)	/* number of reserved bytes */

/*
 * The constants ROM_TEXT_ADRS, ROM_SIZE, RAM_LOW_ADRS and RAM_HIGH_ADRS 
 * are defined in config.h, Makefile.
 * All definitions for these constants must be identical.
 */

#define	ROM_BASE_ADRS		0xfff00000	/* base address of ROM */
#define	ROM_TEXT_ADRS		(ROM_BASE_ADRS + 0x100)

#define	ROM_SIZE		0x00100000	/* 1 Meg ROM space */

/* Shared-memory parameters */

/*
 * INCLUDE_SM_NET and INCLUDE_SM_SEQ_ADDR are the shared memory backplane
 * driver and the auto address setup.  These must be #define'd here in
 * order to configure this BSP for participation in a shared-memory
 * network. These must be undefined for CARRIER_1 and PRPMC_G as there is no
 * shared memory capability.
 */

#undef INCLUDE_SM_NET
#undef INCLUDE_SM_SEQ_ADDR