config.h

vxworks的bsp开发包(基于POWERPC的PRPMC800)

/* config.h - Motorola PowerPlusIII board configuration header */

/* Copyright 1984-2001 Wind River Systems, Inc. */
/* Copyright 1996-2001 Motorola, Inc. All Rights Reserved */

/*
modification history
--------------------
02a,10may02,dtr  Update for shared memory in Tornado 2.2. SPR 73457
01z,11mar02,dtr  Undefining SM_NET SM_SEQ_ADRS and ALTIVEC.
01y,14dec01,dtr  Coding error for SM Bus selection.
01x,06dec01,dtr  Some pre-processor checks don't work.
		 Making INCLUDE_SM_NET conditional on PRPMC_BASE.
		 Adding some comments for DEC2155X define.
01w,25nov01,dtr  Modification for PRPMC_G default PCI_DRAM_MAP_SIZE and 
                 BSP_VERSION.
01v,16nov01,scb  Shared memory fixes using mcpn765 as carrier.
01u,15oct01,scb  Mods to integrate WRS fei driver in lieu of i82559 driver.
01t,10oct01,scb  Modifications for shared-memory support.
01s,31jul01,srr  Added PrPMC-G Gigabit Ethernet and PrPMC Carrier 1 support.
01r,18jun01,srr  Added Harrier DMA support.
01q,14jun01,srr  Fix problem with dec21554 interrupt enabling and updated
                 information about Slave memory in PCI_MSTR_MEMIO space.
01p,12jun01,srr  Removed unneeded PrPMC definitions.
01o,14may01,bvc  Removed unneeded INCLUDE_MOT_BUG_ROM and ATA support.
01n,08jan01,dmw  Changed PCI window sizes for Slave Ethernet support.
01m,08jan01,krp  Changed window size of flash Bank 'A'
01l,05jan01,krp  The erroneous reference to INCLUDE_ATA was removed.
01k,07dec00,krp  Added support for Watchdog Timer
01j,21nov00,dmw  Removed stand-alone defines.
01i,17nov00,dmw  Added slave Ethernet support.
01h,14nov00,dmw  Fixed FLASH Bank 1's size.
01g,27oct00,dmw  Added Xport addresses and sizes.
01f,12oct00,dmw  Documentation cleanup.
01e,09oct00,dmw  Turned on MMU.
01d,08oct00,dmw  Turned off aux clock and MMU.
01c,12sep00,dmw  Added Harrier internal interrupts.
01b,07sep00,dmw  Removed PReP address map for PowerPlusIII.
01a,31jul00,dmw  Written. (from ver 01l, mcpn765/config.h)
*/

/*
This file contains the configuration parameters for the
Motorola PowerPlusIII architecture
*/

#ifndef	INCconfigh
#define	INCconfigh

#ifdef __cplusplus
    extern "C" {
#endif /* __cplusplus */

/* The following defines must precede configAll.h */

/* BSP version/revision identification */

#define BSP_VER_1_1     1
#define BSP_VER_1_2     1
#define BSP_VERSION     "1.2"
#define BSP_REV         "/1"

/* PRIMARY INCLUDES */

#include "configAll.h"
#include "sysMotCpci.h"

/* defines */

#define DEFAULT_BOOT_LINE \
	"fei(0,0)host:/tornado/prpmc800/vxWorks h=90.0.0.1 e=90.0.0.2 u=vxworks"
#define WRONG_CPU_MSG "A PPC604 VxWorks image cannot run on a PPC603!\n";

/*
 * CPCI_MSTR_MEM_BUS accesses the beginning of system
 * (cPCI master) DRAM.  This should be set to:
 *     0x80000000 if the cPCI master is an MCP750;
 *     0x00000000 if the cPCI master is a CPV5000.
 * LOCAL_PCI_MSTR_MEM_BUS accesses the beginning of local
 * (PCI master) DRAM.
 * 
 */

#define CPCI_MSTR_MEM_BUS	0x80000000
#define LOCAL_PCI_MSTR_MEM_BUS	0x0

/*
 * Default board configurations
 *
 * If a supported feature is desired,
 *         change to: #define
 * If a feature is not desired or not supported
 *         change to: #undef
 *
 * NOTE: Not all functionality is supported on all boards
 */

#define	INCLUDE_I8250_SIO       /* COM1 thru COM4 are 16C550 UARTS */
#define	INCLUDE_CACHE_L2        /* L2 cache support */
#define	INCLUDE_ECC             /* Harrier SMC ECC */
/* Undefining INCLUDE_BPE will cause machine check, bus parity exceptions 
 * to be disabled in romInit.s */
#define	INCLUDE_BPE             /* Processor bus Parity checking */
#define	INCLUDE_DPM             /* Dynamic Power Management */
#undef	INCLUDE_AUX_CLK          /* Harrier aux clock */
#undef	INCLUDE_HARRIER_DMA     /* Harrier DMA */
#define INCLUDE_DEC2155X        /* Intel/DEC 21554 PCI-to-PCI bridge 
				   Only on PRPMC_BASE which is default*/
#undef	INCLUDE_SECONDARY_ENET	/* Enable Secondary Ethernet */
#undef	INCLUDE_TERTIARY_ENET	/* Enable Tertiary Ethernet on Carrier 1 only */
#undef  INCLUDE_PRPMC800XT      /* Extended version of the PrPMC800 */
#define INCLUDE_FEI_END
#undef  INCLUDE_DEC_END         /* Support for DEC21x4x driver. */
#undef  INCLUDE_GEI_END
#undef  INCLUDE_ALTIVEC         /* Support for Altivec coprocessor */
#undef  INCLUDE_TFFS

#ifdef  INCLUDE_TFFS
#define INCLUDE_DOSFS
#endif

/*
 * Carrier boards available for selection:
 * PRPMC_BASE (default), PRPMC_CARRIER_1, PRPMC_G
 */

#define CARRIER_TYPE		PRPMC_BASE

/*
 * If the Primary Ethernet device on the Carrier 1 board is the
 * PrPMC800 onboard i82559 device, then PCI_CARRIER_1_PRI_BUS must
 * be set to 0 (default).  Otherwise, if the Primary Ethernet device
 * is one of the two Carrier 1 onboard i82559 devices, the value
 * must be set to 1.
 */

#define PCI_CARRIER_1_PRI_BUS	 0  /* PCI Bus Primary i82559 is on */

#   define VM_STATE_MASK_FOR_ALL \
           VM_STATE_MASK_VALID | VM_STATE_MASK_WRITABLE |VM_STATE_MASK_CACHEABLE
#   define VM_STATE_FOR_IO \
           VM_STATE_VALID | VM_STATE_WRITABLE | VM_STATE_CACHEABLE_NOT
#   define VM_STATE_FOR_MEM_OS \
           VM_STATE_VALID | VM_STATE_WRITABLE | VM_STATE_CACHEABLE
#   define VM_STATE_FOR_MEM_APPLICATION \
           VM_STATE_VALID | VM_STATE_WRITABLE | VM_STATE_CACHEABLE
#   define VM_STATE_FOR_PCI \
           VM_STATE_VALID | VM_STATE_WRITABLE | VM_STATE_CACHEABLE_NOT

/* 
 *  Watchdog timer support - ONLY on the PrPMC800 Extended board  
 */

#undef  INCLUDE_M48T559WDT      
                               

/* 
 * The following define controls the Slave's use of its onboard Ethernet.
 * Defining SLAVE_OWNS_ETHERNET will allow the Slave to install the
 * Ethernet driver and connect/enable the Ethernet interrupt.
 */

#undef  SLAVE_OWNS_ETHERNET       

/*
 * NONFATAL_VPD_ERRORS is a debug build switch which, when defined, allows
 * the BSP to tolerate what would otherwise be fatal VPD errors.
 */

#undef     NONFATAL_VPD_ERRORS  /* define to debug VPD info */

/*
 * BYPASS_VPD_PCO is a debug build switch which, when defined, causes the
 * BSP to ignore the VPD Product Configuration Options bit array and use
 * a default configuration which assumes one serial port (debug console) and
 * one Ethernet device (Unit 0).
 */

#undef     BYPASS_VPD_PCO       /* define to ignore VPD PCO */

/*
 * BYPASS_SPD is a debug build switch which, when defined, forces the BSP
 * to ignore SPD information and assume a 32MB SDRAM array and configures
 * the system memory controller for default (worst case) memory timing. It 
 * will also produce a Group A 0x40000000 Bootrom Error message at startup 
 * as a reminder that default timing is in use.
 */

#undef     BYPASS_SPD	    /* define to debug SPD info */

/*
 * PCI_MSTR_IO_SIZE, PCI_MSTR_MEMIO_SIZE and PCI_MSTR_MEM_SIZE control the
 * sizes of the available PCI address spaces. The windows defined by these
 * parameters must be large enough to accommodate all of the PCI memory and
 * I/O space requests found during PCI autoconfiguration. If they are not,
 * some devices will not be autoconfigured.
 *
 * Be aware that these values alter entries in the sysPhysMemDesc[] array
 * (in sysLib.c) and affect the size of the resulting MMU tables at the
 * rate of 128:1. For each 128K of address space, a 1K piece of RAM will be
 * used for MMU tables.  If the region is very large, modifications to
 * sysLib.c can be made to use BAT (Block Address Translation) registers
 * instead of MMU page tables to map the memory.
 *
 * PCI_MSTR_MEMIO_LOCAL which is defined below with a default value
 * of 0x40000000 (1-GigaByte) defines the beginning local (processor-based)
 * address of PCI memory space.  The value may be altered if desired but
 * be aware that the value of PCI_MSTR_MEMIO_LOCAL should always be greater
 * than or equal to the amount of DRAM on the largest prpmc800 in a
 * Monarch/Slave pairing.  If it is not there will be PCI memory which
 * unaccessible to the prpmc800 with the larger amount of DRAM.
 *
 * NOTE: Since PCI auto-configuration is performed by the bootroms,
 *       changing any of these values requires the creation of new bootroms.
 */

/*
 * The Extended PCI map (Pseudo-CHRP) maximizes PCI mapped Memory space.
 *
 * CPU Space   -----------------  PCI Space (these are the values used
 *            |                 |            for autoconfig setup)
 *            |                 |
 * sysMemTop   ----------------- 
 *            :  Unused         :
 *            :                 :
 *             ----------------- PCI_MSTR_MEMIO_LOCAL 
 *            | NPREF PCI MEM   |
 * + 0x800000  ----------------- PCI_MSTR_MEM_LOCAL = PCI_MSTR_MEMIO_LOCAL +
 *            | PCI 32-bit MEM  |                     PCI_MSTR_MEMIO_SIZE
 *            |                 |
 *            |                 | 
 *             ----------------- PCI_MSTR_ZERO_LOCAL = PCI_MSTR_MEM_LOCAL + 
 *            | Maps to Local   |                      PCI_MSTR_MEM_SIZE
 *            | PCI address 0   |
 *             ----------------- PCI_MSTR_ZERO_LOCAL + PCI_MSTR_ZERO_SIZE
 *            :                 :
 *            :                 :
 * 0xF0000000  ----------------- Flash Bank 'A' 32MB
 *            |                 | 
 * 0xF1FFFFFF  ----------------- 
 * 0xFC000000  ----------------- 
 *            | MPIC registers  |
 * 0xFD000000  ----------------- ISA_MSTR_IO_LOCAL
 *            | ISA LEGACY      |
 * 0xFD004000  ----------------- ISA_MSTR_IO_LOCAL + ISA_LEGACY_SIZE
 *            | PCI 16-bit I/O  |
 * 0xFD010000  ----------------- ISA_MSTR_IO_LOCAL + ISA_MSTR_IO_SIZE
 *            | PCI 32-bit I/O  |
 * 0xFE810000  ----------------- PCI_MSTR_IO_LOCAL + PCI_MSTR_IO_SIZE
 * 0xFEFF0000  ----------------- HARRIER_XCSR_BASE
 *            | Harrier XCSRs   |
 * 0xFFEF4000  ----------------- 
 *
 * PCI Mapped Memory consists of non-prefetchable and prefetchable.
 * 
 * The maximum amount of non-prefetchable PCI memory is defined by
 * the value of PCI_MSTR_MEMIO_SIZE.
 *
 * The amount of prefetchable PCI memory is defined by the value of
 * PCI_MSTR_MEM_SIZE.  The map for prefetchable and noprefetchable
 * PCI memory must not extend beyond the flash bank address of
 * 0xF0000000.  
 *
 * That is:
 * PCI_MSTR_MEMIO_LOCAL + PCI_MSTR_MEMIO_SIZE + PCI_MSTR_MEM_SIZE must
 * be less than 0xF0000000.
 *
 * PCI Mapped I/O consists of 16 and 32 bit I/O.
 *
 * The amount of 16 bit I/O is configured by ISA_MSTR_IO_SIZE and defaults
 * to 64KB.
 *
 * The amount of 32 bit I/O is configured by PCI_MSTR_IO_SIZE.  This size
 * is determined by the user but cannot overrun the System Memory 
 * Controller Registers at 0xFEF80000.
 *
 * Therefore:
 * the maximum value of PCI_MSTR_IO_SIZE = 
 *                                    System Memory Controller Registers - 
 *                                    (ISA_MSTR_IO_LOCAL + ISA_MSTR_IO_SIZE)
 *                                        
 * - or -           max PCI_MSTR_IO_SIZE = 0xFEF80000 - 
 *                                                (0xFE000000 + 0x00010000)
 *
 * - or -           max PCI_MSTR_IO_SIZE =  0x00F70000
 *
 * PCI_MSTR_ZERO_SIZE - represents the amount of memory at PCI bus
 * address zero which will be mapped on an outbound window
 * in the host bridge.  See #define of PCI_MSTR_ZERO_LOCAL (in
 * another header file), which represents the local (processor) address 
 * address of this memory region.
 *
 */

#define PCI_MSTR_IO_SIZE     0x00800000           /* 8MB (default) */

#define PCI_MSTR_MEMIO_LOCAL ((UINT)0x40000000)           /* 1 GB */
#define PCI_MSTR_MEMIO_SIZE  ((UINT)0x40000000)           /* 1 GB */
#define PCI_MSTR_MEM_SIZE    ((UINT)0x00800000)           /* 8 MB */
#define PCI_MSTR_ZERO_SIZE   ((UINT)0x00400000)		  /* 4 MB */

/* 
 * PCI2DRAM_MAP_SIZE governs how large a piece of low-order DRAM will
 * be mapped onto the local PCI bus through the Harrier inbound translation
 * zero register set.  16MB (0x01000000) is the minimum amount which will
 * allow for proper operation of ethernet devices - such devices must use
 * preallocated buffers for their descriptors and these buffers appear
 * between the 8MB and 16MB in DRAM.
 *
 * To handle the start offset of the bootrom, PCI2DRAM_MAP_SIZE must be
 * larger than RAM_HIGH_ADRS to include the Ethernet buffers in the window
 * visible from the PCI bus.
 *
 * For the PRPMC_G the PCI2DRAM_MAP_SIZE cannot be truncated it must be set to
 * size of the local dram to use the gigabit driver.
 */

#define PCI2DRAM_MAP_SIZE    (RAM_HIGH_ADRS + 0x00800000)    /* configured for PRPMC_BASE,PRPMC_CARRIER. */


#define PRPMC800_XPORT0_ADDR         0xF0000000   /* Xport0 */
#define PRPMC800_XPORT1_ADDR         0xFF800000   /* Xport1 */
#define PRPMC800_XPORT2_ADDR         0xFF100000   /* Xport2 */
#define PRPMC800_XPORT3_ADDR         0xFF200000   /* Xport3 */

#define PRPMC800_XPORT0_SIZE         0x02000000 
#define PRPMC800_XPORT1_SIZE         0x00700000 
#define PRPMC800_XPORT2_SIZE         0x00200000 
#define PRPMC800_XPORT3_SIZE         0x00080000