target.nr

vxworks的bsp开发包(基于POWERPC的PRPMC800)

must be defined in config.h:

.CS
1. #define INCLUDE_DEC_END

2. #define INCLUDE_SECONDARY_ENET
.CE

If the PrPMC800 is depopulated without an Intel 82559 chip, then to use
the PrPMCBASE-001 carrier board's DEC21143 as the primary Ethernet connection
with the device name of "dc0", the following changes must occur in config.h:

.CS
1. #define INCLUDE_DEC_END

2. #undef  INCLUDE_SECONDARY_ENET
.CE

IMPORTANT NOTE:
The DEC21143 will only work on the Monarch and not the Slave.

.SS "Configuring the PrPMC800 networking on the PrPMC Carrier 1"
If the Primary Ethernet device on the PrPMC Carrier 1 board is the PrPMC800
onboard i82559 device, then PCI_CARRIER_1_PRI_BUS in config.h must be set to
0 (default).  Otherwise, if the Primary Ethernet device is one of the two
PrPMC Carrier 1 onboard i82559 devices, the value must be set to 1.
To access all three i82559 devices (including the one on-board the PrPMC800),
change config.h to:

1. #define  INCLUDE_TERTIARY_ENET

.SS "Configuring the PrPMC800 networking on the PrPMC-G"
The Primary Ethernet on the PrPMC-G is the 82543 Gigabit Ethernet.
The 82543 Gigabit Ethernet driver does require that the whole of local dram 
be mapped onto the pci. You will need to set PCI2DRAM_MAP_SIZE to the size of 
the dram, it is set to 64MB as default for a PrPMC_G board.

The Secondary Ethernet on the PrPMC-G is the PrPMC800 on-board i82559 Ethernet.
The 82543 Gigabit Ethernet Driver does not use the value of PCI_IDSEL_PRI_LAN,
so if INCLUDE_SECONDARY_ENET is defined, there are no other changes required
to be made for the on-board i82559 to be used as the Secondary Ethernet.


.SS "Configuring the PrPMC800 to use its own ethernet on the MCPN765"
Under the current VxWorks software configuration, a PrPMC800 that
is placed on an MCPN765 does not have access to its own i82559
Ethernet chip.  The MCPN765 will auto configure the Ethernet chip,
but the PrPMC800 will not be able to use it.  To enable this access, 
the MCPN765 and PrPMC800 BSPs must be changed as follows:

.CS
In the MCPN765 config.h file:

1. Change the value of PCI_MSTR_MEMIO_SIZE so it is AT LEAST twice the size
   of the PrPMC800's DRAM_SIZE.  It also must be large enough to handle
   any additional PCI devices that are auto configured after the PrPMC800
   so it may need to be larger than twice the size of the PrPMC800's
   DRAM_SIZE.

2. Search for INTERRUPT_ROUTING_TABLE and change the device number 18
   line in the table from:

   { 0xff,                 /* device number 18 PMC 2B Connector */ \
     0xff,\
     0xff,\
     0xff },\

   to:

   { PCI_INTB_VEC,         /* device number 18 PMC 2B Connector */ \
     0xff,\
     0xff,\
     0xff },\

3. Search for INIT_EXT_SRC9 and change PRIORITY_LVL3 to PRIORITY_LVL0.

In the PrPMC800 config.h file:

1. Search for SLAVE_OWNS_ETHERNET and #define it.

2. Change PCI_MSTR_MEMIO_SIZE to make sure that
   (DRAM_SIZE + PCI_MSTR_MEMIO_SIZE) on the MCPN765 equals
   (PCI_MSTR_MEMIO_LOCAL + PCI_MSTR_MEMIO_SIZE) on the PrPMC800.
.CE

.TS C
center;
l l .
\f3NOTE:\f1	T{
The MCPN765's PMC Site 2 (top slot) has the Request/Grant and IDSEL
lines for access to the PrPMC800 onboard Ethernet chip.  However, 
these lines are not available on PMC Site 1 of the MCPN765 board, 
so the MCPN765 cannot auto configure the PrPMC800's Ethernet device.
Therefore, the PrPMC800's Ethernet chip cannot be used for any
communication when the PrPMC800 is installed on PMC Site 1.
T}
.TE
After these changes are made, the bootrom and kernel software must be
rebuilt and installed for both BSPs.

.SS "Configuring the PrPMC800 to use its own ethernet on a PrPMCBase with a PrPMC750 Monarch"

.CS
In the PrPMC750 config.h file:

1. Change the value of PCI_MSTR_MEMIO_SIZE so it is AT LEAST twice the size
   of the PrPMC800's DRAM_SIZE.  It also must be large enough to handle
   any additional PCI devices that are auto configured after the PrPMC800
   so it may need to be larger than twice the size of the PrPMC800's
   DRAM_SIZE.

2. Search for INTERRUPT_ROUTING_TABLE and change the device number 18
   line in the table from:

   { PCI_INTC_VEC, /* device number 18 PMC 1 Alt Device */ \
     0xff,\
     0xff,\
     0xff },\

   to:

   { PCI_INTB_VEC, /* device number 18 PMC 1 Alt Device */ \
     0xff,\
     0xff,\
     0xff },\

3. Search for INIT_EXT_SRC11 and change PRIORITY_LVL7 to PRIORITY_LVL0.

In the PrPMC800 config.h file:

1. Search for SLAVE_OWNS_ETHERNET and #define it.

2. Change PCI_MSTR_MEMIO_SIZE to make sure that
   (DRAM_SIZE + PCI_MSTR_MEMIO_SIZE) on the PrPMC750 equals
   (PCI_MSTR_MEMIO_LOCAL + PCI_MSTR_MEMIO_SIZE) on the PrPMC800.

.CE
After these changes are made, the bootrom and kernel software must be
rebuilt and installed for both BSPs.

.SS "Configuring the PrPMC800 to use its own ethernet on a PrPMCBase with a PrPMC800 Monarch"

.CS
In the PrPMC800 Monarch config.h file:

1. Search for SLAVE_OWNS_ETHERNET and #define it.

2. Change the value of PCI_MSTR_MEMIO_SIZE so it is AT LEAST twice the size
   of the PrPMC800 Slave's DRAM_SIZE.  It also must be large enough to handle
   any additional PCI devices on the PrPMCBase that are auto configured after
   the PrPMC800 Slave's Harrier, so it may need to be larger than twice the
   size of the PrPMC800's DRAM_SIZE.

In the PrPMC800 Slave config.h file:

1. Search for SLAVE_OWNS_ETHERNET and #define it.

2. Change PCI_MSTR_MEMIO_SIZE and PCI_MSTR_MEMIO_SIZE to have the
   same value on both Monarch and Slave.

.CE
After these changes are made, the bootrom and kernel software must be
rebuilt and installed for both BSPs.

.SS "PCI Access"
The 32-bit PCI bus is fully supported under the
.I PCI Local Bus Specification, Revision 2.1.
The 64-bit extensions are not supported.  All configuration space accesses
are made with BDF (bus number, device number, function number) format calls
in the pciConfigLib module.  For more information, refer to the man pages
.I prpmc800_xxpciXxx.


.SS "Using Customer-Designed Carrier Boards"
To use a customer-designed carrier board, the following changes must be made to
this BSP:

In config.h:
Modify the definition of INTERRUPT_ROUTING_TABLE to match the configuration
of your hardware. This table maps PCI IDSEL numbers to MPIC interrupt inputs.
The 4 columns in the table map INTA, INTB, INTC and INTD respectively as
viewed from the PrPMC site. The default table matches the MCG PrPMCBASE-001
Carrier board.

Modify the definitions of INIT_EXT_SRC0 through INIT_EXT_SRC15 to reflect
the desired MPIC interrupt priorities. To disable an interrupt, set it's
priority level to 0.

The values of PCI_MSTR_IO_SIZE, PCI_MSTR_MEMIO_SIZE and PCI_MSTR_MEM_SIZE may
also require modifications depending in the required PCI dynamic configuration
areas required.


.SS "Bootrom Errors"
Errors encountered during the early stages of the bootrom execution are saved
in the processor's general purpose registers as bit flags. Once the system is able to
report these errors, they are logged in the following form:

.CS
    Bootrom Error: Group = X, Code = 0xXXXXXXXX
.CE

The following errors are defined for this BSP:
.TS E
expand;
lf3 lf3 lf3
c l l .
.ne 4
.sp .5
Group	Bit Pattern	Meaning
_
A	0x80000000	Unable to read bus frequency from VPD.
A	0x40000000	Using default SDRAM Timing.
.TE

.TS C
center;
l l .
\f3NOTE:\f1	T{
When multiple errors are present simultaneously, the error bits are OR'd
together.
T}
.TE

.SS "Boot Devices"
The supported boot devices are:

    \f3sm\f1	- shared memory
    \f3er\f1	- Primary Ethernet (10baseT or 100baseTX)
    \f3dc1\f1	- Secondary Ethernet (10baseT or 100baseTX)


Motorola's PPC-Bug can be used to download and run VxWorks.
Consult the relevant user's manuals for details.

.SS "Boot Methods"
The boot methods are affected by the boot parameters.  If no password is
specified, RSH (remote shell) protocol is used.  If a password is specified,
FTP protocol is used, or, if the flag is set, TFTP protocol is used.

These protocols are used for both Ethernet and shared memory boot devices.

.SS "ROM Considerations"
Use the following command sequence on the host to re-make the BSP boot ROM:
.CS
    cd target/config/prpmc800
    make clean
    make bootrom_uncmp.bin
    cp bootrom_uncmp.bin /tftpboot/bootrom_uncmp.bin
.CE

Power down the board and switch the ROM jumper to select socketed FLASH.
Connect the Ethernet and console serial port cables, then power the board back
up.

.SS "Flashing the Boot ROM Using Motorola PPC-Bug:" 1
Using `niot', the Client IP Address, Server IP Address, and Gateway IP Address
must be set up for the user's specific environment:

.CS
   PPC-Bug>niot
   Controller LUN =00?
   Device LUN     =00?
   Node Control Memory Address =00FA0000?
   Client IP Address      =123.123.10.100? 123.321.12.123
   Server IP Address      =123.123.18.105? 123.321.21.100
   Subnet IP Address Mask =255.255.255.0?
   Broadcast IP Address   =255.255.255.255?
   Gateway IP Address     =123.123.10.254? 123.321.12.254
   Boot File Name ("NULL" for None)     =? .

   Update Non-Volatile RAM (Y/N)? y
   PPC-Bug>
.CE

The file is transferred from the TFTP host to the target board using
the `niop' command.  Important: You must have a TFTP server running on your
host's subnet for the `niop' command to succeed.  The file name must be set to
the location of the binary file on the TFTP host.  The binary file must be
stored in the directory identified for TFTP accesses, but the file name is
a relative path and does not include the \f3/tftpboot\f1 directory name:

.CS
   PPC-Bug>niop
   Controller LUN =00?
   Device LUN     =00?
   Get/Put        =G?
   File Name      =? boot.bin
   Memory Address =00004000?
   Length         =00000000?
   Byte Offset    =00000000?

   PPC-Bug>
.CE

After the file is loaded onto the target, the `pflash' command is used
to put it into Bank A (soldered FLASH) parts.

.CS
   PPC-Bug>pflash 4000:fff00 f0000100
.CE

When the command is finished, power down the board and switch the ROM
jumper to select Bank A (soldered FLASH).  Then power the board back up.

.SH "SPECIAL CONSIDERATIONS"
.SS "Delivered Objects"
The delivered objects are: `bootrom.hex', `vxWorks', `vxWorks.sym', and
`vxWorks.st'.

.SS "Make Targets"
The make targets are listed as the names of object-format files.  Append `.hex'
to each to derive a hex-format file name and append .bin for binary format.

 `bootrom'
 `bootrom_uncmp'
 `bootrom_res_high'  (`bootrom_res' does not build)
 `vxWorks' (with `vxWorks.sym')
 `vxWorks_rom'
 `vxWorks.st'
 `vxWorks.st_rom'
 `vxWorks.res_rom_res_low' (`vxWorks.res_rom' does not build)
 `vxWorks.res_rom_nosym_res_low' (`vxWorks.res_rom_nosym' does not build)

.SS "Special Routines"
The PrPMC800 does not contain an on-board oscillator for generating the 
processor bus clock. The processor bus clock is generated using a PLL which 
multiplies the system PCI bus frequency up to create the CPU bus frequency. 
The maximum PPC bus frequency (66 Mhz or 100 Mhz) is determined at module 
assembly time by populating the appropriate select resistors. The 100Mhz bus 
mode will be the standard configuration, but the 66Mhz bus mode may be 
available for low power configurations. The bus speed value (in Hertz) may be 
accessed using the macro MEMORY_BUS_SPEED which is defined in prpmc800.h.

.SS "TFFS support"
With TFFS included into your system, you will need to copy the cfiscs.c 
driver to the BSP from target/src/drv/tffs/. The file needs to be modified 
by defining BUFFER_WRITE_BROKEN. You must recompile the file 
eg make cfiscs.o. Then add this object to those pulled in via the Makefile 
using MACH_EXTRA.

.SH "BOARD LAYOUT"
The diagrams below show flash EEPROM locations and jumpers relevant to VxWorks
configuration:

For the PrPMC800EXT, the 10baseT/100baseTTX port appears through the front
panel opening reserved for PMC slot 1 when installed on the PrPMCBASE-001.

.ne 4i

.bS

              PrPMC800
____________________________________
|              P14          P12     |
|           =========== =========== |
|              P13          P11     |
|           =========== =========== |
|                PMC connectors     |
|                                   |
|                                   |
|                                   |
|                                   |
| +-----+