target.nr

vxworks的bsp开发包(基于POWERPC的PRPMC800)

card containing either a Monarch or Monarch and slave.
T}
2)	T{
MCP750 and PrPMCBASE card (Monarch only) with the Monarch containing
the anchor.  Note a slave is not allowed in this configuration.
T}
3)	T{
PrPMCBASE card with Monarch and Slave installed, Monarch contains
the anchor.  Note that a system-slot card such as the MCP750 is
required to be present but does not participate in shared memory.
T}
.TE

Below is a description of how each of the above systems would be
configured.  Crucial "config.h" and boot parameter settings for an
example system are given.  In each example, SYS_SM_ANCHOR_POLL_LIST
was defined to contain information identifying the Dec2155x bridge
chip (present on the PrPMCBASE board).  See "config.h" for the example of
how this was done.

.TS C
center;
l l .
1)	T{
Three nodes, MCP750 master (node 0, anchor), PrPMC Base with Monarch/Slave:
Note sequential addressing is turned off.
T}
.TE
.CS

   MCP750:

        #define SM_OFF_BOARD FALSE
        #undef  SYS_SM_SYSTEM_MEM_POLL
        #undef  INCLUDE_SM_SEQ_ADDR

        boot device          : dc
        processor number     : 0
        host name            : sunray
        inet on ethernet (e) : 144.191.16.191
        inet on backplane (b): 144.140.200.1:ffffff00
        host inet (h)        : 144.191.16.163
        gateway inet (g)     : 144.191.16.253
        target name (tn)     : gamma


   PrPMCBASE/PrPMC800-1 (Monarch):

        #define INCLUDE_DEC2155X
        #define SM_OFF_BOARD TRUE
        #define SYS_SM_SYSTEM_MEM_POLL
        #define SYS_BACKPLANE_BUS_NUMBER    1
	#define SYS_SM_BUS_NUMBER SYS_BACKPLANE_BUS_NUMBER
        #undef  INCLUDE_SM_SEQ_ADDR

        boot device          : sm
        processor number     : 1
        host name            : sunray
        inet on ethernet (e) : 144.191.16.192
        inet on backplane (b): 144.140.200.2:ffffff00
        host inet (h)        : 144.191.16.163
        gateway inet (g)     : 144.140.200.1
        target name (tn)     : alpha

   PrPMCBASE/PrPMC800-2 (Slave):

        (same "config.h" setup as Monarch)

        boot device          : sm
        processor number     : 2
        host name            : sunray
        inet on ethernet (e) : 144.191.16.193
        inet on backplane (b): 144.140.200.3:ffffff00
        host inet (h)        : 144.191.16.163
        gateway inet (g)     : 144.140.200.1
        target name (tn)     : beta
.CE

Note that multiple PrPMCBASE cards, each with a Monarch/Slave
pair could be added to this setup.  Each different prpmc800 would have
to configured with a different "processor number", 
"inet on ethernet", "inet on backplane", and "target name".

.TS C
center;
l l .
2)	T{
Two nodes, MCP750 (node 1), PrPMCBASE with Monarch (node 0, anchor):
T}
.TE
.CS

   MCP750:

        #define SM_OFF_BOARD TRUE
        #define SYS_BACKPLANE_BUS_NUMBER    1
        #undef SYS_SM_SYSTEM_MEM_POLL
        #undef INCLUDE_SM_SEQ_ADDR 

        boot device          : sm
        processor number     : 1
        host name            : sunray
        inet on ethernet (e) : 144.191.16.192
        inet on backplane (b): 144.140.200.2:ffffff00
        host inet (h)        : 144.191.16.163
        gateway inet (g)     : 144.140.200.1
        target name (tn)     : gamma

   PrPMCBASE/PrPMC800-1 (Monarch - slave not allowed):

        #define INCLUDE_DEC2155X
        #define SM_OFF_BOARD FALSE
        #define SYS_BACKPLANE_BUS_NUMBER    1
        #define SYS_SM_SYSTEM_MEM_POLL
	#define SYS_SM_BUS_NUMBER SYS_BACKPLANE_BUS_NUMBER
        #undef INCLUDE_SM_SEQ_ADDR

        boot device          : fei0
        processor number     : 0
        host name            : sunray
        inet on ethernet (e) : 144.191.16.191
        inet on backplane (b): 144.140.200.1:ffffff00 
	host inet (h)        : 144.191.16.163 
        gateway inet (g)     : 144.191.16.253
        target name (tn)     : alpha

.CE

.TS C
center;
l l .
3)	T{
Two nodes, PrPMC800-1 master (node 0, anchor), PrPMC800-2 slave
T}
.TE
.CS


   PrPMCBASE/PrPMC800-1 (Monarch):

        #define SM_OFF_BOARD FALSE
        #define SYS_BACKPLANE_BUS_NUMBER    1  (Not Used)
	#define SYS_LOCAL_PCI_BUS_NUMBER 0
	#define SYS_SM_BUS_NUMBER SYS_LOCAL_PCI_BUS_NUMBER
        #undef  SYS_SM_SYSTEM_MEM_POLL
        #undef  INCLUDE_SM_SEQ_ADDR

        boot device          : fei0
        processor number     : 0
        host name            : sunray
        inet on ethernet (e) : 144.191.16.192
        inet on backplane (b): 144.140.200.1:ffffff00
        host inet (h)        : 144.191.16.163
        gateway inet (g)     : 144.191.16.253
        target name (tn)     : alpha

   PrPMCBASE/PrPMC800-1 (Slave):

        #define INCLUDE_DEC2155X
        #define SM_OFF_BOARD TRUE
        #define SYS_BACKPLANE_BUS_NUMBER    1   (Not Uesd)
	#define SYS_LOCAL_PCI_BUS_NUMBER 0
	#define SYS_SM_BUS_NUMBER SYS_LOCAL_PCI_BUS_NUMBER
        #define SYS_SM_SYSTEM_MEM_POLL
        #undef  INCLUDE_SM_SEQ_ADDR

        boot device          : sm
        processor number     : 1
        host name            : sunray
        inet on ethernet (e) : 144.191.16.193
        inet on backplane (b): 144.140.200.2:ffffff00
        host inet (h)        : 144.191.16.163
        gateway inet (g)     : 144.140.200.1
        target name (tn)     : beta
.CE


.SS "Memory Maps"
On-board RAM for these boards always appears at address 0x00000000 locally.

Dynamic memory sizing is supported.  By default, LOCAL_MEM_AUTOSIZE is
defined so memory is auto-sized at hardware initialization time.
If auto-sizing is not selected, LOCAL_MEM_SIZE must be set to the actual size
of DRAM memory available on the board to ensure all memory is available.
The default fixed RAM size is set to 64MB (see LOCAL_MEM_SIZE in config.h).

Note that LOCAL_MEM_SIZE only controls the amount of memory mapped by the MMU.
It does not control the amount of memory detected and configured by the Bootrom.
The amount of physical memory indicated by the Serial Presence Detect data
determines the memory controller configuration and, if enabled, the ECC
initialization range. If hardware memory problem is suspected, the Bootrom can
be configured to ignore the Serial Presence Detect data and program the
memory controller with a set of default parameters. For more information on
this feature, see the BYPASS_SPD note in config.h.

.SS "Interrupts"
The system interrupt vector table has 256 entries.  Vectors for the various
devices on the buses are assigned hierarchically as follows:

.TS C
center;
lf3 lf3
l lw(2.6i) .
.ne 6
.sp .5
Vector#	Assigned to
_
00 - 0f	[User defined]
10 - 1f	All MPIC interrupts
20 - 23	system timers
24 - 27	system interprocessor dispatch
28	board detected internal errors
29 - 5f	[User defined]
60 - 72	Dec2155x interrupts
73 - ff	[User defined]
.TE

Vector numbers not in the table are not used by this BSP.

The Multi-Processor Interrupt Controller (MPIC) sets system interrupt
priorities and serves as controller of all external interrupts.  Each
of its 16 interrupt control registers, designated IRQ0 through IRQ15, can be
programmed with a relative priority from 15, the highest, to 0, the lowest.  A
priority of zero effectively disables the interrupt.  All but three of the 16
control registers has been hardwired to a particular interrupt source.  The IRQ
number and priority assignments are as follows:

.TS E
expand;
lf3 lf3 lf3
l l lw(2.6i) .
.ne 6
.sp .5
MPIC IRQ	Polarity	IRQ Source
_
IRQ0	High	Host INT 0 - Board Specific
IRQ1	N/A	Not used
IRQ2	Low	Board Specific interrupt (non-PCI)
IRQ3	Low	Watch Dog Timer 1 or 2
IRQ4	N/A	Not used 
IRQ5	N/A	Not used 
IRQ6	Low	HOSTINT1 
IRQ7	Low	HOSTINT2
IRQ8	Low	HOSTINT3
IRQ9	Low	PCI INTA
IRQ10	Low	PCI INTB or On-board Ethernet
IRQ11	Low	PCI INTC
IRQ12	Low	PCI INTD
IRQ13	N/A	Not used 
IRQ14	N/A	Not used 
IRQ15	N/A	Not used 
.TE

For further details, refer to the appropriate board's reference guide.

There are only four PCI bus interrupts: A, B, C, and D.  They are shared among
all PCI bus devices and do not have levels.  PCI bus interrupts are wired
directly to the MPIC and, therefore, have preassigned system vector numbers
and interrupt levels.

.SS "PCI Auto-Configuration"
To simplify the addition of PCI-based add-in cards, the BSP provides a PCI
auto-configuration library. When INCLUDE_AUTOCONF is defined (default), the BSP
will automatically locate and configure installed PCI devices. When
INCLUDE_AUTOCONF is not defined (intended for debug use only), add-in PCI
devices will not be located or configured.

When PCI auto-configuration is selected, the auto-configuration library will be
called from sysHwInit to discover and configure the installed PCI devices and
bridges. Device configuration includes the following PCI information:

.IP "Base Address Registers (BARs)"
Space in the address map is dynamically allocated to each valid BAR detected.
Allocation pools are maintained for the following PCI address spaces:

16-Bit PCI I/O

32-Bit PCI I/O

PCI Memory I/O (non-prefetchable memory)

PCI Memory (pre-fetchable)


.IP "Interrupt Routing"
The correct interrupt vector number is placed in the intLine register of the
device's PCI header. To connect to the device's interrupt, simply call
intConnect with the value read from intLine.

.IP "PCI Header Completion"
The PCI auto-configuration library fills in the remainder of the PCI header as
follows:

Cache Line Size = _CACHE_ALIGN_SIZE/4

Latency Timer = PCI_LAT_TIMER

Command Register = I/O enabled, Memory enabled and Bus Master enabled.

.IP "Transparent PCI-to-PCI Bridge Configuration"
Transparent PCI-to-PCI bridges encountered during PCI auto-configuration will
be configured as necessary and devices detected behind the bridge will be
configured as described above. Bridge configuration consists of the following:

Primary Bus Number, Secondary Bus Number and Subordinate Bus Number are
filled in according to the bridge's position in the system.

I/O Base and Limit registers are configured as required to forward PCI
transactions to PCI devices detected and configured beyond the bridge.

Memory Base and Memory Limit registers are configured as required to forward
PCI transactions to PCI devices detected and configured beyond the bridge.

Command Register = I/O enabled, Memory enabled and Bus Master enabled.

Cache Line Size = _CACHE_ALIGN_SIZE/4

Primary Latency Timer = PCI_LAT_TIMER

Secondary Latency Timer = PCI_LAT_TIMER

.SS "Serial Configuration"
The single debug port on the PrPMC800 board family is implemented in a
TLC16550 UART. The RJ-45 jack is placed on the front panel of the PrPMC Carrier
board and is configured as a DTE connection.

By default, the serial port is configured as asynchronous, 9600 baud, with
1 start bit, 8 data bits, 1 stop bit, no parity, and no hardware or software
handshake.  Hardware handshake using RTS/CTS is a supported option.

.SS "SCSI Configuration"
SCSI is not available on the PrPMC800 board family.

.SS "Harrier DMA Configuration"
To enable DMA support using the Harrier, change the #undef INCLUDE_HARRIER_DMA
in config.h to #define.  Instructions for configuring DMA Descriptor Lists are
contained in harrierDma.c and harrierDma.h.

.SS "Network Configuration"
The PrPMC800 has one Ethernet port which is 10baseT and 100baseTX
compatible using a RJ45 jack on the front panel for connection to this facility.

The Ethernet driver automatically senses and configures the port as 10baseT or
100baseTX.  For the PrPMC800 family, an Intel 82559 chip is used.  

The Media Access Control (Ethernet) address for each port is obtained from a
serial ROM connected to the Ethernet chip.  

The PrPMCBASE-001 has one Ethernet port which is 10baseT and 100baseTX
compatible using a RJ45 jack on the front panel for connection to this facility.

Support for the carrier boards DEC21143 exists in the BSP by defining
INCLUDE_DEC_END and INCLUDE_SECONDARY_ENET.

The Ethernet driver automatically senses and configures the port as 10baseT or
100baseTX.  The Ethernet driver is compatible with both DEC2104x and DEC2114x
devices.

The Media Access Control (Ethernet) address for each port is obtained from a
serial ROM connected to the DEC21143 chip.  

.SS "Configuring the PrPMC800 networking on the PrPMCBASE-001"
If the PrPMC800 is paired with the PrPMCBASE-001 carrier board, both
Ethernet devices will be auto-configured but the Ethernet driver will be
attached to the Ethernet device on the PrPMC800 ("fei0").  To use the
carrier board's DEC21143 as device name "dc1", then the following items