target.nr

vxworks的bsp开发包(基于POWERPC的PRPMC800)

.SS "Internal Dec2155x Interrupt Sources"
At start-up, all Dec2155x interrupt sources are masked and cleared.
Before unmasking an interrupt, an application ISR service routine must be
attached to the appropriate Dec2155x interrupt vector using intConnect().
Multiple ISR service routines can be connected to each vector if required
by the application. Once the handler is attached, the interrupt can be
enabled and disabled by calling sysDec2155xIntEnable() or
sysDec2155xIntDisable() as required. Interrupt vector definitions for the
Dec2155x internal interrupt sources are defined in prpmc800.h.

Unique interrupt vectors are provided for each of the 16 bits in the
Dec2155x Secondary IRQ register. Bit 0 (LSB) corresponds to
DEC2155X_DOORBELL0_INT_VEC with the remaining bits mapped in sequence.
These doorbell interrupts can be used for host-to-PrPMCBASE or
PrPMCBASE-to-PrPMCBASE event notification. The Dec2155x interrupt handler
clears these interrupts which simplifies the application ISR.

Individual interrupt vectors are also provided for Dec2155x Hot Swap
Power State and I2O in-bound list events. The Dec2155x interrupt handler
also clears these interrupts.

The 64 Upstream Memory 2 BAR Page Crossing interrupts are all presented
on a single interrupt vector and the application ISR is responsible for
clearing the bits serviced. Calls to sysDec2155xIntEnable() and
sysDec2155xIntDisable() enable or disable all 64 interrupts.

The Dec2155x interrupt handler provides a default service routine for all
unclaimed interrupt vectors, including the Upstream Memory 2 BAR Page
Crossing interrupt. The default routine reports the event and clears the
interrupt source.

.SS "Compact PCI Backpanel Interrupts"
The Dec2155x can generate cPCI backpanel interrupts using any of the bits
in the Primary IRQ register if they have been un-masked by the host. The
following code fragment generates a compact PCI backpanel interrupt by
setting bit 15 (MSB) of the Primary IRQ register:

.CS
    if (sysBusIntGen (DEC2155X_DOORBELL15_INT_LVL,
                      DEC2155X_DOORBELL15_INT_VEC) != OK)
        return (ERROR);
.CE

Note that the cPCI bus does not provide an interrupt vector to the host.
The vector number passed to sysBusIntGen() simply identifies which bit in
the register to set. It is the host's responsibility to locate the
interrupt source and clear the interrupt.

.SH "BSP CONFIGURATION"
Most BSP configuration values are taken from on-board Vital Product Data
(VPD) and Serial Presence Detect (SPD) serial EEPROMs. If invalid VPD or SPD
information is suspected or reported, defining NONFATAL_VPD_ERRORS, BYPASS_VPD
and/or BYPASS_SPD in config.h may permit operation using default parameters.
These build switches are intended for use during debug only as they hard-code
non-optimized SDRAM timing and other VPD information. Since the SDRAM timing is
configured by the Bootrom, changing the state of BYPASS_SPD requires rebuilding
the Bootrom image and re-flashing.

.SS "PCI Dynamic Allocation Spaces"
PCI_MSTR_IO_SIZE, PCI_MSTR_MEMIO_SIZE and PCI_MSTR_MEM_SIZE control
the sizes of the available PCI address spaces.  PCI_MSTR_MEMIO_LOCAL
(set to 1-Gigabyte (0x40000000) by default), controls the starting
local address of the PCI memory space.  The windows defined by these
parameters must be large enough to accommodate all of the PCI memory
and I/O space requests found during PCI autoconfiguration.  If they
are not, some devices will not be autoconfigured.  For all prpmc800s
on the same PCI bus, the value assigned to PCI_MSTR_MEMIO_LOCAL must
be greater than or equal to the value of the largest amount of DRAM
among these boards.  PCI_MSTR_MEMIO_LOCAL must also have the same
numeric value for all of the boards which appear on the same PCI bus.

.TS C
center;
l l .
\f3NOTE:\f1	T{
PCI auto-configuration is performed by the bootroms. Any changes to
PCI_MSTR_MEMIO_LOCAL, PCI_MSTR_IO_SIZE, PCI_MSTR_MEMIO_SIZE or 
PCI_MSTR_MEM_SIZE requires the creation of a new bootrom image.
T}
.TE

By default, the companion MCP750 BSP allocates a 32MB area aligned to a
32MB boundary for dynamic PCI configuration. To access peer PrPMC800 DRAM
areas, an upstream window must be opened which matches the size of the
host's dynamic PCI configuration area. For translation to work correctly,
the host's dynamic PCI configuration area must be aligned to a multiple
of the area's size and the corresponding Dec2155x upstream translation
register must contain the area's base cPCI address (not CPU address).
Since this BSP supports peer-to-peer access between PrPMC800 DRAM areas,
the default dynamic PCI configuration area for the PrPMC800 is 64MB aligned
to a 64MB boundary which satisfies these requirements.

In addition to the peer access window, sufficient space must also be
available for mapping the host DRAM upstream window and any space
required by PrPMCBASE-resident PCI devices. A margin must also be allowed
for areas that are unusable due to window alignment requirements.

If the application does not require peer-to-peer PrPMC800 DRAM access, the
large 32MB window used to contain the host's dynamic PCI configuration
area can be eliminated with a corresponding decrease in the required
PrPMC800 dynamic PCI configuration area. If peer-to-peer doorbell
interrupts are still required, the doorbell interrupt registers of peer
PrPMCBASE boards may be accessed through an I/O window which has much smaller
CPU address space requirements. This would require re-configuring the
default BSP to access host DRAM through Upstream Memory 1 BAR and using
the Upstream I/O or Memory 0 BAR to access the peer PrPMCBASE doorbell
interrupt registers.

.SS "Altering the Default Dec2155x Configuration:
Altering the Dec2155x configuration requires the careful consideration of
several items:

.IP
Dec2155x window sizes and alignment.
.IP
Dec2155x translation values.
.IP
The size and alignment of the host's dynamic PCI configuration area.
.IP
The size and alignment of the PrPMC800's dynamic PCI configuration area.
.LP

The Dec2155x window parameters are controlled by #defines in config.h.
There are three defines associated with each window:

.TS C
center;
rw11 lw(4.0i) .
\&..._SIZE	T{
determines the size of the window in bytes and must be an
integral power of two. The minimum size for a PCI I/O
space window is 64 bytes. The minimum size for a PCI
memory space window is 4KB. To disable a window, set the
size to 0. Note that the Dec2155x will not allow the
Primary CSR and Downstream Memory 0 BAR to be
disabled. If the size of this window is set to zero, the
Dec2155x will default to a 4KB window.
T}

\f3NOTE:\f1	T{
If a window value is not a power of 2, or is below the minimum size, sysLib.c
will not compile.
T}
.TE

.TS C
center;
rw11 lw(4.0i) .
\&..._TYPE	T{
determines the type of the window and any placement
restrictions. For proper operation, the window must be
configured for placement anywhere in the 32-bit PCI
address space.
T}
.TE

.TS C
center;
rw11 lw(4.0i) .
\&..._TRANS	T{
determines the base address of the window on the target
PCI bus. It is important to remember that this is a local
PCI address (downstream window) or a cPCI address
(upstream window). The translation value chosen must be
an even multiple if the window size.
T}

\f3NOTE:\f1	T{
If the translation value is not a multiple of the window
size, sysLib.c will not build.
T}
.TE

The default window sizes can be reduced without altering the sizes of the
dynamic PCI configuration area. However, if the required values are
significantly reduced from the default values, reducing the size of the
dynamic PCI configuration area reduces the size of the MMU page tables at
the ratio of 128:1 (a 128KB reduction saves 1KB of MMU table space).

.SS "Shared Memory Support"

The PrPMC800 BSP supports shared memory backplane communication with
the MCP750 or CPV5000 as the Compact PCI host node.  The Wind River
documentation provides a great deal of information regarding shared
memory concepts.  The section below provides tutorial style information
regarding the setup of a shared memory system involving the PrPMC800/PrPMCBASE
and either a MCP750 or a CPV5000.

.TS C
center;
l l .
\f3NOTE:\f1	T{
Wind River shared memory support is available for Monarch/Slave
configurations with the anchor and shared memory pool residing on the
Monarch.  Shared memory support is also available for
MCP750/Monarch/Slave configurations in which the Monarch and Slave are
configured together on a single carrier card.  Multiple carrier cards
with Monarch/Slave configurations are possible in the same shared
memory setup as long as the shared memory pool is configured on the
system-slot board (MCP750 or CPV5000).
T}
.TE

Setting up a working shared memory system involves proper setting of
certain "config.h" parameters and proper setting of boot parameters
via the "c" command from the boot prompt.  There are three components
involved in shared memory communication which must be configured
properly to create a working system:

.IP "Anchor:"
This is an area of memory which must be accessible to all nodes
participating in shared memory backplane communication.  The anchor
points to the actual shared memory buffer pool which must be located
in the same memory space as the anchor itself.  The associated
"config.h" parameter is SM_ANCHOR_ADRS.  In certain configurations,
nonzero nodes will "poll" for the location of the anchor.  "config.h"
#define's which come into play for polling are SM_OFF_BOARD,
SYS_SM_SYSTEM_MEM_POLL, and SYS_SM_BUS_NUMBER.

.IP "Master node:"
This node is always designated as node zero.  It is the node which
sets up the anchor and shared memory pool.  Once the anchor and shared
memory pool is set up, the master node acts as a peer with the other
nodes.  The node number (0 in this case) is one of the boot parameters
which can be set up with the "c" command from the bootline prompt.

.IP "Sequential addressing:"
This is governed by a "config.h" parameter, INCLUDE_SM_SEQ_ADDR and is
used when sequential IP addresses are assigned to the participating
nodes.  Node zero is assigned the lowest IP address, followed by nodes
1, 2 etc. which are assigned the subsequent and sequential IP addresses.
The advantage of sequential addressing is that fewer boot parameters
must be specified to configure the system.
.LP

The following restrictions apply to shared memory configurations.

.TS C
center;
l l .
1)	T{
Node zero must not boot over the shared memory interface.  Only
nonzero nodes are allowed to boot over the shared memory "sm"
interface.
T}
2)	T{
The location of the anchor must be statically determinable by the
master node (node 0).  That is, the location of the anchor must
either be a build-time static parameter or it must be able to
be communicated to the master node via the "sm=xxxxxxxx" boot
configuration parameter.  The nonzero nodes need not know the
location of the anchor at build or boot time but can be configured
to poll for the anchor dynamically.
T}
.TE

.TS C
center;
l l .
\f3NOTE:\f1	T{
Another piece of shared memory terminology is "host node".
The "host node" is the node which configures the compact PCI bus
during startup initialization.  In a system consisting of an MCP750
and one or more PrPMCBASE boards, the "host node" is the MCP750.  Don't
confuse "host node" with "master node".  "Master node" is simply a
synonym for "node 0".  The "host node" may or may not be the "master
node".  Note also that the "host node" need not necessarily be a VxWorks
node.
T}
.TE

Below are the crucial "config.h" parameters involved in shared memory:

.IP "CPCI_MSTR_MEM_BUS (address):"
The parameter is used to identify the address at which the
system-slot board's DRAM will be configured.  This is dependent 
on the host
board used and is defined in "config.h".  The explanation says
to set the value to 0x80000000 for a MCP750 host (default) or
0x00000000 for a CPV5000 host.

.IP "SM_OFF_BOARD (TRUE or FALSE):"
The parameter has a configurable value of either TRUE or FALSE
and directly determines the value of SM_ANCHOR_ADRS (the anchor
address).

If SM_OFF_BOARD is defined as FALSE, then the anchor is on-board
and SM_ANCHOR_ADRS is defined to be
LOCAL_MEM_LOCAL_ADRS + SM_ANCHOR_OFFSET.
LOCAL_MEM_LOCAL_ADRS is defined as 0x0 in "config.h" and
SM_ANCHOR_OFFSET is defined as 0x4100 in "config.h" to work with
an MCP750.  SM_ANCHOR_OFFSET needs to be changed to 0x1100 in
"config.h" to work with a CPV5000.

If defined as TRUE, then SM_ANCHOR_ADRS is defined as a function
call: sysSmAnchorAdrs() (defined in "sysLib.c").  This function
will dynamically poll, at system startup, various locations
(explained below) for the exact location of the shared memory
anchor.

Note that if "sm=xxxxxxxx" is used as a boot parameter, then
SM_OFF_BOARD has no effect.  The value of "xxxxxxxx" will be used
as the anchor location regardless of the setting of SM_OFF_BOARD.
If simply "sm" is used as a boot parameter, then SM_OFF_BOARD is
queried at initialization time to determine if polling is required
or not.

.IP "SYS_SM_BUS_NUMBER:"
This can be #define'd to be either SYS_LOCAL_PCI_BUS_NUMBER or
SYS_BACKPLANE_BUS_NUMBER.  If a system-slot board such as the MCP750 is
participating in shared memory, then SYS_SM_BUS_NUMBER must be #define'd to
be SYS_BACKPLANE_BUS_NUMBER.  This signifies the fact that the Monarch
and/or slave must generate traffic on the compactPCI bus in order for
the shared memory system to function properly.  If only a Monarch and
Slave are involved in the shared memory system then all of the
activity for shared memory is restricted to the local PCI bus.  In
that case SYS_SM_BUS_NUMBER should be #define'd as
SYS_LOCAL_PCI_BUS_NUMBER.

.IP "SYS_SM_SYSTEM_MEM_POLL (#define or #undef):"
This define only has an effect if anchor polling is called for
(because SM_OFF_BOARD is defined as TRUE and "sm" is used with no
"=xxxxxxxx").  In this case, simply defining SYS_SM_SYSTEM_MEM_POLL
will cause the node to poll for the anchor at compact PCI bus
address CPCI_MSTR_MEM_BUS + SM_ANCHOR_OFFSET (0x80004100).
"System memory" (which is the host node's DRAM) will
be included as one of the locations where the anchor might reside.
Note that other locations may be polled as well (explained later).

Not defining SYS_SM_SYSTEM_MEM_POLL will prevent the polling of
system  memory for the anchor.

.IP "SYS_SM_ANCHOR_POLL_LIST (#define or #undef):"
This define has an effect only if polling is called for (see
SM_OFF_BOARD explained above).  When defined,
SYS_SM_ANCHOR_POLL_LIST allows a list of devices, identified by
device/vendor ID and subsystem ID/subsystem vendor ID to be
specified as candidates for the anchor location.  Devices which
appear on the bus #define'd by SYS_SM_BUS_NUMBER (described
above) are found and if they
appear on the list defined by SYS_SM_ANCHOR_POLL_LIST, they are
checked to see if they contain the shared memory anchor.  The memory
accessed by the BAR at configuration offset "N" (where "N" is also defined in 
SYS_SM_ANCHOR_POLL_LIST) is queried.  The block of memory viewable
through this BAR is examined at address offset SM_ANCHOR_OFFSET (defined
in "config.h).
If SYS_SM_ANCHOR_POLL_LIST is not defined, ALL devices on the 
specified bus will be considered candidates for the anchor location and
will be polled.  If SYS_SM_ANCHOR_POLL_LIST defined but empty, NO
devices on bus will be considered candidates for
the anchor location.  In that case, the only location polled would
be system memory if SYS_SM_SYSTEM_MEM_POLL (see above) was defined.

.IP "INCLUDE_SM_SEQ_ADDR (#define or #undef)"
If "undef'ed", sequential addressing is disabled.  This symbol
is defined by default.
.LP

Consider a system consisting of an MCP750 (host node) and two PrPMCBASE
boards. The following three configurations are the only ones possible:

.TS C
center;
l l .
1)	T{
MPC750 (contains anchor) with one or more PrPMC Base cards, each