target.nr

vxworks的bsp开发包(基于POWERPC的PRPMC800)

normal operation.
T}
Miscellaneous	T{
ABORT switch (Extended PrPMC)
T}
.TE

.SS "Feature Interactions"
.IP "MPIC Spurious Interrupts"
A race condition can exist between PCI write posting and interrupt
processing which can cause an MPIC spurious interrupt.  The problem occurs
when a device's interrupt service routine writes to clear the interrupt
source and then returns to the interrupted code. When the PCI bus is very
busy, the write takes a while to get onto the bus and reach the
interrupting device. During this time, the device's interrupt will remain
asserted. If the PowerPC re-enables external interrupts before the PCI
write has reached the interrupting device, the processor will see the
interrupt still asserted and re-enter the MPIC interrupt routines.

When the MPIC handler reads the vector, the MPIC reports a spurious
interrupt because the PCI write has generally completed by then and the
device's interrupt has now been cleared.

.IP "Spurious Interrupt Workaround"
Modify the driver to perform a read from the PCI device (after writing to
the device to clear the interrupt) to ensure that
the write has fully propagated.  sysPciOutWordConfirm() will do this
automatically. Note that sysPciOutWordConfirm() reads from the address
written which may cause an undesirable side-effect depending on the design
of the hardware. If it does, just add a read from any safe location on the
device. The primary goal is force to the write out of the posting queues before
proceeding.

.SH "HARDWARE DETAILS"
This section details device drivers and board hardware elements.

.SS "Devices"
The device drivers and libraries included with this BSP are:

.TS C
center;
rw(1.0i) lw(3.7i) .
i8250Sio:	T{
Intel 8250 UART driver (serial port).
T}
AuxClk:	T{
Motorola timer driver for auxiliary clock.
T}
I2c:	T{
I2C support.
T}
Mpic:	T{
Motorola MPIC interrupt controller driver.
T}
Phb:	T{
Motorola PCI bus bridge driver.
T}
Smc:	T{
Motorola System Memory Controller.
T}
Dma:	T{
Motorola DMA Controller.
T}
fei82557End:	T{
10baseT/100baseTX Intel 82557/9 Ethernet driver.
T}
dec21x40End:	T{
10baseT/100baseTX DEC 21x4x Ethernet driver.
T}
gei82543End:	T{
10baseT/100baseTX/1000BaseT Intel 82543 Ethernet driver.
T}
dec2155xCpci:	T{
DEC 2155x Non-Transparent PCI-to-PCI Bridge support.
T}
pciAutoConfigLib:	T{
PCI autoconfiguration library.
T}
pciConfigLib:	T{
PCI configuration library.
T}
pciConfigShow:	T{
Show routines of PCI bus library.
T}
ppcDecTimer:	T{
PowerPC decrementer timer driver (system clock).
T}
SmcShow:	T{
System Memory Controller configuration Show routine.
T}
sysCache:	T{
MPC750/MPC7410 L2 1MB/2MB Cache support.
T}
sysMotVpd:	T{
Vital Product Data Support.
T}
sysMotVpdShow:	T{
Vital Product Data Show routines.
T}
sysMotVpdUtil:	T{
Vital Product Data Utility routines.
T}
.TE

.SS "Dec2155x PCI-to-PCI Non-Transparent Bridge Support"
This BSP contains support for the Dec2155x non-transparent PCI-to-PCI
bridge located on the PrPMCBASE-001 board. This device provides read/write
access to and from the Compact PCI bus (cPCI).

The following support is provided:
.IP
Up to 4 user configurable downstream cPCI to local PCI windows.
.IP
Up to 2 user configurable upstream local PCI to cPCI windows.
.IP
Support for in-bound "doorbell" interrupts.
.IP
Support for cPCI backpanel interrupts.
.IP
cPCI to local CPU address translation.
.IP
Local CPU to cPCI address translation.
.IP
Build-time validation of Dec2155x configuration parameters.

.SS "Dec2155x Support Limitations"
The PReP standard does not support 64-bit PCI addressing. Therefore, this
BSP does not provide support for 64-bit addressing through the Dec2155x.

There is a limitation when the cPCI to local PCI or cPCI to local CPU
address translation routines are presented with a cPCI address which maps
into a downstream window on the local board. The translation will succeed
and return an address, but when that address is accessed, the Dec2155x
will attempt to access one of its own downstream windows. The transfer
will fail because PCI devices cannot access themselves on the cPCI bus.
Depending on how error detection is configured, the result will be
invalid data or a PCI Master Abort.

Interrupt vectors are provided for the interrupts associated with
Dec2155x Hot Swap Power State transitions, Intelligent I/O (I2O), and the
Upstream Memory 2 Base Address Register but no other support for these
features is provided.

During system startup, the Dec2155x must be configured and unlocked
before the host enumerates the cPCI bus. To meet this timing requirement,
the Dec2155x is configured by the vxWorks boot ROM image. If changes to
the Dec2155x configuration are made, new boot ROMs are required in
addition to a new kernel. For proper operation, the Dec2155x
configuration in the Boot ROMs must match the configuration used by the
kernel.

The Dec2155x places certain limitations on window sizes and translation
values. This BSP adheres to those limitations and provides
build-time parameter checking to help avoid misconfigurations.
Modifications to the default Dec2155x configuration provided in this BSP
must be made with care to avoid invalid configurations. Information on
the default Dec2155x configuration provided by this BSP is presented in
the next section and modification guidelines appear later in this entry.

.SS "Dec2155x Default Configuration"
The default Dec2155x configuration supports a host processor (MCP750) and
up to 7 cPCI peripheral boards. The following interoperability is supported:

.IP
Host access to PrPMC800 CSR and the low 4MB of PrPMC800 DRAM.
.IP
PrPMC800 access to the low 4MB of host DRAM.
.IP
PrPMC800 access to peer cPCI boards.
.LP

The BSP provides these features using the following Dec2155x
configuration:

\f3Primary CSR and Downstream Memory 0 BAR:\f1
.TS C
center;
r lw(3.2i) .
Size:	T{
4MB
T}
Direction:	T{
In-Bound (cPCI to PrPMC800)
T}
cPCI Adrs:	T{
Dynamic (assigned by host)
T}
Local PCI Adrs:	T{
PCI_SLV_MEM_BUS (Dynamic - Harrier inbound translation base reg 0 value*)
T}
Local CPU Adrs:	T{
PCI_SLV_MEM_LOCAL (0x00000000 by convention)
T}
Use:	T{
R/W access to CSR (low 4KB) and PrPMC800 DRAM (above 4KB)
T}
.TE

* - Note that the Harrier inbound translation base register 0 value is
dynamically programmed at startup to map to low-order DRAM.  The
dynamically programmed value is dependent upon the value which is
dynamically programmed by the PCI autoconfiguration routine into the
Harrier's Inbound Translation Base Address Register 0.  The amount of
DRAM mapped through this inbound register set is dependent upon the
setting of PCI2DRAM_MAP_SIZE in "config.h".  The default amount is
16MB which is the minimum amount which can be mapped to allow the
fei (ethernet) driver to function.

\f3Upstream I/O or Memory 0 BAR:\f1
.TS C
center;
r lw(3.2i) .
Size:	T{
4MB
T}
Direction:	T{
Out-Bound (PrPMC800 to cPCI)
T}
cPCI Adrs:	T{
CPCI_MSTR_MEM_BUS (0x80000000 by convention)
T}
Local PCI Adrs:	T{
Dynamic (assigned by PrPMC800)
T}
Local CPU Adrs:	T{
Dynamic (based on local PCI adrs)
T}
Use:	T{
R/W access to host DRAM
T}
.TE


\f3Upstream Memory 1 BAR:\f1
.TS C
center;
r lw(3.2i) .
Size:	T{
32MB
T}
Direction:	T{
Out-Bound (PrPMC800 to cPCI)
T}
cPCI Adrs:	T{
Base cPCI address of the host's dynamic PCI configuration area (0x00000000 for
the default MCP750 BSP)
T}
Local PCI Adrs:	T{
Dynamic (assigned by PrPMC800)
T}
Local CPU Adrs:	T{
Dynamic (based on local PCI adrs)
T}
Use:	T{
R/W access to cPCI devices
T}
.TE

The remaining Dec2155x Base Address Registers are not used by the BSP and
are available for use by the application.

.SS "Dec2155x Address Translation:
Due to the dynamic nature of PCI address allocation, the locations of the
upstream Dec2155x windows move as devices are added to the PrPMC800 PCI
bus. Since these windows map the cPCI space into the local PrPMC800 PCI
and CPU address spaces, their positions determine where the cPCI
resources appear when viewed by the PrPMC800 CPU and any PCI devices resident
on the PrPMC carrier board. Likewise, the downstream windows move as cPCI
devices are added and removed. The downstream windows are used to map the
on-board PCI and DRAM resources into the cPCI address space for access by the
host and other cPCI devices.

To assist with address translation, two translation routines are
provided by this BSP:

.TS C
center;
rw20 lw(3.2i) .
sysLocalToBusAdrs()	T{
Translates a local CPU address to an equivalent cPCI or local PCI memory or
I/O address.
T}

sysBusToLocalAdrs()	T{
Translates a cPCI or local PCI memory or I/O space address to a local CPU
equivalent address.
T}
.TE

.TS C
center;
l l .
\f3NOTE:\f1	T{
The translations performed by sysLocalToBusAdrs() and
sysBusToLocalAdrs() are not symmetrical if one of the endpoints is the Compact
PCI bus. sysLocalToBusAdrs() translates by locating a downstream window which
makes the local CPU address visible in the cPCI address space.
sysBusToLocalAdrs() performs a similar operation by locating an upstream window
which makes the cPCI address visible in the local CPU address space. Since the
two sets of windows map different areas of the local address space,
the translation is not reversible.
T}
.TE

.SS "Accessing Dec2155x CSR Registers"
Due to dynamic PCI address allocation, the PCI address assigned to the
Dec2155x CSR area cannot be known until runtime. To determine the
assigned address, it is necessary to read the Secondary CSR memory
BAR (or the Secondary CSR I/O BAR if I/O space is to be used).

The following code fragment derives the CPU address of the Scratchpad 0
register using its PCI memory space address:

.CS
    UINT32 bar;

    /* get the contents of the secondary CSR memory BAR
       (see note below) */

    if (pciConfigInLong (0, DEC2155X_PCI_DEV_NUMBER, 0,
                         DEC2155X_CFG_SEC_CSR_MEM_BAR,
                         &bar) != OK)
        {
        return (ERROR);
        }

    /* calculate the local PCI address of the scratchpad 0
       register */

    bar += DEC2155X_CSR_SCRATCHPAD0;

    /* convert the result to the CPU equivalent address */

    if (sysBusToLocalAdrs (PCI_SPACE_MEM_PRI, (char *)bar,
                         (char **)&bar) != OK)
        {
        return (ERROR);
        }

    return (bar);
.CE

.TS C
center;
l l .
\f3NOTE:\f1	T{
Using the constant DEC2155X_PCI_DEV_NUMBER ensures that the
on-board Dec2155x is read. If a search of the local PCI bus had
been performed using the Dec2155x device ID, the returned Bus,
Device and Function numbers may have corresponded to a Dec2155x
part found on an installed PMC card.
T}
.TE

Once the local CPU address is known, the cPCI address can be derived by
adding the following code fragment before returning the result:

.CS
    if (sysLocalToBusAdrs (PCI_SPACE_MEM_SEC,
                           (char *)bar,
                           (char **)&bar) != OK)
        return (ERROR);
    else
        return (bar);
.CE