target.nr

vxworks的bsp开发包(基于POWERPC的PRPMC800)

'\" t
.so wrs.an
.\" PrPMC800/target.nr - Motorola PrPMC target-specific documentation
.\"
.\" Copyright 2002 Wind River Systems, Inc.
.\" Copyright 1999-2001 Motorola, Inc. All Rights Reserved
.\"
.\" modification history
.\" --------------------
.\" 01t,19jul02,dtr  Changing Shared Memory config description.
.\" 01s,29mar02,dtr  Adding comments for TFFS with strataflash.
.\" 01r,21mar02,kab  remove ref to elfToBin (obs in T2.2); 
.\"		     add supported target list.
.\" 01q,16nov01,dtr  Small changes for dec21143,gei mods. TFFS support added.
.\" 01p,16nov01,scb  Minor mods to cover last minute T2.1 updates.
.\" 01o,10oct01,scb  Added info regarding new mappings and shared memory.
.\" 01n,18sep01,srr  Replaced i82559 driver references with FEI driver.
.\"                  Updated Bank A & B FLASH references.
.\" 01m,10aug01,srr  Added instructions PrPMC-G and Carrier 1 boards.
.\" 01l,21jun01,srr  Added instructions for enabling Harrier DMA driver.
.\" 01k,14jun01,srr  Updated Monarch prpmc800 instructions for slave's Ethernet
.\"                  to increase the size of PCI_MSTR_MEMIO_SIZE.
.\" 01j,08jun01,srr  Updated instructions for prpmc800 slave using Ethernet.
.\" 01i,14may01,blk  Added instructions for prpmc800 slave on mcpn765
.\" 01h,09may01,bvc  Removed Known Limitations entire empty section
.\" 01g,08may01,bvc  Removed Known Limitations on shared memory
.\" 01f,15jan01,krp  Added section on Known Limitations
.\" 01e,10jan01,krp  Added TFFS in the unsupported featues section
.\" 01e,09jan01,krp  Corrected minor spelling errors in the file.
.\" 01d,08jan01,krp  Changed the board series part number description.     
.\" 01c,05jan01,krp  Added note no WRS SM supported in slave device.
.\" 01b,20dec00,krp  Added tab characters for format tables correctly.
.\" 01a,20nov00,krp  Written (from version 01g of prpmc750/target.nr).
.\"
.\"
.TH "PrPMC800" T "Motorola PrPMC800/PrPMC800EXT" "Rev: 10 August 01" "VXWORKS REFERENCE MANUAL"

.SH "NAME"
.aX "Motorola PrPMC800/PrPMC800EXT"

.SH "INTRODUCTION"
This manual entry provides board-specific information necessary to run
VxWorks.  Before using a board with VxWorks, verify that the board runs in the
factory configuration by using vendor-supplied ROMs and jumper settings and
checking the RS-232 connection.

This BSP encompasses the PrPMC800 and PrPMC800EXT Processor PMC single-board
computers and the MCG Compact PCI PrPMC Carrier board (PrPMCBASE-001).
The PrPMC800 is a processor PMC module based on the PowerPlus III architecture.
It consists of the MPC75x or MPC7410 processor and L2 backside cache, the 
Harrier System Controller/PCI Host Bridge ASIC, up to 32MB to 256MB of 
ECC-protected SDRAM, a 10 BaseT/100 Base TX ethernet channel and an RS232 
serial debug port.

The PrPMC800/PrPMC800EXT series part numbers are of the form:

    PrPMC800-wxyz

    where
        w = CPU Type
           1 = MPC7410 with Ethernet
           2 = MPC7410 without Ethernet (66MHz PCI)
           5 = MPC750 with Ethernet
           6 = MPC750 without Ethernet (66MHz PCI)

        x = CPU Speed
           2 = 450MHz  

        y = ECC SDRAM size
           4 =	64 MB
           5 =	128 MB
           6 =	256 MB
           7 =	512 MB

        z = Ethernet Configuration (if present)
           1 =	Ethernet out front of PrPMC
           9 =	Ethernet out the PCI connector of the PrPMC

For example, an PrPMC800-5251 denotes a 450 MHz PowerPC 750-based board having
128MB of ECC SDRAM in the standard PMC form factor with Ethernet out the front.
Note that not all product combinations are available. Standard equipment
includes 8MB FLASH (9MB on the extended PMC form factor).

The BAT registers are not supported in the current cache management strategy.

.SS "OPERATING MODES"
The PrPMC800 BSP operates in PCI Host mode (installed in PMC site 2 of the
PrPMC carrier) and limited slave mode (installed in PMC site 1 of the
PrPMC carrier).  In limited slave mode, the BSP will come up to a bootrom
prompt.  By default, the slave PrPMC800 does not use its on-board Ethernet
device.  PCI inbound and outbound translation register are programmed
so that the slave can see the Monarch's DRAM and the Monarch PrPMC800 can
see the slave's DRAM.  There is currently no inter Monarch to slave
communication.

In PCI Host mode, the BSP performs PCI auto-configuration at
startup. If a Dec/Intel 21143 is present on Bus 0, the ethernet drivers will be
attached to the device and full ethernet I/O and network boot capabilities will
be available. If multiple 21143 devices are present, the ethernet driver will be
attached to the device with the lowest IDSEL.

The Monarch can control the slave's Ethernet device by defining  
INCLUDE_SECONDARY_ENET and defining PCI_IDSEL_SEC_LAN to 18.

The slave PrPMC800 can control its own on-board Ethernet device by
defining SLAVE_OWNS_ETHERNET in config.h.

.SS "CAUTIONS and WARNINGS"
.IP "\f3Preparing the PrPMCBASE-001 for VxWorks\f1"
In previous non-system cPCI boards, the 21554 non-transparent PCI-to-PCI bridge
was configured for software initialization. To address a start-up timing issue
under PPC-Bug, the 21554 is configured for self-initialization as delivered
from the factory. Before using the PrPMCBASE-001 with the default VxWorks
configuration, the 21554 must be configured for software initialization.

The 21554 initialization mode is controlled by bit 2 (LSB=0) of offset 0x31 in
an I2C SROM attached to the 21554. The state of this bit can be altered from
the BUG command line using the I2C SROM byte editor as follows:

.CS
   PPC-Bug>srom;d

   Device Address =$0000A000 (N/Y)? y
   Reading SROM into Local Buffer.....
   $00 (&000) 80? <return>
   $01 (&001) 00? <return>
   .
   . Continue to press <return> until byte 0x31 is reached.
   .
   $31 (&049) 00? 04 (or 00 for BUG mode)
   $32 (&050) 00? .
   Update SROM (Y/N)? y
   Writing SROM from Local Buffer.....
   Verifying SROM with Local Buffer...
.CE
 
The following symptoms are the result of attempted operation with the wrong
21554 initialization mode:
 
.TS C
center;
l l
l l .
Env	Symptom
-
BUG	T{
Everything appears normal, but a "ver" command from the cPCI Host (MCP750,
CPV500, etc.) does not report the presence of a PrPMCBASE-001.
T}
VxWorks	T{
The mis-configured PrPMCBASE-001 can consume all available PCI allocation space
and prevent the proper configuration of other boards in the cPCI chassis. If in
doubt, re-build the PCI Host BSP with INCLUDE_SHOW_ROUTINES defined and display
the PCI header of the 21554 on the PrPMCBASE-001 using the pciHeaderShow command
at the debug console of the PCI Host. If BAR2 and/or BAR3 are non-zero using
the pre-built PrPMC BSP binary image, the PrPMCBASE-001 is mis-configured.
T}
.TE

.IP "Save a Copy of PPC-Bug"
The FLASH ROMs installed in the Bank B sockets of the PrPMCBASE-001 and
PrPMC800EXT may not contain a BUG image. Before installing a VxWorks bootrom
image in FLASH ROM Bank A, verify that an operational copy of PPC-Bug is
present in Bank B of the PrPMCBASE-001 or the PrPMC800EXT. If necessary, copy
the BUG image from Bank A to Bank B by entering the following line at the BUG
prompt:

.CS
   PPC-Bug>pflash f0000000:100000 ff800000
.CE

Do not overwrite Bank A until the BUG image in Bank B is known to be
operational. Failure to preserve an operational copy of the BUG can render the
board inoperable until a replacement FLASH set can be obtained from the factory.

.IP "Hardware Environment"
This BSP was developed using a MCG PrPMC Compact PCI Carrier (PrPMCBASE-001) as
the base board and a PrPMC800EXT/PrPMC800 installed in PMC site 2. These
instructions assume that a PrPMC Carrier/PrPMC800 or PrPMC Carrier/PrPMC800EXT
combination are in use. Instructions for modifying the BSP for use with a
customer-designed carrier board are contained later in this entry.

The PrPMC800 BSP also supports the MCG PrPMC Carrier 1 board (5 PMC sites)
and the MCG PrPMC-G board with 82543 Gigabit Ethernet support.  To select
between the three of these boards, the value in config.h for CARRIER_TYPE
must be set to PRPMC_BASE (default), PRPMC_CARRIER_1, or PRPMC_G. CARRIER_TYPE
is not available in the Tornado project facility.

IMPORTANT NOTE :
The PRPMC_CARRIER_1 board does not have dec21554 bridge so INCLUDE_DEC2155X 
must be undefined in the BSP. JP4 must be set to 1-2 on PRPMC_CARRIER_1 
board(default). 

.IP "Bank B (Socketed FLASH)) Voltage"
The PrPMCBASE-001 and the PrPMC800EXT use Am29LV040 3.3-volt (only) socketed
FLASH parts. These parts are not 5-volt tolerant. The MVME2400 also uses these
3.3-volt parts as socketed FLASH and its sockets may be used to program FLASH
parts if a dedicated programmer is not available.

.IP "Debug Consoles"
The PrPMCBASE routes the serial outputs from the PMC sites as follows:
.TS C
center;
lf3 lf3
l l .
PMC Site	Serial Port Connection
-
1 (non-Monarch)	Front Panel COM1
2 (Monarch)	Front Panel COM2
.TE

Therefore, access to the debug console of the Monarch PrPMC (installed at PMC
site 2) requires a DTE cable connected to COM2 (not COM1). Likewise, access to
the debug console of the non-Monarch PrPMC requires a DTE cable connected to
COM1.

.IP "Compact PCI Backpanel Clocks"
The PrPMCBASE requires the presence of valid clocks on the Compact PCI backpanel
which are driven by the system processor board (MCP750, CPV5000, etc.). Proper
operation of the PrPMCBASE therefore requires that a system processor be
installed in the Compact PCI chassis's system slot (right-most slot as viewed
from the front of the chassis).

.IP "Processor Address and Data Bus Parity"
This BSP supports parity protection of the processor's address bus and data bus.
This option is enabled by default. If parity protection is not desired, undefine
INCLUDE_BPE in config.h, rebuild both the bootrom and kernel images and re-flash
the bootroms.

.IP "Memory ECC Protection"
This BSP supports ECC memory and configures the memory controller for ECC
operation by default. If ECC protection is not desired, undefine INCLUDE_ECC in
config.h, rebuild both the bootrom and kernel images and re-flash the bootroms.

.SS "Boot ROMS"
.IP "PrPMC800"
The PrPMC800 supports two banks of FLASH memory. Bank A (8-32 MBytes) is onboard
FLASH while Bank B is optional FLASH on the host board and accessed through the
PMC connector. FLASH bank B selection is controlled by a jumper on the
PrPMC800EXT when the PrPMC800EXT is installed on a customer-designed carrier.

.TS C
center;
l l .
\f3NOTE:\f1	T{
When the PrPMC800EXT is used with the PrPMCBASE-001 Compact PCI PMC carrier
board, either the PrPMC800EXT's Bank B (socketed FLASH) parts and boot ROM
selection jumper or the Carrier board's Bank B (socketed FLASH) parts and boot
ROM selection jumper must be depopulated to avoid bus contention issues.
T}
.TE

.IP "PrPMCBASE-001"
The Compact PCI PrPMC Carrier board has one 1MB bank of socketed FLASH composed
of two AMD Am29LV040 FLASH parts (Bank B). A boot FLASH selection jumper is
present on the PrPMC Carrier board which selects between FLASH bank A (soldered
onto the PrPMC800/PrPMC800EXT) or FLASH bank B (socketed) on the Carrier board.

.IP "Boot Line Parameters"
A limited non-volatile storage capability is implemented using a 256-byte
Serial EEPROM (SROM). The entire SROM contents are reserved for storage of the
VxWork boot line.

To load VxWorks, and for more information, follow the instructions in the
\f2Tornado User's Guide: Getting Started.\f1

.SS "Jumpers"
The following jumpers are relevant to VxWorks configuration:

.TS E
expand;
lf3 lf3 lf3 lf3
l l l lw(2.6i) .
.sp .5
Board	Jumper	Function	Description
_
PrPMC800	N/A	N/A	T{
No jumpers on PrPMC800.
T}
PrPMC800EXT	J3	ROM controller	T{
Install the jumper across pins 2 and 3 to select Bank A (socketed FLASH).
Install the jumper across pins 1 and 2 to select Bank B (soldered FLASH)
[factory configuration].
T}
PrPMCBASE-001	J29	ROM controller	T{
Install the jumper across pins 2 and 3 to select Bank A (socketed FLASH).
Install the jumper across pins 1 and 2 to select Bank B (soldered FLASH)
[factory configuration].
T}
.TE

.TS C
center;
l l .
\f3NOTE:\f1	T{
When the PrPMC800EXT is used with the PrPMCBASE-001 Compact PCI PMC carrier
board, either the PrPMC800EXT's socketed Bank B FLASH parts and boot ROM
selection jumper or the Carrier board's socketed Bank B FLASH parts and boot
ROM selection jumper must be depopulated to avoid bus contention issues.
T}
.TE

For jumper configuration details, see the board diagrams at the end of
this entry and in the hardware manual.

.SH "FEATURES"
The following subsections list all supported and unsupported features, as well
as any feature interaction.

.SS "Supported Features"
The following features of the PrPMC800 board family are supported:

.TS E
expand;
lf3 lf3
lw13 lw(3.7i) .
.ne 7
.sp .5
Feature Description
_
Processors	T{
MPC750-450Mhz
MPC7410-450Mhz
Up to 100MHz bus clock (derived from PCI bus clock)
T}
FLASH	T{
8MB-32MB Flash BANK A (16-bit)
Optional on the base board upto 512MB Flash BANK B (16-bit).
T}
DRAM	T{
32 to 256MB ECC SDRAM; auto-sized or fixed
T}
Peripherals	T{
one async serial debug port,
10baseT/100baseTX Ethernet interface (Extended PrPMC and PrPMCBASE-001 only)
T}
PCI Interface	T{
32-bit address, 32-bit data; complies with \f2PCI Local Bus Specification\f1,
Revision 2.1
T}
TFFS	T{
True File Flash System for the Intel StrataFlash memory is supported.
T}
Miscellaneous	T{
RESET switch (Extended PrPMC)
Harrier DMA Controller supported
T}
.TE

.SS "Unsupported Features"
The following features of the PrPMC800 board family are not supported:

.TS E
expand;
lf3 lf3
lw13 lw(3.7i) .
.ne 6
.sp .5
Feature	Description
_
System	T{
Watchdog Timers
T}
PCI Interface	T{
64-bit data; The hardware will perform 64-bit transfers if requested by an
external PCI-master device, but does not generate 64-bit transactions in