prpmc800.h

vxworks的bsp开发包(基于POWERPC的PRPMC800)

/* non-volatile (battery-backed) ram defines
 *
 * the top 16 bytes are used for the RTC registers
 */
 
#define BBRAM_ADRS              PRPMC800_XPORT3_ADDR   /* base address */
#define BBRAM_SIZE              0x8000         /* 32K NVRAM Total Size */
 
/* factory ethernet address */
 
#define BB_ENET                 ((char *)(BBRAM_ADRS + 0x7f2c))
 
/* MK48TXX register settings */
 
/* flag register */
 
#define MK48T_FLAGS             ((char *)(BBRAM_ADRS + 0x7ff0))
 
/* alarm clock registers, 4 1byte locations */
 
#define ALARM_CLOCK             ((char *)(BBRAM_ADRS + 0x7ff2))
 
/* interrupt register */
 
#define MK48T_INTR              ((char *)(BBRAM_ADRS + 0x7ff6))
 
/* watchdog timer register */
 
#define WD_TIMER                ((char *)(BBRAM_ADRS + 0x7ff7))
 
/* MK48TXX bb time of day clk, 8 1byte locations */
 
#define TOD_CLOCK               ((char *)(BBRAM_ADRS + 0x7ff8))
 
/* User configuration SROM */

#define USR_SROM_ADRS	USR_BRD_EEPROM_ADRS
#define USR_SROM_SIZE   256

#define NV_RAM_READ(x)		sysNvRead (x)
#define NV_RAM_WRITE(x,y)	sysNvWrite (x,y)

/* Slave-Mode PRPMC750 related defines */

/*
 * The following define causes the IntPin value presented in the emulated PCI
 * to track the PCI Bus interrupt routing established by the value of
 * PRPMC_SLAVE_BUS_INT_ROUTE in config.h
 */

#define PRPMC_SLAVE_BUS_INT_PIN          (PRPMC_SLAVE_BUS_INT_ROUTE+1)

/*
 * The following define causes the trigger offset to track the value of
 * SM_BUS_INT_LVL. So if SM_BUS_INT_LVL is set to IPI3_INT_LVL, the resulting
 * value of SM_BUS_INT_TRIGGER_OFFSET will be MPIC_CPU1_IPI3_DISP_REG (0x21070).
 */

#define SM_BUS_INT_TRIGGER_OFFSET   (MPIC_CPU1_IPI0_DISP_REG +\
                                     ((SM_BUS_INT_LVL - IPI0_INT_LVL) *\
                          (MPIC_CPU1_IPI1_DISP_REG -\
                                       MPIC_CPU1_IPI0_DISP_REG)))

#define SM_BUS_INT_BIT         1
#define SM_BUS_INT_PRIORITY    PRIORITY_LVL7

/*
 * The following define causes the trigger offset to track the value of
 * SM_MAILBOX_INT_LVL. So if SM_MAILBOX_INT_LVL is set to IPI0_INT_LVL, the
 * resulting value of SM_MAILBOX_INT_OFFSET will be MPIC_CPU0_IPI0_DISP_REG
 * (0x20070).
 */

#define SM_MAILBOX_INT_OFFSET   (MPIC_CPU0_IPI0_DISP_REG +\
                                 ((SM_MAILBOX_INT_LVL - IPI0_INT_LVL) *\
                                  (MPIC_CPU0_IPI1_DISP_REG -\
                                   MPIC_CPU0_IPI0_DISP_REG)))
#define SM_MAILBOX_INT_BIT  0
#define SM_MAILBOX_INT_VEC 	HARR_FUNC_INT_LVL

/* Dec2155x (Drawbridge) related defines */

#define DEC2155X_MAILBOX_INT_VEC (DEC2155X_DOORBELL0_INT_VEC + \
				  DEC2155X_SM_DOORBELL_BIT)

#ifdef INCLUDE_DEC2155X
#   define DEC2155X_BIST_VAL         0x00
#   define DEC2155X_PRI_PRG_IF_VAL   0x00
#   define DEC2155X_PRI_SUBCLASS_VAL 0x20
#   define DEC2155X_PRI_CLASS_VAL    0x0b
#   define DEC2155X_SEC_PRG_IF_VAL   0x00
#   define DEC2155X_SEC_SUBCLASS_VAL 0x80
#   define DEC2155X_SEC_CLASS_VAL    0x06
#   define DEC2155X_MAX_LAT_VAL      0x00
#   define DEC2155X_MIN_GNT_VAL      0xff

#   define DEC2155X_CHP_CTRL0_VAL 0x0000
#   define DEC2155X_CHP_CTRL1_VAL 0x0000

#   define DEC2155X_PRI_SERR_VAL (DEC2155X_SERR_DIS_DLYD_TRNS_MSTR_ABRT | \
			          DEC2155X_SERR_DIS_DLYD_RD_TRNS_TO     | \
			          DEC2155X_SERR_DIS_DLYD_WRT_TRNS_DISC  | \
			          DEC2155X_SERR_DIS_PSTD_WRT_DATA_DISC  | \
			          DEC2155X_SERR_DIS_PSTD_WRT_TRGT_ABRT  | \
			          DEC2155X_SERR_DIS_PSTD_WRT_MSTR_ABRT  | \
			          DEC2155X_SERR_DIS_PSTD_WRT_PAR_ERROR)

#   define DEC2155X_SEC_SERR_VAL (DEC2155X_SERR_DIS_DLYD_TRNS_MSTR_ABRT | \
			          DEC2155X_SERR_DIS_DLYD_RD_TRNS_TO     | \
			          DEC2155X_SERR_DIS_DLYD_WRT_TRNS_DISC  | \
			          DEC2155X_SERR_DIS_PSTD_WRT_DATA_DISC  | \
			          DEC2155X_SERR_DIS_PSTD_WRT_TRGT_ABRT  | \
			          DEC2155X_SERR_DIS_PSTD_WRT_MSTR_ABRT  | \
			          DEC2155X_SERR_DIS_PSTD_WRT_PAR_ERROR)
#endif /* INCLUDE_DEC2155X */

/* Interrupt bases  */

#define ISA_INTERRUPT_BASE       0x00
#define EXT_INTERRUPT_BASE       0x10
#define TIMER_INTERRUPT_BASE     0x20
#define IPI_INTERRUPT_BASE       0x24
#define INTERNAL_INTERRUPT_BASE  0x28
#define	ESCC_INTERRUPT_BASE      0x00

#define DEC2155X_INTERRUPT_BASE 0x60

/* interrupt Level definitions */

#define PIB_INT_LVL         ( 0x00 + EXT_INTERRUPT_BASE )

    /* UART interrupt level is shared by the 2 COM Ports */

#define XPORT_UART_INT_LVL  ( 0x01 + EXT_INTERRUPT_BASE )

    /* Front panel Ethernet interrupt level */

#define LN1_INT_LVL         ( 0x0a + EXT_INTERRUPT_BASE )

    /* P14 carrier board Ethernet interrupt level */

#define LN2_INT_LVL         ( 0x0c + EXT_INTERRUPT_BASE )

    /* Slave Ethernet interrupt level */

#define SLV_LN1_INT_LVL     ( 0x0b + EXT_INTERRUPT_BASE )

    /* Watchdog Timer Level 1 interrupt level */

#define WDTL1_INT_LVL       ( 0x03 + EXT_INTERRUPT_BASE )

    /* Watchdog Timer Level 2 interrupt level */

#define WDTL2_INT_LVL       ( 0x03 + EXT_INTERRUPT_BASE )

    /* Drawbridge interrupt level */

#define DEC2155X_INT_LVL    ( 0x09 + EXT_INTERRUPT_BASE )

    /* Abort interrupt level */

#define ABORT_INT_LVL       ( 0x0e + EXT_INTERRUPT_BASE )

    /* PCI INTA# */

#define PCI_INT_LVL1        ( 0x09 + EXT_INTERRUPT_BASE )

    /* PCI INTB# */

#define PCI_INT_LVL2        ( 0x0a + EXT_INTERRUPT_BASE )

    /* PCI INTC# */

#define PCI_INT_LVL3        ( 0x0b + EXT_INTERRUPT_BASE )

    /* PCI INTD# */

#define PCI_INT_LVL4        ( 0x0c + EXT_INTERRUPT_BASE )

    /* Timer interrupt level (IPI0) */

#define TIMER0_INT_LVL      ( 0x00 + TIMER_INTERRUPT_BASE )

/* Inter-Processor Interrupts */

#define IPI0_INT_LVL        ( 0x00 + IPI_INTERRUPT_BASE )
#define IPI1_INT_LVL        ( 0x01 + IPI_INTERRUPT_BASE )
#define IPI2_INT_LVL        ( 0x02 + IPI_INTERRUPT_BASE )
#define IPI3_INT_LVL        ( 0x03 + IPI_INTERRUPT_BASE )

/* Harrier Internal Functional Interrupts  */

#define HARR_FUNC_INT_LVL   ( 0x00 + INTERNAL_INTERRUPT_BASE )
#define COM1_INT_LVL        HARR_FUNC_INT_LVL
#define COM2_INT_LVL        HARR_FUNC_INT_LVL

/* Harrier Internal Error Interrupts */

#define HARR_ERR_INT_LVL    ( 0x01 + INTERNAL_INTERRUPT_BASE )

#ifdef  INCLUDE_ATA

	/* IDE controller interrupt level */

#   define IDE_CNTRLR0_INT_LVL     ( 0x0e + ISA_INTERRUPT_BASE )
#endif /* INCLUDE_ATA */

/* Drawbridge internal interrupt levels */

#define DEC2155X_DOORBELL0_INT_LVL  ( 0x00 + DEC2155X_INTERRUPT_BASE )
#define DEC2155X_DOORBELL1_INT_LVL  ( 0x01 + DEC2155X_INTERRUPT_BASE )
#define DEC2155X_DOORBELL2_INT_LVL  ( 0x02 + DEC2155X_INTERRUPT_BASE )
#define DEC2155X_DOORBELL3_INT_LVL  ( 0x03 + DEC2155X_INTERRUPT_BASE )
#define DEC2155X_DOORBELL4_INT_LVL  ( 0x04 + DEC2155X_INTERRUPT_BASE )
#define DEC2155X_DOORBELL5_INT_LVL  ( 0x05 + DEC2155X_INTERRUPT_BASE )
#define DEC2155X_DOORBELL6_INT_LVL  ( 0x06 + DEC2155X_INTERRUPT_BASE )
#define DEC2155X_DOORBELL7_INT_LVL  ( 0x07 + DEC2155X_INTERRUPT_BASE )
#define DEC2155X_DOORBELL8_INT_LVL  ( 0x08 + DEC2155X_INTERRUPT_BASE )
#define DEC2155X_DOORBELL9_INT_LVL  ( 0x09 + DEC2155X_INTERRUPT_BASE )
#define DEC2155X_DOORBELL10_INT_LVL ( 0x0a + DEC2155X_INTERRUPT_BASE )
#define DEC2155X_DOORBELL11_INT_LVL ( 0x0b + DEC2155X_INTERRUPT_BASE )
#define DEC2155X_DOORBELL12_INT_LVL ( 0x0c + DEC2155X_INTERRUPT_BASE )
#define DEC2155X_DOORBELL13_INT_LVL ( 0x0d + DEC2155X_INTERRUPT_BASE )
#define DEC2155X_DOORBELL14_INT_LVL ( 0x0e + DEC2155X_INTERRUPT_BASE )
#define DEC2155X_DOORBELL15_INT_LVL ( 0x0f + DEC2155X_INTERRUPT_BASE )
#define DEC2155X_PWR_MGMT_INT_LVL   ( 0x10 + DEC2155X_INTERRUPT_BASE )
#define DEC2155X_I2O_INT_LVL		( 0x11 + DEC2155X_INTERRUPT_BASE )
#define DEC2155X_PG_CRSSNG_INT_LVL	( 0x12 + DEC2155X_INTERRUPT_BASE )

/* interrupt vector definitions */

#define INT_VEC_IRQ0			0x00	/* vector for IRQ0 */

/* PCI/MPIC interrupt vectors */

#define COM1_INT_VEC        ( INT_VEC_IRQ0 + COM1_INT_LVL )
#define COM2_INT_VEC        ( INT_VEC_IRQ0 + COM2_INT_LVL )
#define COM3_INT_VEC        ( INT_VEC_IRQ0 + COM3_INT_LVL )
#define COM4_INT_VEC        ( INT_VEC_IRQ0 + COM4_INT_LVL )
#define WDTL1_INT_VEC       ( INT_VEC_IRQ0 + WDTL1_INT_LVL )
#define WDTL2_INT_VEC       ( INT_VEC_IRQ0 + WDTL2_INT_LVL )
#define	CPCI_INT_VEC        ( INT_VEC_IRQ0 + DEC2155X_INT_LVL )
#define	PCI_INTA_VEC        ( INT_VEC_IRQ0 + PCI_INT_LVL1 )
#define	PCI_INTB_VEC        ( INT_VEC_IRQ0 + PCI_INT_LVL2 )
#define	PCI_INTC_VEC        ( INT_VEC_IRQ0 + PCI_INT_LVL3 )
#define	PCI_INTD_VEC        ( INT_VEC_IRQ0 + PCI_INT_LVL4 )
#define LN1_INT_VEC         ( INT_VEC_IRQ0 + LN1_INT_LVL )
#define LN2_INT_VEC         ( INT_VEC_IRQ0 + LN2_INT_LVL )
#define PIB_INT_VEC         ( INT_VEC_IRQ0 + PIB_INT_LVL )

#ifndef SLAVE_OWNS_ETHERNET
#    define SLV_LN1_INT_VEC     ( INT_VEC_IRQ0 + SLV_LN1_INT_LVL )
#else /* SLAVE_OWNS_ETHERNET */
#    define SLV_LN1_INT_VEC     ( INT_VEC_IRQ0 + LN1_INT_LVL )
#endif /* SLAVE_OWNS_ETHERNET */

/* Internal Harrier interrupt vectors */

#define HARR_FUNC_INT_VEC   ( INT_VEC_IRQ0 + HARR_FUNC_INT_LVL )
#define HARR_ERR_INT_VEC    ( INT_VEC_IRQ0 + HARR_ERR_INT_LVL )


#ifdef       INCLUDE_ATA
#   define IDE_CNTRLR0_INT_VEC      ( INT_VEC_IRQ0 + IDE_CNTRLR0_INT_LVL )
#endif       /* INCLUDE_ATA */

/* Timer interrupt vectors */

#define TIMER0_INT_VEC      ( INT_VEC_IRQ0 + TIMER0_INT_LVL )

/* Drawbridge interrupt vectors */

#define DEC2155X_DOORBELL0_INT_VEC  (INT_VEC_IRQ0 + DEC2155X_DOORBELL0_INT_LVL)
#define DEC2155X_DOORBELL1_INT_VEC  (INT_VEC_IRQ0 + DEC2155X_DOORBELL1_INT_LVL)
#define DEC2155X_DOORBELL2_INT_VEC  (INT_VEC_IRQ0 + DEC2155X_DOORBELL2_INT_LVL)
#define DEC2155X_DOORBELL3_INT_VEC  (INT_VEC_IRQ0 + DEC2155X_DOORBELL3_INT_LVL)
#define DEC2155X_DOORBELL4_INT_VEC  (INT_VEC_IRQ0 + DEC2155X_DOORBELL4_INT_LVL)
#define DEC2155X_DOORBELL5_INT_VEC  (INT_VEC_IRQ0 + DEC2155X_DOORBELL5_INT_LVL)
#define DEC2155X_DOORBELL6_INT_VEC  (INT_VEC_IRQ0 + DEC2155X_DOORBELL6_INT_LVL)
#define DEC2155X_DOORBELL7_INT_VEC  (INT_VEC_IRQ0 + DEC2155X_DOORBELL7_INT_LVL)
#define DEC2155X_DOORBELL8_INT_VEC  (INT_VEC_IRQ0 + DEC2155X_DOORBELL8_INT_LVL)
#define DEC2155X_DOORBELL9_INT_VEC  (INT_VEC_IRQ0 + DEC2155X_DOORBELL9_INT_LVL)
#define DEC2155X_DOORBELL10_INT_VEC (INT_VEC_IRQ0 + DEC2155X_DOORBELL10_INT_LVL)
#define DEC2155X_DOORBELL11_INT_VEC (INT_VEC_IRQ0 + DEC2155X_DOORBELL11_INT_LVL)
#define DEC2155X_DOORBELL12_INT_VEC (INT_VEC_IRQ0 + DEC2155X_DOORBELL12_INT_LVL)
#define DEC2155X_DOORBELL13_INT_VEC (INT_VEC_IRQ0 + DEC2155X_DOORBELL13_INT_LVL)
#define DEC2155X_DOORBELL14_INT_VEC (INT_VEC_IRQ0 + DEC2155X_DOORBELL14_INT_LVL)
#define DEC2155X_DOORBELL15_INT_VEC (INT_VEC_IRQ0 + DEC2155X_DOORBELL15_INT_LVL)
#define DEC2155X_PWR_MGMT_INT_VEC   (INT_VEC_IRQ0 + DEC2155X_PWR_MGMT_INT_LVL)
#define DEC2155X_I2O_INT_VEC        (INT_VEC_IRQ0 + DEC2155X_I2O_INT_LVL)
#define DEC2155X_PG_CRSSNG_INT_VEC  (INT_VEC_IRQ0 + DEC2155X_PG_CRSSNG_INT_LVL)

/*
 * Address range definitions for PCI bus.
 *
 * Used with vxMemProbe() hook sysBusProbe().
 */

#define IS_PCI_ADDRESS(adrs)	((((UINT32)(adrs) >= \
				 (UINT32)PCI_MSTR_MEMIO_LOCAL) && \
				 ((UINT32)(adrs) < \
				 (UINT32)(PCI_MSTR_MEM_LOCAL + \
				 (PCI_MSTR_MEM_SIZE-1)))) || \
				(((UINT32)(adrs) >= \
				 (UINT32)ISA_MSTR_IO_LOCAL) && \
				 ((UINT32)(adrs) < \
				 (UINT32)(PCI_MSTR_IO_LOCAL + \
				 (PCI_MSTR_IO_SIZE-1)))))

/*
 * Support for determining if we're ROM based or not.  _sysInit
 * saves the startType parameter at location ROM_BASED_FLAG.
 */

#define PCI_AUTOCONFIG_FLAG_OFFSET ( 0x4c00 )
#define PCI_AUTOCONFIG_FLAG        ( *(UCHAR *)(LOCAL_MEM_LOCAL_ADRS + \
				     PCI_AUTOCONFIG_FLAG_OFFSET) )
#define PCI_AUTOCONFIG_DONE        ( PCI_AUTOCONFIG_FLAG != 0 )

#ifdef __cplusplus
    }
#endif /* __cplusplus */

#endif /* INCprpmc800h */