prpmc800.h

vxworks的bsp开发包(基于POWERPC的PRPMC800)

     ((int)(x) + PCI_MSTR_IO_LOCAL - PCI_MSTR_IO_BUS)


/* 60x bus adrs to PCI (non-prefetchable) memory address */

#define LOCAL2PCI_MEMIO(x) \
     ((int)(x) + PCI_SLV_MEM_BUS - PCI_SLV_MEM_LOCAL)
#define PCI2LOCAL_MEMIO(x) \
     ((int)(x) - PCI_SLV_MEM_BUS + PCI_SLV_MEM_LOCAL)

/* Cpu PCI adrs to PCI system address */

#define CPCI2PCI(x) \
     ((int)(x) - PCI_SLV_MEM_LOCAL)
#define PCI2CPCI(x) \
     ((int)(x) + PCI_SLV_MEM_LOCAL)


#define CPU2PCI_ADDR0_START     (PCI_MSTR_MEMIO_LOCAL >> 16)
#define CPU2PCI_ADDR0_END       (((PCI_MSTR_MEM_LOCAL + \
                                (PCI_MSTR_MEM_SIZE-1)) >> 16) & 0x0000FFFF)

#define CPU2PCI_OFFSET0         0x00 
#define CPU2PCI_MSATT0          (HARRIER_PCFS_ITAT_RXT | \
                                 HARRIER_PCFS_ITAT_RXS_MASK | \
                                 HARRIER_PCFS_ITAT_RXS_128BYTES | \
                                 HARRIER_PCFS_OTAT_MEM | \
                                 HARRIER_PCFS_OTAT_ENA)

/* Outbound translation address space 1 for PCI I/O space. */

#define CPU2PCI_ADDR1_START     (ISA_MSTR_IO_LOCAL >> 16)
#define CPU2PCI_ADDR1_END       (((ISA_MSTR_IO_LOCAL + ISA_MSTR_IO_SIZE + \
				  PCI_MSTR_IO_SIZE) - 1) >> 16)

#define CPU2PCI_OFFSET1         (ISA_MSTR_IO_BUS - (ISA_MSTR_IO_LOCAL >> 16))
#define CPU2PCI_MSATT1          (HARRIER_PCFS_ITAT_RXT | \
                                 HARRIER_PCFS_ITAT_RXS_128BYTES | \
                                 HARRIER_PCFS_OTAT_ENA)

/* Outbound translation address space 2 maps to local PCI address 0 */

#define CPU2PCI_ADDR2_START     ((PCI_MSTR_ZERO_LOCAL) >> 16)

#define CPU2PCI_ADDR2_END       ( (PCI_MSTR_ZERO_LOCAL + \
				   PCI_MSTR_ZERO_SIZE  - 1) >> 16 )

#define CPU2PCI_OFFSET2         ( (0 - (PCI_MSTR_ZERO_LOCAL)) >> 16 )

#define CPU2PCI_MSATT2          (HARRIER_PCFS_ITAT_RXT | \
                                 HARRIER_PCFS_ITAT_RXS_MASK | \
                                 HARRIER_PCFS_ITAT_RXS_128BYTES | \
                                 HARRIER_PCFS_OTAT_MEM | \
                                 HARRIER_PCFS_OTAT_ENA)

/* 
 * Outbound translation address space 3 for PCI I/O space.
 * This mapped area starts at ISA_MSTR_IO_LOCAL and maps thru I/O memory.
 */

#define CPU2PCI_ADDR3_START     (ISA_MSTR_IO_LOCAL >> 16)
#define CPU2PCI_ADDR3_END       (((ISA_MSTR_IO_LOCAL + ISA_MSTR_IO_SIZE + \
				  PCI_MSTR_IO_SIZE) - 1) >> 16)

#define CPU2PCI_OFFSET3         (ISA_MSTR_IO_BUS - (ISA_MSTR_IO_LOCAL >> 16))
#define CPU2PCI_MSATT3          (HARRIER_PCFS_OTAT_ENA)

/* PCI to CPU definitions (inbound translations) */

#ifdef LOCAL_MEM_AUTOSIZE
#   define DRAM_SIZE		((ULONG)sysPhysMemTop() - LOCAL_MEM_LOCAL_ADRS)
#else /* LOCAL_MEM_AUTOSIZE */
#   define DRAM_SIZE		(LOCAL_MEM_SIZE - LOCAL_MEM_LOCAL_ADRS)
#endif /* LOCAL_MEM_AUTOSIZE */

/* Inbound mapping for low-order DRAM */

#define INBOUND_DRAM_BAR	HARRIER_INBOUND_TRANSLATION_BASE_ADDRESS_0

/* Local base (target) addresses of input mapping */

#define PCI2CPU_0_TARG		0x0
#define PCI2CPU_1_TARG		0x0
#define PCI2CPU_2_TARG		0x0
#define PCI2CPU_3_TARG		0x0

#define PCI2CPU_0_BASE          (PCI2DRAM_BASE_ADRS & \
                                 HARRIER_PCFS_ITBAR_BASE_MASK)
#define PCI2CPU_0_SIZE          (PCI2DRAM_MAP_SIZE) 	/* 16Mb */
#define PCI2CPU_0_OFFSET        (((0x0-PCI2CPU_0_BASE)>>16) & 0x0000FFFF)
#define PCI2CPU_0_ATTR          (HARRIER_ITAT_AWL | \
                                 HARRIER_ITAT_GBL | \
                                 HARRIER_ITAT_RMT | \
                                 HARRIER_ITAT_RMS_256BYTES | \
                                 HARRIER_ITAT_RXT | \
                                 HARRIER_ITAT_RXS_256BYTES | \
                                 HARRIER_ITAT_ENA | \
                                 HARRIER_ITAT_MEM | \
                                 HARRIER_ITAT_WPE | \
                                 HARRIER_ITAT_RAE | \
                                 HARRIER_ITAT_PRE)

#define PCI2CPU_1_BASE          0x00000000
#define PCI2CPU_1_SIZE          0x00
#define PCI2CPU_1_OFFSET        0x0000
#define PCI2CPU_1_ATTR          0x00000000

#define PCI2CPU_2_BASE          0x00000000
#define PCI2CPU_2_SIZE          0x00
#define PCI2CPU_2_OFFSET        0x0000
#define PCI2CPU_2_ATTR          0x00000000

#define PCI2CPU_3_BASE          0x00000000
#define PCI2CPU_3_SIZE          0x00
#define PCI2CPU_3_OFFSET        0x0000
#define PCI2CPU_3_ATTR          0x00000000


/* Harrier PCI Slave Window definitions */

#define PCI2CPU_MEM0_BUS    PCI_SLV_MEM_BUS
#define PCI2CPU_MEM0_LOCAL  PCI_SLV_MEM_LOCAL
#define PCI2CPU_MEM0_SIZE   DRAM_SIZE
#define PCI2CPU_MEM0_ATT        (HARRIER_PCI_SLV_ATTR_REN_MASK  | \
                 HARRIER_PCI_SLV_ATTR_WEN_MASK  | \
                 HARRIER_PCI_SLV_ATTR_WPEN_MASK | \
                 HARRIER_PCI_SLV_ATTR_RAEN_MASK | \
                 HARRIER_PCI_SLV_ATTR_GBL_MASK  | \
                 HARRIER_PCI_SLV_ATTR_INV_MASK)

/* Inbound translation for access to slave's low-order DRAM from PCI mem space */

#define SLAVE_PCI2CPU_0_BASE	(0x00000000)   /* Slave PCI to CPU memory */
#define SLAVE_PCI2CPU_0_SIZE	(0x01000000) /* 16Mb */
#define SLAVE_PCI2CPU_0_ATTR	(HARRIER_ITAT_AWL | \
                                 HARRIER_ITAT_GBL | \
                                 HARRIER_ITAT_RMT | \
                                 HARRIER_ITAT_RMS_256BYTES | \
                                 HARRIER_ITAT_RXT | \
                                 HARRIER_ITAT_RXS_256BYTES | \
                                 HARRIER_ITAT_ENA | \
                                 HARRIER_ITAT_MEM | \
                                 HARRIER_ITAT_WPE | \
                                 HARRIER_ITAT_RAE | \
                                 HARRIER_ITAT_PRE)

/*
 * Address decoders 1, 2 and 3 are not currently used, so they are
 * set to point to an address that is not used on the PCI bus
 */

#define PCI2CPU_MEM1_BUS    0
#define PCI2CPU_MEM1_LOCAL  0
#define PCI2CPU_MEM1_SIZE   0
#define PCI2CPU_MEM1_ATT    0

#define PCI2CPU_MEM2_BUS    0
#define PCI2CPU_MEM2_LOCAL  0
#define PCI2CPU_MEM2_SIZE   0
#define PCI2CPU_MEM2_ATT    0

#define PCI2CPU_MEM3_BUS    0
#define PCI2CPU_MEM3_LOCAL  0
#define PCI2CPU_MEM3_SIZE   0
#define PCI2CPU_MEM3_ATT    0

/* m48TXX non volatile ram, RTC and watchdog timer */

#ifdef INCLUDE_PRPMC800XT
#   ifdef nonXBus
#      define m48TXX_LSB_REG	(ISA_MSTR_IO_LOCAL + 0x0074)
#      define m48TXX_MSB_REG	(ISA_MSTR_IO_LOCAL + 0x0075)
#      define m48TXX_DAT_REG	(ISA_MSTR_IO_LOCAL + 0x0077)
#   endif /* nonXBus */

    /* RTC - Alarm interrupt level - M48T37V */

#   define RTC_ALARM_LVL       ( 0x04 + EXT_INTERRUPT_BASE )
#   define RTC_ALARM_VEC       ( INT_VEC_IRQ0 + RTC_ALARM_LVL )
#endif /* INCLUDE_PRPMC800XT */

/* CPU type */

#define CPU_TYPE            ((vxPvrGet() >> 16) & 0xffff)
#define CPU_REV             (vxPvrGet() & 0xffff)
#define CPU_TYPE_601        0x01	/* PPC 601 CPU */
#define CPU_TYPE_602        0x02	/* PPC 602 CPU */
#define CPU_TYPE_603        0x03	/* PPC 603 CPU */
#define CPU_TYPE_603E       0x06	/* PPC 603e CPU */
#define CPU_TYPE_603P       0x07	/* PPC 603p CPU */
#define CPU_TYPE_750        0x08	/* PPC 750 CPU */
#define CPU_TYPE_604        0x04	/* PPC 604 CPU */
#define CPU_TYPE_604E       0x09	/* PPC 604e CPU */
#define CPU_TYPE_604R       0x0A	/* PPC 604r CPU */
#define CPU_TYPE_MAX        0x0C    /* PPC MAX CPU */
#define CPU_TYPE_NITRO      0x800C	/* PPC NITRO CPU */
#define CPU_REV_NITRO       0x1100	/* PPC Nitro Rev 1.0 CPU */

/* Vital Product Data (VPD) Support */

#define VPD_BRD_EEPROM_ADRS 0xA0    /* i2c address of board's SROM */
#define USR_BRD_EEPROM_ADRS 0xA2    /* i2c address of user config EEPROM */
#define OPT_BASE_BRD_EEPROM 0xA6    /* Optional Base Board Configuration */
#define SPD_EEPROM_ADRS	    0xA8    /* i2c address of first SPD EEPROM */

#if (CARRIER_TYPE == PRPMC_G)
#   define GPIO_I2C_ADRS    0x30    /* i2c address of W83601 GPIO */
#   define W83782_I2C_ADRS  0x50    /* i2c address of W83782 Registers */
#endif /* (CARRIER_TYPE == PRPMC_G) */

#define VPD_BRD_OFFSET      0	    /* offset into brd's eeprom for vpd data */
#define VPD_PKT_LIMIT       25      /* Max number of packets expected */

#define I2C_SINGLE_ADDRESS  1       /* num addr bytes to write for I2C access */
#define I2C_DUAL_ADDRESS    2       /* num addr bytes to write for I2C access */
#define I2C_ADDRESS_BYTES   I2C_DUAL_ADDRESS /* VPD and user ROM accesses */

#define DEFAULT_PCI_CLOCK	33333333
#define DEFAULT_BUS_CLOCK	100000000
#define DEFAULT_INTERNAL_CLOCK	350000000
#define DEFAULT_PRODUCT_ID	"Unknown"

/* Generic VPD Product Configuration Options (PCO) */

#define PCO_PCI0_CONN1		0	/* PCI Bus 0, connector 1 populated */
#define PCO_PCI0_CONN2		1	/* PCI Bus 0, connector 2 populated */
#define PCO_PCI0_CONN3		2	/* PCI Bus 0, connector 3 populated */
#define PCO_PCI0_CONN4		3	/* PCI Bus 0, connector 4 populated */

#define PCO_PCI1_CONN1		4	/* PCI Bus 1, connector 1 populated */
#define PCO_PCI1_CONN2		5	/* PCI Bus 1, connector 2 populated */
#define PCO_PCI1_CONN3		6	/* PCI Bus 1, connector 3 populated */
#define PCO_PCI1_CONN4		7	/* PCI Bus 1, connector 4 populated */

#define PCO_ISA_CONN1		8	/* ISA Bus connector 1 populated */
#define PCO_ISA_CONN2		9	/* ISA Bus connector 2 populated */
#define PCO_ISA_CONN3		10	/* ISA Bus connector 3 populated */
#define PCO_ISA_CONN4		11	/* ISA Bus connector 4 populated */

#define PCO_EIDE1_CONN1		12	/* IDE controller 1, conn 1 populated */
#define PCO_EIDE1_CONN2		13	/* IDE controller 1, conn 2 populated */
#define PCO_EIDE2_CONN1		14	/* IDE controller 2, conn 1 populated */
#define PCO_EIDE2_CONN2		15	/* IDE controller 2, conn 2 populated */

#define PCO_ENET1_CONN		16	/* Ethernet 1 connector populated */
#define PCO_ENET2_CONN		17	/* Ethernet 2 connector populated */
#define PCO_ENET3_CONN		18	/* Ethernet 3 connector populated */
#define PCO_ENET4_CONN		19	/* Ethernet 4 connector populated */

#define PCO_SCSI1_CONN		20	/* SCSI controller 1 conn populated */
#define PCO_SCSI2_CONN		21	/* SCSI controller 2 conn populated */
#define PCO_SCSI3_CONN		22	/* SCSI controller 3 conn populated */
#define PCO_SCSI4_CONN		23	/* SCSI controller 4 conn populated */

#define PCO_SERIAL1_CONN	24	/* Serial port 1 connector populated */
#define PCO_SERIAL2_CONN	25	/* Serial port 2 connector populated */
#define PCO_SERIAL3_CONN	26	/* Serial port 3 connector populated */
#define PCO_SERIAL4_CONN	27	/* Serial port 4 connector populated */

#define PCO_FLOPPY_CONN1	28	/* Floppy 1 connector populated */
#define PCO_FLOPPY_CONN2	29	/* Floppy 2 connector populated */
#define PCO_PARALLEL1_CONN	30	/* Parallel port 1 conn populated */
#define PCO_PARALLEL2_CONN	31	/* Parallel port 2 conn populated */

#define PCO_PMC1_IO_CONN	32	/* PMC Site 1 I/O conn populated */
#define PCO_PMC2_IO_CONN	33	/* PMC Site 2 I/O conn populated */
#define PCO_USB0_CONN		34	/* USB 0 connector populated */
#define PCO_USB1_CONN		35	/* USB 1 connector populated */

#define PCO_KEYBOARD_CONN	36	/* Keyboard connector populated */
#define PCO_MOUSE_CONN		37	/* Mouse connector populated */
#define PCO_VGA1_CONN		38	/* VGA connector populated */
#define PCO_SPEAKER_CONN	39	/* Speaker connector populated */

#define PCO_VME_CONN		40	/* VME connector populated */
#define PCO_CPCI_CONN		41	/* cPCI connector populated */
#define PCO_ABORT_SWITCH	42	/* Abort switch present */
#define PCO_BDFAIL_LIGHT	43	/* Board Fail LED present */

#define PCO_SWREAD_HEADER	44	/* Sofware-readable header present */
#define PCO_MEMMEZ_CONN		45	/* Memory mezanine connector present */
#define PCO_PCI0EXP_CONN	46	/* PCI Expansion connector present */

/* BSP configuration error policy */

#define CONTINUE_EXECUTION	0       /* Tolerate VPD/Configuration errors */
#define EXIT_TO_SYSTEM_MONITOR	1       /* Transfer to System Monitor */

#ifdef VPD_ERRORS_NONFATAL
#   define  DEFAULT_BSP_ERROR_BEHAVIOR  CONTINUE_EXECUTION
#else /* VPD_ERRORS_NONFATAL */
#   define  DEFAULT_BSP_ERROR_BEHAVIOR  EXIT_TO_SYSTEM_MONITOR
#endif /* VPD_ERRORS_NONFATAL */

/*
 * Bootrom error bits.
 * These bits are set during ROM startup before error annunciation is available
 * to save error conditions for later reporting.
 */

#define BOOTROM_NO_VPD_BUS_SPEED       0x80000000     /* Couldn't read VPD */
#define BOOTROM_DEFAULT_SMC_TIMING     0x40000000     /* Couldn't read SPD */

/* programmable interrupt controller (PIC) */

#define	PIC_REG_ADDR_INTERVAL	1	/* address diff of adjacent regs. */

/* serial ports (COM1 - COM2) */

#ifdef INCLUDE_I8250_SIO
#   define COM1_BASE_ADR	    HARRIER_UART_0_RTDL_REG   /* serial port 1 */
#   define COM2_BASE_ADR	    HARRIER_UART_1_RTDL_REG   /* serial port 2 */
#   define UART_REG_ADDR_INTERVAL   1  	/* addr diff of adjacent regs */
#   ifdef  INCLUDE_PRPMC800XT           /* Extended version of the PrPMC800 */
#      define N_UART_CHANNELS       2   /* No. serial I/O channels */
#   else  /* INCLUDE_PRPMC800XT */
#      define N_UART_CHANNELS       1   /* No. serial I/O channels */
#   endif /* INCLUDE_PRPMC800XT */
#endif /* INCLUDE_I8250_SIO */

/* total number of serial ports */

#ifdef  INCLUDE_PRPMC800XT              /* Extended version of the PrPMC800 */
#   define N_SIO_CHANNELS	2           /* No. serial I/O channels */
#else  /* INCLUDE_PRPMC800XT */
#   define N_SIO_CHANNELS	1           /* No. serial I/O channels */
#endif /* INCLUDE_PRPMC800XT */