prpmc800.h

vxworks的bsp开发包(基于POWERPC的PRPMC800)

/* prpmc800.h - Motorola PrPMC800 board header */

/* Copyright 1984-2001 Wind River Systems, Inc. */
/* Copyright 1999-2001 Motorola, Inc. All Rights Reserved */

/*
modification history
--------------------
01t,31jan02,kab  Remove obsolete vmxExcLoad
01s,16nov01,scb  Harrier outbound 2 maps local PCI at address 0.
01r,15nov01,srr  Updated for Tornado 2.1.
01q,15oct01,scb  Mods to integrate WRS fei driver in lieu of i82559 driver.
01p,10oct01,scb  Shared memory support.
01o,10aug01,srr  Added PrPMC-G carrier board support.
01n,18jun01,srr  Added Harrier DMA support.
01m,08jun01,srr  Remove unused macros.
01l,02may01,bvc  Corrected LN2_INT_LVL to 0x0c
01k,07dec00,krp  Added support for Watchdog Timer
01j,17nov00,dmw  Added slave Ethernet support.
01i,14nov00,dmw  Added slave to Monarch inbound translation.
01h,31oct00,krp  Corrected NvRam Address and size to SROM.
01g,16oct00,dmw  Corrected outbound translation addresses.
01f,12oct00,dmw  Moved ISA_MSTR_IO_LOCAL to 0xFD000000.
01e,09oct00,dmw  Moved ISA_MSTR_IO_LOCAL to 0xFE000000.
01d,08oct00,dmw  Modified memory map for PowerPlusIII.
01c,09sep00,dmw  Updated the number of UARTS/SIO drivers for PrPMC800XT.
01b,09sep00,dmw  Added define for dual-address I2C EEPROM accesses.
01a,31jul00,dmw  Written (from version 01m of mcpn765/mcpn765.h).
*/

/*
This file contains I/O addresses and related constants for the
Motorola PowerPlusIII PrPMC800 board.
*/

#ifndef	INCprpmc800h
#define	INCprpmc800h

#ifdef __cplusplus
    extern "C" {
#endif /* __cplusplus */

/* ATA/EIDE support */

#include "drv/hdisk/ataDrv.h"

#include "harrier.h"

/*
 * Carrier boards available for selection:
 * PRPMC_BASE (default), PRPMC_CARRIER_1, PRPMC_G
 */

#define PRPMC_BASE		0	/* default */
#define PRPMC_CARRIER_1		1
#define PRPMC_G			2

/* Harrier Support */

#define HARRIER_MAX_DEV        1	/* Maximun number of Harriers */

/* MPC7400 (Max) Support */

/* Max SPRs */

#define VRSAVE                 256	/* VMX Save register */
#define UBAMR                  935	/* Performance monitor mask */
#define UMMCR2                 928	/* Performance monitor control */
#define BAMR                   951 	/* Performance monitor mask */
#define MMCR2                  944 	/* Performance monitor control */
#define MSSCR0                 1014	/* Memory Subsystem control */
#define MSSCR1                 1015	/* Memory Subsystem debug */
#define PIR                    1023	/* Processor ID register */

/* Max HID0 bit definitions */

#define _PPC_HID0_NOPDST       0x2	/* Nop dst, dstt, dstst, &dststt*/
#define _PPC_HID0_NOPTI        0x1	/* Nop dcbt and dbtst */


#define INCLUDE_PCI		/* always include pci */

/* Boot Line parameters are stored in the 2nd 256 byte block */

#define NV_RAM_SIZE    		USR_SROM_SIZE	
#define NV_RAM_ADRS    		USR_BRD_EEPROM_ADRS
#define NV_RAM_INTRVL           1

/* PCI I/O function defines */

#define INT_NUM_IRQ0            INT_VEC_IRQ0

#ifndef _ASMLANGUAGE

#ifndef PCI_IN_BYTE
#   define PCI_IN_BYTE(x)	sysPciInByte (x)
    IMPORT  UINT8		sysPciInByte  (UINT32 address);
#endif /* PCI_IN_BYTE */
#ifndef PCI_IN_WORD
#   define PCI_IN_WORD(x)	sysPciInWord (x)
    IMPORT  UINT16		sysPciInWord  (UINT32 address);
#endif /* PCI_IN_WORD */
#ifndef PCI_IN_LONG
#   define PCI_IN_LONG(x)	sysPciInLong (x)
    IMPORT  UINT32		sysPciInLong  (UINT32 address);
#endif /* PCI_IN_LONG */
#ifndef PCI_OUT_BYTE
#   define PCI_OUT_BYTE(x,y)	sysPciOutByte (x,y)
    IMPORT  void		sysPciOutByte (UINT32 address, UINT8  data);
#endif /* PCI_OUT_BYTE */
#ifndef PCI_OUT_WORD
#   define PCI_OUT_WORD(x,y)   sysPciOutWord (x,y)
    IMPORT  void	       sysPciOutWord (UINT32 address, UINT16 data);
#endif /* PCI_OUT_WORD */
#ifndef PCI_OUT_LONG
#   define PCI_OUT_LONG(x,y)	sysPciOutLong (x,y)
    IMPORT  void		sysPciOutLong (UINT32 address, UINT32 data);
#endif /* PCI_OUT_LONG */
#ifndef PCI_INSERT_LONG
#   define PCI_INSERT_LONG(a,m,d) sysPciInsertLong((a),(m),(d))
    IMPORT  void                  sysPciInsertLong(UINT32 adrs, UINT32 mask, \
                                                   UINT32 data);
#endif /* PCI_INSERT_LONG */
#ifndef PCI_INSERT_WORD
#   define PCI_INSERT_WORD(a,m,d) sysPciInsertWord((a),(m),(d))
    IMPORT  void                  sysPciInsertWord(UINT32 adrs, UINT16 mask, \
                                                   UINT16 data);
#endif /* PCI_INSERT_WORD */
#ifndef PCI_INSERT_BYTE
#   define PCI_INSERT_BYTE(a,m,d) sysPciInsertByte((a),(m),(d))
    IMPORT  void                  sysPciInsertByte(UINT32 adrs, UINT8 mask, \
                                                   UINT8 data);
#endif /* PCI_INSERT_BYTE */

#endif  /* _ASMLANGUAGE */

/* Cache Line Size - 8 32-bit values = 32 bytes */

#define PCI_CLINE_SZ		(_CACHE_ALIGN_SIZE/4)

/* Latency Timer value - 255 PCI clocks */

#define PCI_LAT_TIMER		0xff

/* clock rates */

/* Calculate Memory Bus Rate in Hertz */

#define MEMORY_BUS_SPEED	( sysGetBusSpd() )

/* System clock (decrementer counter) frequency determination */

#define DEC_CLOCK_FREQ		( sysGetBusSpd() )

/*
 * The PowerPC Decrementer is used as the system clock.
 * It is always included in this BSP.  The following defines
 * are used by the system clock library.
 */

#define SYS_CLK_RATE_MIN	10		/* minimum system clock rate */
#define SYS_CLK_RATE_MAX	5000		/* maximum system clock rate */

/*
 * This macro returns the positive difference between two signed ints.
 * Useful for determining delta between two successive decrementer reads.
 */

#define DELTA(a,b)		( abs((int)a - (int)b) )

/*
 * Auxiliary Clock support is an optional feature that is not supported
 * by all BSPs.  The following defines are used by the aux clock library.
 */

#define AUX_CLK_RATE_MIN	40		/* min auxiliary clock */
#define AUX_CLK_RATE_MAX	5000		/* max auxiliary clock rate */

/* Common I/O synchronizing instructions */

#ifndef EIEIO_SYNC
#   define EIEIO_SYNC  WRS_ASM ("eieio;sync")
#endif	/* EIEIO_SYNC */
#ifndef EIEIO
#   define EIEIO    WRS_ASM ("eieio")
#endif	/* EIEIO */

/* Translation macro */

#define TRANSLATE(x,y,z)\
        ((UINT)(x) - (UINT)(y) + (UINT)(z))

/* Legacy ISA space size. Reserved for kybd, com1, com2,... */

#define ISA_LEGACY_SIZE		0x00004000

#define ISA_MSTR_IO_SIZE	0x00010000	/* 64 kbytes (includes legacy)*/

#define ISA_MSTR_IO_BUS		0x00000000	/* must be zero */

/* ISA I/O space within PCI I/O space (includes ISA legacy space) */

#define ISA_MSTR_IO_LOCAL	0xFD000000  /* base of ISA I/O space */

/* Access to PCI nonprefetchable memory space (including ISA memory space)*/

#define PCI_MSTR_MEMIO_BUS	PCI_MSTR_MEMIO_LOCAL	/* 1-1 mapping */

/* PCI I/O space (above ISA I/O space) */

/*
 * NOTE: (PCI_MSTR_IO_LOCAL+PCI_MSTR_IO_SIZE) must be less than
 *        PCI_MSTR_MEMIO_LOCAL to prevent overlap.
 */

#define PCI_MSTR_IO_LOCAL	(ISA_MSTR_IO_LOCAL+ISA_MSTR_IO_SIZE)
#define PCI_MSTR_IO_BUS		(TRANSLATE(PCI_MSTR_IO_LOCAL,\
				 ISA_MSTR_IO_LOCAL,\
				 ISA_MSTR_IO_BUS))

/* PCI (pre-fetchable) Memory space (above ISA memory space) */

#define PCI_MSTR_MEM_LOCAL	(PCI_MSTR_MEMIO_LOCAL+PCI_MSTR_MEMIO_SIZE)
#define PCI_MSTR_MEM_BUS	(TRANSLATE(PCI_MSTR_MEM_LOCAL,\
				 PCI_MSTR_MEMIO_LOCAL,\
				 PCI_MSTR_MEMIO_BUS))

/*
 * Local address which maps to PCI address zero, so PrPMC can "see"
 * DRAM on CPU card on which it is mounted.  
 * Note: PCI_MSTR_MEM_LOCAL + PCI_MSTR_MEM_SIZE must be <= ISA_MSTR_IO_LOCAL
 */

#define PCI_MSTR_ZERO_LOCAL PCI_MSTR_MEM_LOCAL + \
			    PCI_MSTR_MEM_SIZE

/* defines for memory */

#define SIZE_32MB           0x02000000
#define SIZE_64MB           0x04000000
#define SIZE_128MB          0x08000000
#define SIZE_256MB          0x10000000
#define SIZE_512MB          0x20000000

#define	FLASH_BASE_ADRS     0xF0000000
#define	FLASH_MEM_SIZE      0x0E000000
#define FLASH_ADRS	    FLASH_BASE_ADRS
#define FLASH_SIZE          0x02000000
#define FLASH_WIDTH         0x10

/* MPIC configuration defines */

#define MPIC_BASE_ADRS      0xFC000000
#define MPIC_REG_SIZE       0x00040000

#define MPIC_PCI_BASE_ADRS MPIC_BASE_ADRS

/* Ethernet buffer alignment for low memory */

#define PPC_PAGE_SIZE       0x0001000
#define ENET_BUF_ALIGN(addr)                         \
        (((UINT32)(addr)+PPC_PAGE_SIZE) & ~(PPC_PAGE_SIZE-1))

/* memory map as seen on the PCI bus */

#define PCI_SLV_MEM_LOCAL   LOCAL_MEM_LOCAL_ADRS

/* memory seen from PCI bus */

#define PCI_SLV_MEM_BUS  (LONGSWAP(*(UINT32 *)HARRIER_INBOUND_TRANSLATION_BASE_ADDRESS_0) &  HARRIER_PCFS_ITBAR_BASE_MASK)

#define PCI_SLV_PMEP_BUS (LONGSWAP(*(UINT32 *)HARRIER_XCSR_MPBAR) & HARRIER_PCFS_MPBAR_BASE_MASK)

/*
 * The following #define is set to indicate that the drawbridge has dynamic
 * downstream translation (translation that cannot be computed until run time).
 * Setting this #define will disable the compile-time downstream 
 * cPCI window size/translation compatibility check.
 */

#define CPCI_DOWNSTREAM_DYNAMIC_TRANSLATION 

#define PCI2DRAM_BASE_ADRS  PCI_SLV_MEM_BUS

/*
 * Primary PCI bus configuration space address and data register addresses
 * as seen by the CPU on the local bus.
 */

#define PCI_PRIMARY_CAR     ISA_MSTR_IO_LOCAL + 0xCF8
#define PCI_PRIMARY_CDR     ISA_MSTR_IO_LOCAL + 0xCFC

/* Special dec21143 configuration device driver area register */

#define PCI_CFG_21143_DA    0x40

/* PCI Device/Vendor IDs */

#define PCI_ID_HARRIER      0x480B1057      /* Id for Harrier PHB */
#define PCI_ID_UNIVERSE     0x000010e3      /* Id for Universe VME chip */
#define PCI_ID_LN_DEC21040  0x00021011      /* Id DEC 21040 */
#define PCI_ID_LN_DEC21140  0x00091011      /* Id DEC 21140 */
#define PCI_ID_LN_DEC21143  0x00191011      /* Id DEC 21143 */
#define PCI_ID_I82559       0x12298086      /* Id for Intel 82559 */
#define PCI_ID_I82559ER     0x12098086      /* Id for Intel 82559 ER */
#define PCI_ID_BR_DEC21554  0x00461011      /* Id DEC 21554 PCI bridge */


/* CPU to PCI definitions */

/* 
 * Outbound translation address space 0 for PCI MEM space.
 * This mapped area starts at PCI_MSTR_MEMIO_LOCAL for PCI_MSTR_MEM_SIZE.
 * PCI_MSTR_MEM_SIZE is 32MB by default and can be extended to 3.75GB minus
 * the PCI_MSTR_MEMIO_LOCAL.   Note that PCI_MSTR_MEMIO_LOCAL must be greater
 * than or equal to the amount of DRAM.  This area has a null offset associated 
 * with it and is marked as prefetchable PCI memory.
 */


/* add PCI access macros */
#define PCI_MEMIO2LOCAL(x) \
     ((int)(x) + PCI_MSTR_MEMIO_LOCAL - PCI_MSTR_MEMIO_BUS)

/* PCI IO memory adrs to CPU (60x bus) adrs */

#define PCI_IO2LOCAL(x) \