harrierphb.c

vxworks的bsp开发包(基于POWERPC的PRPMC800)

/* harrierPhb.c - Harrier PCI-Host Bridge (PHB) chip initialization */

/* Copyright 1984-2001 Wind River Systems, Inc. */
/* Copyright 1996-2001 Motorola, Inc., All Rights Reserved */

/*
modification history
--------------------
01n,16nov01,scb  Map outbound 2 to local PCI bus address zero.
01m,10oct01,scb  Fix PCI memory mapping in preparation for shared memory.
01l,11jul01,scb  Slave inbound 0 maps only low-order DRAM (not all DRAM).
01k,11aug01,scb  PPC Abiter register and misc. ctl & stat reg mods.
01j,12jun01,srr  Don't enable memory access if running as a slave.
01i,08jun01,srr  Removed unneeded parameters.
01h,07dec00,krp  Added support for Watchdog Timer
01g,17nov00,dmw  Added slave Ethernet support.
01f,14nov00,dmw  Added inbound/outbound PCI windows for Monarch/Slave.
01e,27oct00,dmw  Added Xport windows and attributes.
01d,16oct00,dmw  Fixed bridge initialization.
01c,08oct00,dmw  Stubbed sysHarrierInitPhbExt, handled by romInit.
01b,12sep00,dmw  Removed byte swapping for 60x bus.
01a,31aug00,dmw  Written (from version 01b of mpcn765/hawkPhb.c).
*/

/*
DESCRIPTION
The following contains the initialization routines
for the Harrier PHB, a Host PCI Bridge/Memory Controller used in
Motorola's PowerPC based boards.
*/

/* includes */

#include "harrier.h"


/* defines */

#define MHZ	1000000
#define SHORTSWAP(x) (((x & 0xFF00) >> 8) | ((x & 0x00FF) << 8))

/* typedefs */

/* globals */

/* forward declarations */

/* externals */

IMPORT	UINT32  sysGetBusSpd(void);
IMPORT	BOOL	sysSysconAsserted (void);


/*******************************************************************************
*
* sysHarrierPhbInit - initialize the Harrier PHB registers
*
* This function performs the first phase of the Harrier PPC-bus registers and
* sets up the CPU->PCI windows.
*
* RETURNS: N/A
*/

void sysHarrierPhbInit (void)
    {

    /* 
     * If the PCI configuration cycles hold off bit is clear, we've already
     * configured the bridge.  Just return. 
     */

    if ((*(UINT32 *)HARRIER_BRIDGE_PCI_CONTROLSTATUS_REG & 
        HARRIER_BPCS_XCSR_CSH) == 0)
        return;

    /* Disable the PCI Bridge */

    *(UINT16 *)HARRIER_PHB_COMMAND_REG &= ~(HARRIER_CMMD_MTSR |
                                            HARRIER_CMMD_MEMSP |
                                            HARRIER_CMMD_IOSP);
    EIEIO_SYNC;

    *(UINT32 *)HARRIER_BRIDGE_PCI_CONTROLSTATUS_REG = HARRIER_BPCS_XCSR_CSH;

    EIEIO_SYNC;

    /* Set Read-Ahead Sync Flush, Store-Gather Sync Flush, Copyback Snarfing */

    *(UINT16 *)HARRIER_BRIDGE_PPC_CONTROLSTATUS_REG |= HARRIER_BXCS_RSF |
                                                       HARRIER_BXCS_SSF |
                                                       HARRIER_BXCS_CSE;
    EIEIO_SYNC;

    /*
     * set the PCI Arbiter.  the default will be:
     *      Priority="Round Robin"
     *      Parking Scheme="Park on last master"
     *      Enable="Enabled"
     */

    *(UINT16 *)HARRIER_PCI_ARBITER_REG = HARRIER_PARB_PRI_ROUNDROBIN |
                                         HARRIER_PARB_ENABLE;

    EIEIO_SYNC;

    /*
     * set the PPC Arbiter.  the default will be:
     *      Parking Scheme="Park on last master"
     *      Enable="Enabled"
     */

    *(UINT16 *)HARRIER_PPC_ARBITER_REG = HARRIER_XARB_PRK_LASTCPU |
                                         HARRIER_XARB_ENABLE;

    EIEIO_SYNC;

    /* Setup Vendor ID and subsystem ID */

    *(UINT16 *)HARRIER_SUBSYSTEM_VENDORID_REG = 
	       SHORTSWAP(HARRIER_SUB_VNDR_ID_VAL);
    *(UINT16 *)HARRIER_SUBSYSTEM_ID_REG = 
	       SHORTSWAP(HARRIER_SUB_SYS_ID_VAL);

    /* clear the Outbound Translation Address Registers 0, 1, and 2 */

    *(UINT32 *)(HARRIER_OUTBOUND_TRANSLATION_ADDR_0_REG) = 0;
    EIEIO_SYNC;

    *(UINT32 *)(HARRIER_OUTBOUND_TRANSLATION_ADDR_1_REG) = 0;
    EIEIO_SYNC;

    *(UINT32 *)(HARRIER_OUTBOUND_TRANSLATION_ADDR_2_REG) = 0;
    EIEIO_SYNC;

    /* clear the Outbound Translation Attribute Registers 0, 1, and 2 */

    *(UINT32 *)(HARRIER_OUTBOUND_TRANSLATION_ADDR_0_REG + 
                HARRIER_OUTBOUND_TRANSLATION_OFFSETINFO_OFFSET) = 0;

    EIEIO_SYNC;

    *(UINT32 *)(HARRIER_OUTBOUND_TRANSLATION_ADDR_1_REG + 
                HARRIER_OUTBOUND_TRANSLATION_OFFSETINFO_OFFSET) = 0;

    EIEIO_SYNC;

    *(UINT32 *)(HARRIER_OUTBOUND_TRANSLATION_ADDR_2_REG + 
                HARRIER_OUTBOUND_TRANSLATION_OFFSETINFO_OFFSET) = 0;

    EIEIO_SYNC;

    /*
     * set the Outbound Translation Address Register 3.
     * This register maps the PCI CONFIG_ADDR and CONFIG_DATA
     * registers to PCI I/O space.  The default is CHRP(Map B)
     * addressing, which places the registers at:
     *      CONFIG_ADDR = ISA_MSTR_IO_LOCAL + 0xCF8
     *      CONFIG_DATA = ISA_MSTR_IO_LOCAL + 0xCFC
     */

    *(UINT32 *)HARRIER_OUTBOUND_TRANSLATION_ADDR_3_REG = ISA_MSTR_IO_LOCAL |
        ((ISA_MSTR_IO_LOCAL >> 16) | 0x0F);

    EIEIO_SYNC;

    /* enable ENA=1,WPE=0,IOM=0 and set offet */

    *(UINT32 *)(HARRIER_OUTBOUND_TRANSLATION_ADDR_3_REG + 
                HARRIER_OUTBOUND_TRANSLATION_OFFSETINFO_OFFSET) = 
                HARRIER_PCFS_ITAT_ENA | 
	        ((ISA_MSTR_IO_BUS - (ISA_MSTR_IO_LOCAL >> 16)) << 16);

    EIEIO_SYNC;

    /* disable the Passive Slave registers */

    *(UINT32 *)HARRIER_PASSIVE_SLAVEADDRESS_REG = 0;

    EIEIO_SYNC;

    *(UINT32 *)HARRIER_PASSIVE_SLAVEOFFSET_REG = 0;

    EIEIO_SYNC;

    /* Set outbound translation register 0 to the top of DRAM */

    *(UINT32 *)(HARRIER_OUTBOUND_TRANSLATION_ADDR_0_REG) = 
               ((CPU2PCI_ADDR0_START<<16) | CPU2PCI_ADDR0_END);

    EIEIO_SYNC;

    /* Set offset and attributes */

    *(UINT32 *)(HARRIER_OUTBOUND_TRANSLATION_ADDR_0_REG +
                HARRIER_OUTBOUND_TRANSLATION_OFFSETINFO_OFFSET) =
                ((CPU2PCI_OFFSET0 << 16) | CPU2PCI_MSATT0);

    EIEIO_SYNC;

    /* Set CPU->PCI window 1 for PCI I/O space */

    *(UINT32 *)(HARRIER_OUTBOUND_TRANSLATION_ADDR_1_REG) = 
               ((CPU2PCI_ADDR1_START << 16) | (CPU2PCI_ADDR1_END));

    EIEIO_SYNC;

    *(UINT32 *)(HARRIER_OUTBOUND_TRANSLATION_ADDR_1_REG +
                HARRIER_OUTBOUND_TRANSLATION_OFFSETINFO_OFFSET) =
                ((CPU2PCI_OFFSET1 << 16) | CPU2PCI_MSATT1);

    EIEIO_SYNC;

    /* Set CPU->PCI window 2 (maps local PCI address 0) */

    *(UINT32 *)(HARRIER_OUTBOUND_TRANSLATION_ADDR_2_REG) = 
               ((CPU2PCI_ADDR2_START<<16) | CPU2PCI_ADDR2_END);

    EIEIO_SYNC;

    *(UINT32 *)(HARRIER_OUTBOUND_TRANSLATION_ADDR_2_REG +
                HARRIER_OUTBOUND_TRANSLATION_OFFSETINFO_OFFSET) =
                ((CPU2PCI_OFFSET2 << 16) | CPU2PCI_MSATT2);

    EIEIO_SYNC;

    /* 
     * Enable visibility of message passing register group.  Setting the
     * bit below will ensure that the MPBAR (Harrier BAR at PCI config
     * offset 0x10 will be visible during PCI autoconfiguration and
     * will request 0x1000 (4K) bytes of memory
     */

    *(UINT32 *)(HARRIER_MSG_PASSINGATTR_REG) = HARRIER_MPAT_ENA;

    EIEIO_SYNC;

    /* Set up the PCFS Register. Turn everthing off and clear error status */

    *(UINT32 *)HARRIER_PHB_COMMAND_REG = HARRIER_STAT_RCVPE |
                                         HARRIER_STAT_SIGSE |
                                         HARRIER_STAT_RCVMA |
                                         HARRIER_STAT_RCVTA |
                                         HARRIER_STAT_SIGTA |
                                         HARRIER_STAT_DPAR;
    EIEIO_SYNC;

    *(UINT32 *)HARRIER_CACHE_LINESIZE_REG = HARRIER_CACHE_LINESIZE |
                                            HARRIER_READLATENCY;

    EIEIO_SYNC;

    /* Setup interrupt line register INTL=00,INT=1(INT_A),MNGN=00,MXLA=00 */

    *(UINT32 *)HARRIER_INTERRUPT_LINE_REG = HARRIER_INTP_1;

    EIEIO_SYNC;

    /*
     * Disable all inbound translation registers (ITBAR) - 
     * we'll enable some later.
     */

    *(UINT32 *)HARRIER_INBOUND_TRANSLATION_BASE_ADDRESS_0 = 0;
    *(UINT32 *)HARRIER_INBOUND_TRANSLATION_ATTRIBUTE_0    = 0; 
    *(UINT8 *)HARRIER_INBOUND_TRANSLATION_SIZE_0_REG      = inboundSizeCode(0);