harrier.h

vxworks的bsp开发包(基于POWERPC的PRPMC800)

/* HARRIER_DMA_SOURCEATTR_REG	 (DSAT) XCSR+$264 */

#define HARRIER_DSAT_TYP_MASK		(3<<28)	/* DMA source type mask */
#define HARRIER_DSAT_TYP_PPCBUS		(0<<28)	/* DMA source is PPC bus */
#define HARRIER_DSAT_TYP_PCIBUS		(1<<28)	/* DMA source is PCI bus */
#define HARRIER_DSAT_TYP_DATAPATTERN	(2<<28)	/* DMA source is data pattern */

#define HARRIER_DSAT_NIN		(1<<24)	/* disable source increment */
#define HARRIER_DSAT_PSZ		(1<<16)	/* data pattern transfer size */
#define HARRIER_DSAT_PRC_MASK		(0xf<<8) /* PCI Read Cmd Mask */ 
#define HARRIER_DSAT_PRC_IO		(2<<8)	/* PCI IO Read Cmd */ 
#define HARRIER_DSAT_PRC_MEM		(6<<8)	/* PCI Memory Read Cmd */ 
#define HARRIER_DSAT_PRC_MEM_MULTI	(0xc<<8) /* PCI Memory Read Multi Cmd */
#define HARRIER_DSAT_PRC_MEM_LINE	(0xe<<8) /* PCI Mem Read Line Cmd */ 
#define HARRIER_DSAT_CRI		(1<<2)	/* cache line read invalidate */
#define HARRIER_DSAT_GBL		(1<<0)	/* assert GBL_ for PPC reads */



/* HARRIER_DMA_DESTINATIONATTR_REG     (DDAT) XCSR+$26C */

#define HARRIER_DDAT_TYP_MASK		(1<<28)  /* DMA destination type */
#define HARRIER_DDAT_TYP_PPCBUS 	(0<<28)  /* DMA destination type */
#define HARRIER_DDAT_TYP_PCIBUS 	(1<<28)  /* DMA destination type */
#define HARRIER_DDAT_NIN		(1<<24)  /* disable dest increment */
#define HARRIER_DDAT_PWC_MASK		(0xf<<8) /* PCI Write Cmd Mask */ 
#define HARRIER_DDAT_PWC_IO		(3<<8)	 /* PCI IO Write Cmd */
#define HARRIER_DDAT_PWC_MEM		(7<<8)	 /* PCI Memory Write Cmd */
#define HARRIER_DDAT_PWC_MEM_INV	(0xf<<8) /* PCI Mem Write and Inv Cmd */
#define HARRIER_DDAT_CWF		(1<<1)	 /* cache line write flush */
#define HARRIER_DDAT_GBL		(1<<0)	 /* assert GBL_ for PPC writes */



/* HARRIER_DMA_NEXTLINKADDR_REG    (DNLA) XCSR+$270 */

#define HARRIER_DNLA_NLA_MASK		0xFFFFFFE0 /* next link address mask */
#define HARRIER_DNLA_LLA		(1<<0)	   /* last link address flag */

/* HARRIER_MP_GENERIC_OUTBOUNDDOORBELL_REG  (MGOD)   XCSR+$298 */

#define	HARRIER_MGOD_ODBI31		(0x1<<31)	/* MGOD DB 31 */
#define	HARRIER_MGOD_ODBI30		(0x1<<30)	/* MGOD DB 30 */
#define	HARRIER_MGOD_ODBI29		(0x1<<29)	/* MGOD DB 29 */
#define	HARRIER_MGOD_ODBI28		(0x1<<28)	/* MGOD DB 28 */
#define	HARRIER_MGOD_ODBI27		(0x1<<27)	/* MGOD DB 27 */
#define	HARRIER_MGOD_ODBI26		(0x1<<26)	/* MGOD DB 26 */
#define	HARRIER_MGOD_ODBI25		(0x1<<25)	/* MGOD DB 25 */
#define	HARRIER_MGOD_ODBI24		(0x1<<24)	/* MGOD DB 24 */
#define	HARRIER_MGOD_ODBI23		(0x1<<23)	/* MGOD DB 23 */
#define	HARRIER_MGOD_ODBI22		(0x1<<22)	/* MGOD DB 22 */
#define	HARRIER_MGOD_ODBI21		(0x1<<21)	/* MGOD DB 21 */
#define	HARRIER_MGOD_ODBI20		(0x1<<20)	/* MGOD DB 20 */
#define	HARRIER_MGOD_ODBI19		(0x1<<19)	/* MGOD DB 19 */
#define	HARRIER_MGOD_ODBI18		(0x1<<18)	/* MGOD DB 18 */
#define	HARRIER_MGOD_ODBI17		(0x1<<17)	/* MGOD DB 17 */
#define	HARRIER_MGOD_ODBI16		(0x1<<16)	/* MGOD DB 16 */
#define	HARRIER_MGOD_ODBI15		(0x1<<15)	/* MGOD DB 15 */
#define	HARRIER_MGOD_ODBI14		(0x1<<14)	/* MGOD DB 14 */
#define	HARRIER_MGOD_ODBI13		(0x1<<13)	/* MGOD DB 13 */
#define	HARRIER_MGOD_ODBI12		(0x1<<12)	/* MGOD DB 12 */
#define	HARRIER_MGOD_ODBI11		(0x1<<11)	/* MGOD DB 11 */
#define	HARRIER_MGOD_ODBI10		(0x1<<10)	/* MGOD DB 10 */
#define	HARRIER_MGOD_ODBI9		(0x1<<9)	/* MGOD DB 9 */
#define	HARRIER_MGOD_ODBI8		(0x1<<8)	/* MGOD DB 8 */
#define	HARRIER_MGOD_ODBI7		(0x1<<7)	/* MGOD DB 7 */
#define	HARRIER_MGOD_ODBI6		(0x1<<6)	/* MGOD DB 6 */
#define	HARRIER_MGOD_ODBI5		(0x1<<5)	/* MGOD DB 5 */
#define	HARRIER_MGOD_ODBI4		(0x1<<4)	/* MGOD DB 4 */
#define	HARRIER_MGOD_ODBI3		(0x1<<3)	/* MGOD DB 3 */
#define	HARRIER_MGOD_ODBI2		(0x1<<2)	/* MGOD DB 2 */
#define	HARRIER_MGOD_ODBI1		(0x1<<1)	/* MGOD DB 1 */
#define	HARRIER_MGOD_ODBI0		(0x1<<0)	/* MGOD DB 0 */


/*  HARRIER_MP_GENERIC_INBOUNDDOORBELL_REG   (MGID)   XCSR+$2A8 */

#define	HARRIER_MGID_IDBI7		(0x1<<31)	/* MGID DB 7 */
#define	HARRIER_MGID_IDBI6		(0x1<<30)	/* MGID DB 6 */
#define	HARRIER_MGID_IDBI5		(0x1<<29)	/* MGID DB 5 */
#define	HARRIER_MGID_IDBI4		(0x1<<28)	/* MGID DB 4 */
#define	HARRIER_MGID_IDBI3		(0x1<<27)	/* MGID DB 3 */
#define	HARRIER_MGID_IDBI2		(0x1<<26)	/* MGID DB 2 */
#define	HARRIER_MGID_IDBI1		(0x1<<25)	/* MGID DB 1 */
#define	HARRIER_MGID_IDBI0		(0x1<<24)	/* MGID DB 0 */

#define	HARRIER_MGID_IDBI15		(0x1<<23)	/* MGID DB 15 */
#define	HARRIER_MGID_IDBI14		(0x1<<22)	/* MGID DB 14 */
#define	HARRIER_MGID_IDBI13		(0x1<<21)	/* MGID DB 13 */
#define	HARRIER_MGID_IDBI12		(0x1<<20)	/* MGID DB 12 */
#define	HARRIER_MGID_IDBI11		(0x1<<19)	/* MGID DB 11 */
#define	HARRIER_MGID_IDBI10		(0x1<<18)	/* MGID DB 10 */
#define	HARRIER_MGID_IDBI9		(0x1<<17)	/* MGID DB 9 */
#define	HARRIER_MGID_IDBI8		(0x1<<16)	/* MGID DB 8 */

#define	HARRIER_MGID_IDBI23		(0x1<<15)	/* MGID DB 23 */
#define	HARRIER_MGID_IDBI22		(0x1<<14)	/* MGID DB 22 */
#define	HARRIER_MGID_IDBI21		(0x1<<13)	/* MGID DB 21 */
#define	HARRIER_MGID_IDBI20		(0x1<<12)	/* MGID DB 20 */
#define	HARRIER_MGID_IDBI19		(0x1<<11)	/* MGID DB 19 */
#define	HARRIER_MGID_IDBI18		(0x1<<10)	/* MGID DB 18 */
#define	HARRIER_MGID_IDBI17		(0x1<<9)	/* MGID DB 17 */
#define	HARRIER_MGID_IDBI16		(0x1<<8)	/* MGID DB 16 */

#define	HARRIER_MGID_IDBI31		(0x1<<7)	/* MGID DB 31 */
#define	HARRIER_MGID_IDBI30		(0x1<<6)	/* MGID DB 30 */
#define	HARRIER_MGID_IDBI29		(0x1<<5)	/* MGID DB 29 */
#define	HARRIER_MGID_IDBI28		(0x1<<4)	/* MGID DB 28 */
#define	HARRIER_MGID_IDBI27		(0x1<<3)	/* MGID DB 27 */
#define	HARRIER_MGID_IDBI26		(0x1<<2)	/* MGID DB 26 */
#define	HARRIER_MGID_IDBI25		(0x1<<1)	/* MGID DB 25 */
#define	HARRIER_MGID_IDBI24		(0x1<<0)	/* MGID DB 24 */


#define HARRIER_MP_GENERIC_INBOUNDDOORBELLMASK_REG (HARRIER_XCSR_BASE + 0x2B0)
#define HARRIER_XCSR_MGIDM HARRIER_MP_GENERIC_INBOUNDDOORBELLMASK_REG

#define	HARRIER_MGIDM_IDBM7_MASK	(0x1<<31)	/* MGIDM DB 7 Mask */
#define	HARRIER_MGIDM_IDBM6_MASK	(0x1<<30)	/* MGIDM DB 6 Mask */
#define	HARRIER_MGIDM_IDBM5_MASK	(0x1<<29)	/* MGIDM DB 5 Mask */
#define	HARRIER_MGIDM_IDBM4_MASK	(0x1<<28)	/* MGIDM DB 4 Mask */
#define	HARRIER_MGIDM_IDBM3_MASK	(0x1<<27)	/* MGIDM DB 3 Mask */
#define	HARRIER_MGIDM_IDBM2_MASK	(0x1<<26)	/* MGIDM DB 2 Mask */
#define	HARRIER_MGIDM_IDBM1_MASK	(0x1<<25)	/* MGIDM DB 1 Mask */
#define	HARRIER_MGIDM_IDBM0_MASK	(0x1<<24)	/* MGIDM DB 0 Mask */

#define	HARRIER_MGIDM_IDBM15_MASK	(0x1<<23)	/* MGIDM DB 15 Mask */
#define	HARRIER_MGIDM_IDBM14_MASK	(0x1<<22)	/* MGIDM DB 14 Mask */
#define	HARRIER_MGIDM_IDBM13_MASK	(0x1<<21)	/* MGIDM DB 13 Mask */
#define	HARRIER_MGIDM_IDBM12_MASK	(0x1<<20)	/* MGIDM DB 12 Mask */
#define	HARRIER_MGIDM_IDBM11_MASK	(0x1<<19)	/* MGIDM DB 11 Mask */
#define	HARRIER_MGIDM_IDBM10_MASK	(0x1<<18)	/* MGIDM DB 10 Mask */
#define	HARRIER_MGIDM_IDBM9_MASK	(0x1<<17)	/* MGIDM DB 9 Mask */
#define	HARRIER_MGIDM_IDBM8_MASK	(0x1<<16)	/* MGIDM DB 8 Mask */

#define	HARRIER_MGIDM_IDBM23_MASK	(0x1<<15)	/* MGIDM DB 23 Mask */
#define	HARRIER_MGIDM_IDBM22_MASK	(0x1<<14)	/* MGIDM DB 22 Mask */
#define	HARRIER_MGIDM_IDBM21_MASK	(0x1<<13)	/* MGIDM DB 21 Mask */
#define	HARRIER_MGIDM_IDBM20_MASK	(0x1<<12)	/* MGIDM DB 20 Mask */
#define	HARRIER_MGIDM_IDBM19_MASK	(0x1<<11)	/* MGIDM DB 19 Mask */
#define	HARRIER_MGIDM_IDBM18_MASK	(0x1<<10)	/* MGIDM DB 18 Mask */
#define	HARRIER_MGIDM_IDBM17_MASK	(0x1<<9)	/* MGIDM DB 17 Mask */
#define	HARRIER_MGIDM_IDBM16_MASK	(0x1<<8)	/* MGIDM DB 16 Mask */

#define	HARRIER_MGIDM_IDBM31_MASK	(0x1<<7)	/* MGIDM DB 31 Mask */
#define	HARRIER_MGIDM_IDBM30_MASK	(0x1<<6)	/* MGIDM DB 30 Mask */
#define	HARRIER_MGIDM_IDBM29_MASK	(0x1<<5)	/* MGIDM DB 29 Mask */
#define	HARRIER_MGIDM_IDBM28_MASK	(0x1<<4)	/* MGIDM DB 28 Mask */
#define	HARRIER_MGIDM_IDBM27_MASK	(0x1<<3)	/* MGIDM DB 27 Mask */
#define	HARRIER_MGIDM_IDBM26_MASK	(0x1<<2)	/* MGIDM DB 26 Mask */
#define	HARRIER_MGIDM_IDBM25_MASK	(0x1<<1)	/* MGIDM DB 25 Mask */
#define	HARRIER_MGIDM_IDBM24_MASK	(0x1<<0)	/* MGIDM DB 24 Mask */

#define HARRIER_MI2OHT_PTR_MASK		(16<<2)


/* HARRIER_MP_I2O_CONTROL_REG	(MICT) XCSR+$2E0 */

#define HARRIER_MICT_ENA		(1<<8) /* Enable I2O MP */
#define HARRIER_MICT_QSZ_MASK		(7<<0) /* Queue Size Mask */
#define HARRIER_MICT_QSZ_2K		(0<<0) /* Queue Size */
#define HARRIER_MICT_QSZ_4K		(1<<0) /* Queue Size */
#define HARRIER_MICT_QSZ_8K		(2<<0) /* Queue Size */
#define HARRIER_MICT_QSZ_16K		(3<<0) /* Queue Size */
#define HARRIER_MICT_QSZ_32K		(4<<0) /* Queue Size */
#define HARRIER_MICT_QSZ_64K		(5<<0) /* Queue Size */
#define HARRIER_MICT_QSZ_128K		(6<<0) /* Queue Size */
#define HARRIER_MICT_QSZ_256K		(7<<0) /* Queue Size */


/* HARRIER_MP_I2O_QUEUEBASE_REG   (MIQB) XCSR+$2E4 */

#define HARRIER_MIQB_QBA_MASK		(0xfff<<20) /* Queue Base Addr Mask */


/*
 * HARRIER_PHB_VENDORID_REG    (VENI) XCSR+$300
 * HARRIER_PHB_DEVICEID_REG    (DEVI) XCSR+$302
 */

#define HARRIER_VENI_MASK		(0xffff<<16)	/* vendor ID */
#define HARRIER_DEVI_MASK		(0xffff<<0)	/* device ID */


/* HARRIER_PHB_COMMAND_REG     (CMMD) XCSR+$304 */

#define HARRIER_CMMD_MASK		(0xffff<<16)	/* CMMD MASK */

#define HARRIER_CMMD_PERR		(1<<14)	/* PCI parity error check */
#define HARRIER_CMMD_MTSR		(1<<10)	/* PCI bus master enable */
#define HARRIER_CMMD_MEMSP		(1<<9)	/* PCI memory space enable */
#define HARRIER_CMMD_IOSP		(1<<8)	/* I/O Space Enable */
#define HARRIER_CMMD_SERR		(1<<0)	/* enable SERR_ */



/* HARRIER_PHB_STATUS_REG    (STAT) XCSR+$306 */

#define HARRIER_STAT_MASK		(0xffff<<0)	/* STAT MASK */

#define HARRIER_STAT_FAST		(1<<15)	/* fast back-to-back capable */
#define HARRIER_STAT_P66M		(1<<13)	/* PCI bus 66Mhz capable */
#define HARRIER_STAT_RCVPE		(1<<7)	/* parity error detected */
#define HARRIER_STAT_SIGSE		(1<<6)	/* signaled system error */
#define HARRIER_STAT_RCVMA		(1<<5)	/* received master abort */
#define HARRIER_STAT_RCVTA		(1<<4)	/* received target abort */
#define HARRIER_STAT_SIGTA		(1<<3)	/* signalled target abort */
#define HARRIER_STAT_SELTIM1		(1<<2)	/* DEVSEL timing field */
#define HARRIER_STAT_SELTIM0		(1<<1)	/* DEVSEL timing field */
#define HARRIER_STAT_DPAR		(1<<0)	/* data parity error detected */


/* HARRIER_PHB_REVISIONANDCLASS_REG (REVI)	XCSR+$308 */

#define HARRIER_REVI_MASK		(0xff<<24)	/* REVI Mask */
#define HARRIER_PRGIF_MASK		(0xff<<16)	/* PRGIF Mask */
#define HARRIER_SUBCL_MASK		(0xff<<8)	/* SUBCL Mask */
#define HARRIER_CLASS_MASK		(0xff<<0)	/* CLASS Mask */


/*
 * HARRIER_MSG_PASSING_REGGROUPBASEADDR_REG (MPBAR) XCSR+$310
 *
 *	NOTE:	Use the PCI Config Space Header Bit Definitions (PCFS)
 *		because the PowerPC Bus point of view fragments the
 *		"BASE" field into two separate fields.  However, issuing
 *		PCI config cycles is not desireable.  Therefore, it is
 *		recommended that the corresponding XCSR register be
 *		accessed, but the data needs to be BYTE SWAPPED after
 *		reads and before writes so that the PCFS definitions can
 *		be applied.
 */

/*
 * HARRIER_INBOUND_TRANSLATION_BASE_ADDRESS_0 (ITBAR0) XCSR+$314
 * HARRIER_INBOUND_TRANSLATION_BASE_ADDRESS_1 (ITBAR1) XCSR+$318
 * HARRIER_INBOUND_TRANSLATION_BASE_ADDRESS_2 (ITBAR2) XCSR+$31c
 * HARRIER_INBOUND_TRANSLATION_BASE_ADDRESS_3 (ITBAR3) XCSR+$320
 *
 *	NOTE:	Use the PCI Config Space Header Bit Definitions (PCFS)
 *		because the PowerPC Bus point of view fragments the
 *		"BASE" field into two separate fields.  However, issuing
 *		PCI config cycles is not desireable.  Therefore, it is
 *		recommended that the corresponding XCSR register be
 *		accessed, but the data needs to be BYTE SWAPPED after
 *		reads and before writes so that the PCFS definitions can
 *		be applied.
 */


/*
 * HARRIER_SUBSYSTEM_ID_REG	  (SUBV)  XCSR+$32C
 * HARRIER_SUBSYSTEM_VENDORID_REG (SUBI)  XCSR+$32E
 */

#define HARRIER_SUBV_MASK		(0xffff<<16)	/* SUBV Mask */
#define HARRIER_SUBI_MASK		(0xffff<<0)	/* SUBI Mask */


/*
 * HARRIER_INTERRUPT_LINE_REG  (INTL)	   XCSR+$33C
 * HARRIER_INTERRUPT_PIN_REG   (INTP)	   XCSR+$33D
 * HARRIER_MINIMUM_GRANT_REG   (MNGN)	   XCSR+$33E
 * HARRIER_MAXIMUM_LATENCY_REG (MXLA)	   XCSR+$33F
 */

#define HARRIER_INTL_MASK		(0xff<<24)	/* INTL Mask */
#define HARRIER_INTP_MASK		(0xff<<16)	/* INTP Mask */
#define HARRIER_MNGN_MASK		(0xff<<8)	/* MNGN Mask */
#define HARRIER_MXLA_MASK		(0xff<<0)	/* MXLA Mask */

#define HARRIER_INTP_1                  (1 << 16)	/* INTP = 1 */


/* HARRIER_MSG_PASSINGATTR_REG	(MPAT) XCSR+$344 */

#define HARRIER_MPAT_ENA		(1<<31)	/* enable MP */
#define HARRIER_MPAT_MEM		(1<<30)	/* located in PCI memory */
#define HARRIER_MPAT_WPE		(1<<29)	/* write-post enable */
#define HARRIER_MPAT_RAE		(1<<28)	/* read ahead enable */
#define HARRIER_MPAT_GBL		(1<<8)	/* assert GBL_ */


/*
 * HARRIER_INBOUND_TRANSLATION_SIZE_0_REG  (ITAT0) XCSR+$348
 * HARRIER_INBOUND_TRANSLATION_SIZE_1_REG  (ITAT1) XCSR+$350
 * HARRIER_INBOUND_TRANSLATION_SIZE_2_REG  (ITAT2) XCSR+$358
 * HARRIER_INBOUND_TRANSLATION_SIZE_3_REG  (ITAT3) XCSR+$360
 */

#define HARRIER_ITSZX_MASK		(0xff<<24) /* ITSZ Mask */
#define HARRIER_ITOFX_MASK		(0xffff<<0) /* ITOF Mask */

#define HARRIER_ITAT_ENA		(1<<31)	/* read & write enable */
#define HARRIER_ITAT_MEM		(1<<30)	/* map to PCI memory space */
#define HARRIER_ITAT_WPE		(1<<29)	/* write pos