harrier.h

vxworks的bsp开发包(基于POWERPC的PRPMC800)

/* HARRIER_MPIC_BASEADDRESS_REG     (MBAR) XCSR+$0E0 */

#define	HARRIER_MBAR_MBA_MASK		0xFFFC0000 /* MPIC base address mask */
#define HARRIER_MBAR_ENA		(1<<16)	/* enable XMPI reg visibility */



/* HARRIER_MPIC_CONTROL_STATUS_REG    (MCSR) XCSR+$0E4 */

#define HARRIER_MCSR_OPI	       (1<<6)  /* OPIC interrupt */



/* HARRIER_SDRAM_GENERAL_CONTROL_REG  (SDGC) XCSR+$100 */

#define HARRIER_SDGC_MXRR               (3<<12) /* Multiply Refresh Rate */
#define HARRIER_SDGC_DREF		(1<<26)	/* disable refresh */
#define HARRIER_SDGC_DERC		(1<<25)	/* disable error correction */
#define HARRIER_SDGC_RWCB		(1<<24)	/* read/write chk bits enable */
#define HARRIER_SDGC_ENRV		(1<<23)	/* enable reset vector */
#define HARRIER_SDGC_SWVT		(1<<19)	/* swap vector table */


/* HARRIER_SDRAM_TIMING_CONTROL_REG   (SDTC) XCSR+$104 */

#define HARRIER_SDTC_CL3		(1<<28)	/* SDRAM CAS latency */
#define HARRIER_SDTC_CL3_SHIFT	28	    /* SDRAM CAS latency shift */
#define HARRIER_SDTC_CL3_MASK	0x01	    /* SDRAM CAS latency mask  */

#define HARRIER_SDTC_TRC8		(0<<24)	/* SDRAM tRC 8 CLKS */
#define HARRIER_SDTC_TRC9		(1<<24)	/* SDRAM tRC 9 CLKS */
#define HARRIER_SDTC_TRC10		(2<<24)	/* SDRAM tRC 10 CLKS */
#define HARRIER_SDTC_TRC11		(3<<24)	/* SDRAM tRC 11 CLKS */
#define HARRIER_SDTC_TRC6		(6<<24)	/* SDRAM tRC 6 CLKS */
#define HARRIER_SDTC_TRC7		(7<<24)	/* SDRAM tRC 7 CLKS */

#define HARRIER_SDTC_TRC_SHIFT  24      /* TRC bit position */
#define HARRIER_SDTC_TRC_MASK   0x07    /* TRC bits position mask */

#define HARRIER_SDTC_TRAS4		(0<<20)	/* SDRAM tRAS 4CLKS */
#define HARRIER_SDTC_TRAS5		(1<<20)	/* SDRAM tRAS 5CLKS */
#define HARRIER_SDTC_TRAS6		(2<<20)	/* SDRAM tRAS 6CLKS */
#define HARRIER_SDTC_TRAS7		(3<<20)	/* SDRAM tRAS 7CLKS */

#define HARRIER_SDTC_TRAS_SHIFT 20      /* TRAS bit position */
#define HARRIER_SDTC_TRAS_MASK  0x03    /* TRAS bit position mask */

#define HARRIER_SDTC_WDPL		(1<<17)	/* wait on tDPL*/
#define HARRIER_SDTC_WDPL_SHIFT 17      /* wdpl bit position */

#define HARRIER_SDTC_TDP1		(0<<16)	/* SDRAM tDP 1 CLKS */
#define HARRIER_SDTC_TDP2		(1<<16)	/* SDRAM tDP 2 CLKS */

#define HARRIER_SDTC_TDP_SHIFT_MASK  0x01    /* tdp bit position mask */
#define HARRIER_SDTC_TDP_SHIFT  16      /* tdp bit position */

#define HARRIER_SDTC_TRP2		(0<<12)	/* SDRAM tRP 2 CLKS */
#define HARRIER_SDTC_TRP3		(1<<12)	/* SDRAM tRP 3 CLKS */

#define HARRIER_SDTC_TRP_SHIFT  12           /* trp bit position */
#define HARRIER_SDTC_TRP_SHIFT_MASK  0x01    /* trp bit position mask */

#define HARRIER_SDTC_TRCD2		(0<<8)	/* SDRAM tRCD 2 CLKS */
#define HARRIER_SDTC_TRCD3		(1<<8)	/* SDRAM tRCD 3 CLKS */

#define HARRIER_SDTC_TRCD_SHIFT	8	      /* tRCD bit position */
#define HARRIER_SDTC_TRCD_SHIFT_MASK  0x01    /* trcd bit position mask */

#define HARRIER_SDTC_SDER		(1<<0)	/* swap vector table */


/*
 * HARRIER_REG_SDRAM_BLOCK_ADDRESSING_A (SDBAA) XCSR+($110)
 * HARRIER_REG_SDRAM_BLOCK_ADDRESSING_B (SDBAB) XCSR+($114)
 * HARRIER_REG_SDRAM_BLOCK_ADDRESSING_C (SDBAC) XCSR+($118)
 * HARRIER_REG_SDRAM_BLOCK_ADDRESSING_D (SDBAD) XCSR+($11C)
 * HARRIER_REG_SDRAM_BLOCK_ADDRESSING_E (SDBAE) XCSR+($120)
 * HARRIER_REG_SDRAM_BLOCK_ADDRESSING_F (SDBAF) XCSR+($124)
 * HARRIER_REG_SDRAM_BLOCK_ADDRESSING_G (SDBAG) XCSR+($128)
 * HARRIER_REG_SDRAM_BLOCK_ADDRESSING_H (SDBAH) XCSR+($12C)
 */

#define HARRIER_SDBA_BASE_MASK		0xFF000000 /* SDRAM base address mask */
#define HARRIER_SDBA_BASE_SHIFT		24         /* SDRAM base address shift */

#define HARRIER_SDBA_SIZE_MASK		(15<<16)   /* SDRAM block size mask */
#define HARRIER_SDBA_SIZE_SHIFT		16         /* SDRAM block size shift */

#define HARRIER_SDBA_SIZE_0           (0<<16)  /* bank size 0MB            */
#define HARRIER_SDBA_SIZE_32_4MX16    (1<<16)  /* bank size 32MB(4Mx16)    */
#define HARRIER_SDBA_SIZE_64_8MX8     (2<<16)  /* bank size 64MB(8Mx8)     */
#define HARRIER_SDBA_SIZE_64_8MX16    (3<<16)  /* bank size 64MB(8Mx16)    */
#define HARRIER_SDBA_SIZE_128_16MX4   (4<<16)  /* bank size 128MB(16Mx4)   */
#define HARRIER_SDBA_SIZE_128_16MX8   (5<<16)  /* bank size 128MB(16Mx8)   */
#define HARRIER_SDBA_SIZE_128_16MX16  (6<<16)  /* bank size 128MB(16Mx16)  */
#define HARRIER_SDBA_SIZE_256_32MX4   (7<<16)  /* bank size 256MB(32Mx4)   */
#define HARRIER_SDBA_SIZE_256_32MX8   (8<<16)  /* bank size 256MB(32Mx8)   */
#define HARRIER_SDBA_SIZE_256_32MX16  (9<<16)  /* bank size 256MB(32Mx8)   */
#define HARRIER_SDBA_SIZE_512_64MX4   (10<<16) /* bank size 512MB(64Mx4)   */
#define HARRIER_SDBA_SIZE_512_64MX8   (11<<16) /* bank size 512MB(64Mx8)   */
#define HARRIER_SDBA_SIZE_512_64MX16  (12<<16) /* bank size 512MB(64MX16)  */
#define HARRIER_SDBA_SIZE_1024_128MX4 (13<<16) /* bank size 1024MB(128MX4) */
#define HARRIER_SDBA_SIZE_1024_128MX8 (14<<16) /* bank size 1024MB(128MX8) */
#define HARRIER_SDBA_SIZE_2048_256MX4 (15<<16) /* bank size 2048MB(256MX4) */

#define HARRIER_SDBA_ENB		(1<<8)	/* SDRAM block enable */



/* HARRIER_SDRAM_SCRUB_CONTROL_REG     (SDSC) XCSR+$130 */

#define HARRIER_SDSC_SCWE		(1<<15)	/* scrub write enable */
#define HARRIER_SDSC_SCCNT_MASK		(3<<8)	/* scrub counter */
#define HARRIER_SDSC_SCPA_MASK		(255<<0) /* scrub prescalar adjust */


/*
 * HARRIER_SDRAM_SBE_SYNDROME_REG    (ESYN)  $140
 * HARRIER_SDRAM_SBE_SCRUBBLOCK_REG  (ESB)   $141
 * HARRIER_SDRAM_SBE_COUNT_REG	     (SECNT) $142
 */

#define HARRIER_SDSES_EOS		(1<<3)	/* error on scrub */
#define HARRIER_SDSES_ESB_MASK		(7<<0)	/* error scrub block mask */
#define HARRIER_SDSES_ESB_A		(0<<0)	/* error scrub block A */
#define HARRIER_SDSES_ESB_B		(1<<0)	/* error scrub block B */
#define HARRIER_SDSES_ESB_C		(2<<0)	/* error scrub block C */
#define HARRIER_SDSES_ESB_D		(3<<0)	/* error scrub block D */
#define HARRIER_SDSES_ESB_E		(4<<0)	/* error scrub block E */
#define HARRIER_SDSES_ESB_F		(5<<0)	/* error scrub block F */
#define HARRIER_SDSES_ESB_G		(6<<0)	/* error scrub block G */
#define HARRIER_SDSES_ESB_H		(7<<0)	/* error scrub block H */



/* HARRIER_SDRAM_MBE_SCRUBBLOCK_REG  (ESB) $149 */

#define HARRIER_SDMES_ESB_MASK		(7<<0)	/* error scrub block mask */
#define HARRIER_SDMES_ESB_A		(0<<0)	/* error scrub block A */
#define HARRIER_SDMES_ESB_B		(1<<0)	/* error scrub block B */
#define HARRIER_SDMES_ESB_C		(2<<0)	/* error scrub block C */
#define HARRIER_SDMES_ESB_D		(3<<0)	/* error scrub block D */
#define HARRIER_SDMES_ESB_E		(4<<0)	/* error scrub block E */
#define HARRIER_SDMES_ESB_F		(5<<0)	/* error scrub block F */
#define HARRIER_SDMES_ESB_G		(6<<0)	/* error scrub block G */
#define HARRIER_SDMES_ESB_H		(7<<0)	/* error scrub block H */


/*
 * HARRIER_XPORT0_ATTR_REG	   (XPAT0) XCSR+$154
 * HARRIER_XPORT1_ATTR_REG	   (XPAT1) XCSR+$15C
 * HARRIER_XPORT2_ATTR_REG	   (XPAT2) XCSR+$164
 * HARRIER_XPORT3_ATTR_REG	   (XPAT3) XCSR+$16C
 */

#define HARRIER_XPAT_REN		(1<<31)	/* read enable */
#define HARRIER_XPAT_WEN		(1<<30)	/* write enable */
#define HARRIER_XPAT_BAM		(1<<29)	/* basic mode */
#define HARRIER_XPAT_RVEN		(1<<27)	/* reset vector enable */

#define HARRIER_XPAT_DW_MASK		(3<<24)	/* data width mask */
#define HARRIER_XPAT_DW_8BITS		(0<<24)	/* data width 8 bits */
#define HARRIER_XPAT_DW_16BITS		(1<<24)	/* data width 16 bits */
#define HARRIER_XPAT_DW_32BITS		(2<<24)	/* data width 32 bits */
#define HARRIER_XPAT_DW_16HAWK		(3<<24)	/* 16 bits Hawk compatible */
#define HARRIER_XPAT_AD_MASK		(15<<20) /* access delay */
#define HARRIER_XPAT_BLE_MASK		(3<<16)	/* burst length mask */
#define HARRIER_XPAT_BLE_4BYTES		(0<<16)	/* burst length 4 bytes */
#define HARRIER_XPAT_BLE_8BYTES		(1<<16)	/* burst length 8 bytes */
#define HARRIER_XPAT_BLE_16BYTES	(2<<16)	/* burst length 16 bytes */
#define HARRIER_XPAT_BLE_32BYTES	(3<<16)	/* burst length 32 bytes */

#define HARRIER_XPAT_BREN		(1<<12)	/* burst read enable */
#define HARRIER_XPAT_BRD_MASK		(7<<8)	/* burst read delay mask */

#define HARRIER_XPAT_BWEN		(1<<4)	/* burst write enable */
#define HARRIER_XPAT_BWD_MASK		(7<<0)	/* burst write delay mask */

#define HARRIER_I2CO_STA		(1<<3)	/* i2c mstr controller start */
#define HARRIER_I2CO_STP		(1<<2)	/* i2c mstr controller stop */
#define HARRIER_I2CO_ACKO		(1<<1)	/* i2c mstr controller ack */
#define HARRIER_I2CO_ENA		(1<<0)	/* i2c mstr interface enable */


#define HARRIER_I2ST_DIN		(1<<3)	/* data in from i2c slave */
#define HARRIER_I2ST_ERR		(1<<2)	/* error: STA & STP both set */
#define HARRIER_I2ST_ACKI		(1<<1)	/* acknowledge in slave */
#define HARRIER_I2ST_CMP		(1<<0)	/* i2c operation complete */



/* HARRIER_BRIDGE_PCI_CONTROLSTATUS_REG   (BPCS) XCSR+$200 */

#define HARRIER_BPCS_OFBR		(1<<15)	/* outbound flush before read */
#define HARRIER_BPCS_DLR		(1<<14)	/* ignore latency requirement */
#define HARRIER_BPCS_HIL		(1<<13)	/* host brdg initial latency */

#define HARRIER_BPCS_PIM_MASK		(3<<8)	/* PCI interrupt mappin mask */
#define HARRIER_BPCS_PIM_INTA_		(0<<8)	/* map PCI interrupt to INTA_ */
#define HARRIER_BPCS_PIM_INTB_		(1<<8)	/* map PCI interrupt to INTB_ */
#define HARRIER_BPCS_PIM_INTC_		(2<<8)	/* map PCI interrupt to INTC_ */
#define HARRIER_BPCS_PIM_INTD_		(3<<8)	/* map PCI interrupt to INTD_ */

#define HARRIER_BPCS_CSM		(1<<5)	/* config space mask */
#define HARRIER_BPCS_CSH		(1<<4)	/* config space hold off */
#define HARRIER_BPCS_P64		(1<<0)	/* PCI 64-bit bus */

#define HARRIER_BPCS_XCSR_CSH	(1<<20)

/* HARRIER_BRIDGE_PPC_CONTROLSTATUS_REG   (BXCS) XCSR+$204 */

#define HARRIER_BXCS_IFBR		(1<<15)	/* inbound flush before read */
#define HARRIER_BXCS_BHG		(1<<14)	/* Harrier bus hog mode */
#define HARRIER_BXCS_RSF		(1<<13)	/* read-ahead sync flush */
#define HARRIER_BXCS_SSF		(1<<12)	/* store-gathter sync flush */

#define HARRIER_BXCS_RBT_MASK		(3<<10)	/* read-ahead backup tmr msk */
#define HARRIER_BXCS_RBT_32CLKS		(0<<10)	/* time out: 32 clocks */
#define HARRIER_BXCS_RBT_64CLKS		(1<<10)	/* time out: 64 clocks */
#define HARRIER_BXCS_RBT_256CLKS	(2<<10)	/* time out: 256 clocks */
#define HARRIER_BXCS_RBT_DISABLED	(3<<10)	/* time out: disabled */

#define HARRIER_BXCS_SBT_MASK		(3<<8)	/* store-gthr backup tmr msk */
#define HARRIER_BXCS_SBT_32CLKS		(0<<8)	/* time out: 32 clocks */
#define HARRIER_BXCS_SBT_64CLKS		(1<<8)	/* time out: 64 clocks */
#define HARRIER_BXCS_SBT_256CLKS	(2<<8)	/* time out: 256 clocks */
#define HARRIER_BXCS_SBT_DISABLED	(3<<8)	/* time out: disabled */

#define HARRIER_BXCS_P1H		(1<<5)	/* processor 1 holdoff */
#define HARRIER_BXCS_P0H		(1<<4)	/* processor 0 holdoff */
#define HARRIER_BXCS_CSE		(1<<3)	/* enable copy-back snarfing */

#define HARRIER_OTOF_RXT		(1<<10)	/* read any threshold */

#define HARRIER_OTOF_RXS_MASK		(3<<8)	/* read any size mask */
#define HARRIER_OTOF_RXS_64BYTES	(0<<8)	/* read size 64 bytes */
#define HARRIER_OTOF_RXS_128BYTES	(1<<8)	/* read size 128 bytes */
#define HARRIER_OTOF_RXS_256BYTES	(2<<8)	/* read size 256 bytes */

#define HARRIER_OTOF_ENA		(1<<7)	/* enable oubound translation */
#define HARRIER_OTOF_WPE		(1<<4)	/* enable write posting */
#define HARRIER_OTOF_SGE		(1<<3)	/* enable store-gather */
#define HARRIER_OTOF_RAE		(1<<2)	/* enable read-ahead */
#define HARRIER_OTOF_MEM		(1<<1)	/* memory I/O */
#define HARRIER_OTOF_IOM		(1<<0)	/* I/O mode */



/* HARRIER_PASSIVE_SLAVEATTRIBUTE_REG  (PSAT) XCSR+$24F */

#define HARRIER_PSAT_ENA		(1<<7)	/* enable passive translation */
#define HARRIER_PSAT_SGE		(1<<3)	/* enable store-gather */



/* HARRIER_DMA_CONTROL_REG    (DCTL) XCSR+$250 */

#define HARRIER_DCTL_ABT		(1<<27)	/* DMA transaction abort */
#define HARRIER_DCTL_PAU		(1<<26)	/* DMA transaction pause */
#define HARRIER_DCTL_DGO		(1<<25)	/* DMA transaction start */

#define HARRIER_DCTL_MOD		(1<<23)	/* DMA transaction mode */

#define HARRIER_DCTL_XTH_MASK		(3<<20)	/* PowerPC throttle mask */
#define HARRIER_DCTL_XTH_256BYTES	(0<<20)	/* transfer size: 256 bytes */
#define HARRIER_DCTL_XTH_512BYTES	(1<<20)	/* transfer size: 512 bytes */
#define HARRIER_DCTL_XTH_1024BYTES	(2<<20)	/* transfer size: 1024 bytes */
#define HARRIER_DCTL_XTH_CONTINUOUS	(3<<20)	/* continous transfer */

#define HARRIER_DCTL_PBT_MASK		(7<<16)	/* PCI back-off timer mask */
#define HARRIER_DCTL_PBT_0_CLKS		(0<<16)	/* PCI back-off 0 clocks */
#define HARRIER_DCTL_PBT_32_CLKS	(1<<16)	/* PCI back-off 32 clocks */
#define HARRIER_DCTL_PBT_64_CLKS	(2<<16)	/* PCI back-off 64 clocks */
#define HARRIER_DCTL_PBT_128_CLKS	(3<<16)	/* PCI back-off 128 clocks */
#define HARRIER_DCTL_PBT_256_CLKS	(4<<16)	/* PCI back-off 256 clocks */
#define HARRIER_DCTL_PBT_512_CLKS	(5<<16)	/* PCI back-off 512 clocks */
#define HARRIER_DCTL_PBT_1024_CLKS	(6<<16)	/* PCI back-off 1024 clocks */
#define HARRIER_DCTL_PBT_2048_CLKS	(7<<16)	/* PCI back-off 2048 clocks */

#define HARRIER_DCTL_CSE		(1<<11)	/* copy-back snarfing enable */
#define HARRIER_DCTL_CRI		(1<<10)	/* C-line invalidate - LLD RD */

#define HARRIER_DCTL_GBL		(1<<8)	/* GBL_ pin for PPC LLD reads */


/* HARRIER_REGISTER_DMA_STATUS (DSTA) XCSR+$254 */

#define HARRIER_DSTA_SMA		(1<<15)	/* DMA Signalled Master Abort */
#define HARRIER_DSTA_RTA		(1<<14)	/* DMA Received Target Abort */
#define HARRIER_DSTA_MRC		(1<<13)	/* DMA Max Retry Count error */
#define HARRIER_DSTA_XBT		(1<<12)	/* DMA PPC Bus timeout */
#define HARRIER_DSTA_ABT		(1<<11)	/* DMA abort */
#define HARRIER_DSTA_PAU		(1<<10)	/* DMA pause */
#define HARRIER_DSTA_DON		(1<<9)	/* DMA done */
#define HARRIER_DSTA_BSY		(1<<8)	/* DMA busy */