harrier.h

vxworks的bsp开发包(基于POWERPC的PRPMC800)

#define HARRIER_FEMA_MIP	    (1<<11) /* mask MIP exception */
#define HARRIER_FEMA_UA0	    (1<<10) /* mask UART #0 exception */
#define HARRIER_FEMA_UA1	    (1<<9)  /* mask UART #1 exception */
#define HARRIER_FEMA_ABT	    (1<<8)  /* mask abort exception */


/* HARRIER_EXCEPTION_CLEAR_REG	   (FECL) XCSR+$04C */

#define HARRIER_FECL_DMA	    (1<<15) /* clear DMA exception */
#define HARRIER_FECL_IMM0	    (1<<13) /* clear IB msg passing 0 exc */
#define HARRIER_FECL_IMM1	    (1<<12) /* clear IB msg passing 1 exc */
#define HARRIER_FECL_ABT	    (1<<8)  /* clear abort exception */



/* HARRIER_ERROR_EXCEPTION_ENABLE_REG	 (EEEN) XCSR+$050 */

#define HARRIER_EEEN_PMA	    (1<<31) /* enable PCI mstr abort exc */
#define HARRIER_EEEN_PTA	    (1<<30) /* enable PCI trgt abort exc */
#define HARRIER_EEEN_PAP	    (1<<29) /* enable PCI addr parity exc */
#define HARRIER_EEEN_PDP	    (1<<28) /* enable PCI data parity exc */
#define HARRIER_EEEN_PDT	    (1<<27) /* enable PCI bus delay exc */
#define HARRIER_EEEN_PSE	    (1<<26) /* enable PCI SERR exception */
#define HARRIER_EEEN_PPE	    (1<<25) /* enable PCI PERR exception */
#define HARRIER_EEEN_SSE	    (1<<23) /* enable SDRAM SBE exception */
#define HARRIER_EEEN_SSC	    (1<<22) /* enable SBE cnt overflow ex */
#define HARRIER_EEEN_SMX	    (1<<21) /* enable SDRAM MBE exception */
#define HARRIER_EEEN_SMS	    (1<<20) /* enable SDRAM MBE scrub exc */
#define HARRIER_EEEN_XBT	    (1<<15) /* enable PPC bus timeout exc */
#define HARRIER_EEEN_XAP	    (1<<14) /* enable PPC addr parity exc */
#define HARRIER_EEEN_XDP	    (1<<13) /* enable PPC data parity exc */
#define HARRIER_EEEN_XDT	    (1<<12) /* enable PPC del timeout exc */



/* HARRIER_ERROR_EXCEPTION_STATUS_REG	 (EEST) XCSR+$054 */

#define HARRIER_EEST_PMA	    (1<<31) /* PCI master abort exc */
#define HARRIER_EEST_PTA	    (1<<30) /* PCI target abort exc */
#define HARRIER_EEST_PAP	    (1<<29) /* PCI address parity exc */
#define HARRIER_EEST_PDP	    (1<<28) /* PCI data parity exc */
#define HARRIER_EEST_PDT	    (1<<27) /* PCI bus delay exc */
#define HARRIER_EEST_PSE	    (1<<26) /* PCI SERR exception */
#define HARRIER_EEST_PPE	    (1<<25) /* PCI PERR exception */
#define HARRIER_EEST_POF	    (1<<24) /* PCI error overflow */
#define HARRIER_EEST_SSE	    (1<<23) /* SDRAM SBE exception */
#define HARRIER_EEST_SSC	    (1<<22) /* SDRAM SBE cnt overflow exc */
#define HARRIER_EEST_SMX	    (1<<21) /* SDRAM MBE exception */
#define HARRIER_EEST_SMS	    (1<<20) /* SDRAM MBE scrub exception */
#define HARRIER_EEST_SSOF	    (1<<17) /* SDRAM SBE overflow */
#define HARRIER_EEST_SMOF	    (1<<16) /* SDRAM MBE overflow */
#define HARRIER_EEST_XBT	    (1<<15) /* PPC bus timeout exc */
#define HARRIER_EEST_XAP	    (1<<14) /* PPC addr parity exc */
#define HARRIER_EEST_XDP	    (1<<13) /* PPC data parity exc */
#define HARRIER_EEST_XDT	    (1<<12) /* PPC del timeout exc */
#define HARRIER_EEST_XOF	    (1<<8)  /* PPC error overflow exc */


/* HARRIER_ERROR_EXCEPTION_CLEAR_REG	 (EECL) XCSR+$058 */

#define HARRIER_EECL_PMA	    (1<<31) /* clear PCI master abort exc */
#define HARRIER_EECL_PTA	    (1<<30) /* clear PCI target abort exc */
#define HARRIER_EECL_PAP	    (1<<29) /* clear PCI addr parity exc */
#define HARRIER_EECL_PDP	    (1<<28) /* clear PCI data parity exc */
#define HARRIER_EECL_PDT	    (1<<27) /* clear PCI bus delay exc */
#define HARRIER_EECL_PSE	    (1<<26) /* clear PCI SERR exception */
#define HARRIER_EECL_PPE	    (1<<25) /* clear PCI PERR exception */
#define HARRIER_EECL_POF	    (1<<24) /* clear PCI error overflow */
#define HARRIER_EECL_SSE	    (1<<23) /* clear SDRAM SBE exception */
#define HARRIER_EECL_SSC	    (1<<22) /* clear SBE cnt overflow exc */
#define HARRIER_EECL_SMX	    (1<<21) /* clear SDRAM MBE exception */
#define HARRIER_EECL_SMS	    (1<<20) /* clear SDRAM MBE scrub exc */
#define HARRIER_EECL_SSOF	    (1<<17) /* clear SBE overflow exc */
#define HARRIER_EECL_SMOF	    (1<<16) /* clear MBE overflow exc */
#define HARRIER_EECL_XBT	    (1<<15) /* clear PPC bus timeout exc */
#define HARRIER_EECL_XAP	    (1<<14) /* clear PPC addr parity exc */
#define HARRIER_EECL_XDP	    (1<<13) /* clear PPC data parity exc */
#define HARRIER_EECL_XDT	    (1<<12) /* clear PPC del timeout exc */
#define HARRIER_EECL_XOF	    (1<<8)  /* clear PPC err overflow exc */



/* HARRIER_ERROR_EXCEPTION_INT_ENABLE_REG   (EEINT) XCSR+$05C */

#define HARRIER_EEINT_PMA	    (1<<31) /* enable PCI mstr abort int */
#define HARRIER_EEINT_PTA	    (1<<30) /* enable PCI trgt abort int */
#define HARRIER_EEINT_PAP	    (1<<29) /* enable PCI addr parity int */
#define HARRIER_EEINT_PDP	    (1<<28) /* enable PCI data parity int */
#define HARRIER_EEINT_PDT	    (1<<27) /* enable PCI bus delay int */
#define HARRIER_EEINT_PSE	    (1<<26) /* enable PCI SERR interrupt */
#define HARRIER_EEINT_PPE	    (1<<25) /* enable PCI PERR interrupt */
#define HARRIER_EEINT_SSE	    (1<<23) /* enable SDRAM SBE interrupt */
#define HARRIER_EEINT_SSC	    (1<<22) /* enable SBE cnt overflo int */
#define HARRIER_EEINT_SMX	    (1<<21) /* enable SDRAM MBE interrupt */
#define HARRIER_EEINT_SMS	    (1<<20) /* enable SDRAM MBE scrub int */
#define HARRIER_EEINT_XBT	    (1<<15) /* enable PPC bus timeout int */
#define HARRIER_EEINT_XAP	    (1<<14) /* enable PPC addr parity int */
#define HARRIER_EEINT_XDP	    (1<<13) /* enable PPC data parity int */
#define HARRIER_EEINT_XDT	    (1<<12) /* enable PPC del timeout int */


/*
 * HARRIER_ERROR_EXCMACHINECHECK0_ENABLE (EEMCKx)
 * HARRIER_ERROR_EXCMACHINECHECK1_ENABLE (EEMCKx)
 * XCSR+$060 & XCSR+$064
 */

#define HARRIER_EEMCK_PMA	    (1<<31) /* enable PCI mstr abort MC */
#define HARRIER_EEMCK_PTA	    (1<<30) /* enable PCI trgt abort MC */
#define HARRIER_EEMCK_PAP	    (1<<29) /* enable PCI addr parity MC */
#define HARRIER_EEMCK_PDP	    (1<<28) /* enable PCI data parity MC */
#define HARRIER_EEMCK_PDT	    (1<<27) /* enable PCI bus delay MC */
#define HARRIER_EEMCK_PSE	    (1<<26) /* enable PCI SERR MC */
#define HARRIER_EEMCK_PPE	    (1<<25) /* enable PCI PERR MC */
#define HARRIER_EEMCK_SSE	    (1<<23) /* enable SDRAM SBE MC */
#define HARRIER_EEMCK_SSC	    (1<<22) /* enable SBE cnt overflow MC */
#define HARRIER_EEMCK_SMX	    (1<<21) /* enable SDRAM MBE MC */
#define HARRIER_EEMCK_SMS	    (1<<20) /* enable SDRAM MBE scrub MC */
#define HARRIER_EEMCK_XBT	    (1<<15) /* enable PPC bus timeout MC */
#define HARRIER_EEMCK_XAP	    (1<<14) /* enable PPC addr parity MC */
#define HARRIER_EEMCK_XDP	    (1<<13) /* enable PPC data parity MC */
#define HARRIER_EEMCK_XDT	    (1<<12) /* enable PPC del timeout MC */


/* HARRIER_ERR_DIAGS_PPCATTRIBUTE_REG  (EXAT) XCSR+$074 */

#define HARRIER_EXAT_MID_MASK		(3<<28)	/* PPC bus master ID mask */
#define HARRIER_EXAT_TBST		(1<<24)	/* transfer burst */
#define HARRIER_EXAT_TSIZ_MASK		(7<<21)	/* transfer size mask */
#define HARRIER_EXAT_TT_MASK		(31<<16) /* transfer type mask */


/* HARRIER_ERR_DIAGS_PCIATTRIBUTE_REG	 (EPAT) XCSR+$07C */

#define HARRIER_EPAT_MID_MASK		(15<<28) /* PCI command mask */


/*
 * HARRIER_REGISTER_WATCHDOG_TIMER_CONTROL (WTxC)
 * XCSR+$080 & XCSR+$088
 */

#define HARRIER_WTxC_KEY1		(0x55<<24) /* key pattern #1 */
#define HARRIER_WTxC_KEY2		(0xAA<<24) /* key pattern #2 */
#define HARRIER_WTxC_ENA		(1<<23)	/* watchdog timer enable */
#define HARRIER_WTxC_ARM		(1<<22)	/* register armed for write */

#define HARRIER_WTxC_RES_MASK		(15<<16) /* watchdog timer resolution */
#define HARRIER_WTxC_RES_1U		(0<<16)	/* 1 usec resolution */
#define HARRIER_WTxC_RES_2U		(1<<16)	/* 2 usec resolution */
#define HARRIER_WTxC_RES_4U		(2<<16)	/* 4 usec resolution */
#define HARRIER_WTxC_RES_8U		(3<<16)	/* 8 usec resolution */
#define HARRIER_WTxC_RES_16U		(4<<16)	/* 16 usec resolution */
#define HARRIER_WTxC_RES_32U		(5<<16)	/* 32 usec resolution */
#define HARRIER_WTxC_RES_64U		(6<<16)	/* 64 usec resolution */
#define HARRIER_WTxC_RES_128U		(7<<16)	/*  usec resolution */
#define HARRIER_WTxC_RES_256U		(8<<16)	/*  usec resolution */
#define HARRIER_WTxC_RES_512U		(9<<16)	/*  usec resolution */
#define HARRIER_WTxC_RES_1024U		(10<<16) /*  usec resolution */
#define HARRIER_WTxC_RES_2048U		(11<<16) /*  usec resolution */
#define HARRIER_WTxC_RES_4096U		(12<<16) /*  usec resolution */
#define HARRIER_WTxC_RES_8192U		(13<<16) /*  usec resolution */
#define HARRIER_WTxC_RES_16384U		(14<<16) /*  usec resolution */
#define HARRIER_WTxC_RES_32768U		(15<<16) /*  usec resolution */



/* HARRIER_PCI_ARBITER_REG  (PARB) XCSR+$090 */

#define HARRIER_PARB_PRI_MASK		(3<<14)	/* PCI arbiter priority mask */
#define HARRIER_PARB_PRI_FIXED		(0<<14)	/* fixed priority */
#define HARRIER_PARB_PRI_ROUNDROBIN	(1<<14) /* round robin prioity */
#define HARRIER_PARB_PRI_MIXED		(2<<14)	/* mixed priority scheme */

#define HARRIER_PARB_PRK_MASK		(15<<10) /* PCI arbiter parking mask */
#define HARRIER_PARB_PRK_LASTMASTER	(0<<10)	/* park on last master */
#define HARRIER_PARB_PRK_PARB6		(1<<10)	/* park on PARB6 */
#define HARRIER_PARB_PRK_PAR5B		(2<<10)	/* park on PARB5 */
#define HARRIER_PARB_PRK_PARB4		(3<<10)	/* park on PARB4 */
#define HARRIER_PARB_PRK_PARB3		(4<<10)	/* park on PARB3 */
#define HARRIER_PARB_PRK_PARB2		(5<<10)	/* park on PARB2 */
#define HARRIER_PARB_PRK_PARB1		(6<<10)	/* park on PARB1 */
#define HARRIER_PARB_PRK_PARB0		(7<<10)	/* park on PARB0 */
#define HARRIER_PARB_PRK_HARRIER	(8<<10)	/* park on Harrier */
#define HARRIER_PARB_PRK_NONE		(15<<10) /* none */
#define HARRIER_PARB_HIE_MASK		(7<<7)	/* PCI arbiter hierarchy */
#define HARRIER_PARB_POL		(1<<0)	/* park on lock */

#define HARRIER_PARB_ENABLE		(1<<0) /* enable arbiter */

/* HARRIER_PPC_ARBITER_REG (XARB) - XCSR+$094 */

#define HARRIER_XARB_PIPE_FBR_NONE	(0<<14) /* None */
#define HARRIER_XARB_PIPE_FBR_FLTA	(2<<14) /* Flatten always */
#define HARRIER_XARB_PIPE_FBR_FLTS	(3<<14) /* Flatten on mstr. switch */

#define HARRIER_XARB_PIPE_FSR_NONE	(0<<12) /* None */
#define HARRIER_XARB_PIPE_FSR_FLTA	(2<<12) /* Flatten always */
#define HARRIER_XARB_PIPE_FSR_FLTS	(3<<12) /* Flatten on mstr. switch */

#define HARRIER_XARB_PIPE_FBW_NONE	(0<<10) /* None */
#define HARRIER_XARB_PIPE_FBW_FLTA	(2<<10) /* Flatten always */
#define HARRIER_XARB_PIPE_FBW_FLTS	(3<<10) /* Flatten on mstr. switch */

#define HARRIER_XARB_PIPE_FSW_NONE	(0<<8)  /* None */
#define HARRIER_XARB_PIPE_FSW_FLTA	(2<<8)  /* Flatten always */
#define HARRIER_XARB_PIPE_FSW_FLTS	(3<<8)  /* Flatten on mstr. switch */

#define HARRIER_XARB_PRK_NONE		(0<<4)	 /* None */
#define HARRIER_XARB_PRK_LASTCPU	(1<<4)	 /* Park on last CPU */
#define HARRIER_XARB_PRK_CPU0		(2<<4)	 /* Park always on CPU0 */
#define HARRIER_XARB_PRK_CPU1		(3<<4)	 /* Park always on CPU1 */

#define HARRIER_XARB_ENABLE		(1<<0)   /* Enable PowerPC Arbiter */

/*
 * HARRIER_UART_x_RTDL_REG  (RTDLx) XCSR+$0C0 & XCSR+$0C8
 * HARRIER_UART_x_IEDH_REG  (IEDHx) XCSR+$0C1 & XCSR+$0C9
 * HARRIER_UART_x_IDFC_REG  (IDFCx) XCSR+$0C2 & XCSR+$0CA
 * HARRIER_UART_x_LCTL_REG  (LCTLx) XCSR+$0C3 & XCSR+$0CB
 */

#define HARRIER_IEDH_EDSSI		(1<<3)	/* enable modem status int */
#define HARRIER_IEDH_ELSI		(1<<2)	/* enable rec line stat int */
#define HARRIER_IEDH_ETBEI		(1<<1)	/* enable xmit hold reg int */
#define HARRIER_IEDH_ERBFI		(1<<0)	/* enable data available int */

#define	HARRIER_IDFC_FENS_MASK		(3<<6)	/* FIFOs enabled status mask */
#define	HARRIER_IDFC_FENS_DISABLED	(0<<6)	/* FIFOs disabled */
#define	HARRIER_IDFC_FENS_ENABLED	(3<<6)	/* FIFOs enabled */
#define	HARRIER_IDFC_IID_MASK		(7<<1)	/* interrupt ID mask */
#define	HARRIER_IDFC_IPEN		(1<<0)	/* interrupt pending */

#define	HARRIER_IDFC_RFTL_MASK		(3<<6)	/* receiver trigger lvl mask */
#define	HARRIER_IDFC_DMAS		(1<<3)	/* DMA mode select */
#define	HARRIER_IDFC_TFR		(1<<2)	/* transmitter FIFO reset */
#define	HARRIER_IDFC_RFR		(1<<1)	/* receiver FIFO reset */
#define	HARRIER_IDFC_FIFOEN		(1<<0)	/* FIFO enable */

#define	HARRIER_LCTL_DLAB		(1<<7)	/* divisor latch access bit */
#define	HARRIER_LCTL_SB			(1<<6)	/* set break */
#define	HARRIER_LCTL_SP			(1<<5)	/* stick parity */
#define	HARRIER_LCTL_EPS		(1<<4)	/* even parity select */
#define	HARRIER_LCTL_PEN		(1<<3)	/* parity enable */
#define	HARRIER_LCTL_STB		(1<<2)	/* number of stop bits */
#define	HARRIER_LCTL_WLS_MASK		(3<<0)	/* word length select mask */
#define	HARRIER_LCTL_WLS_5BIT		(0<<0)	/* 5 bits per character */
#define	HARRIER_LCTL_WLS_6BIT		(1<<0)	/* 6 bits per character */
#define	HARRIER_LCTL_WLS_7BIT		(2<<0)	/* 7 bits per character */
#define	HARRIER_LCTL_WLS_8BIT		(3<<0)	/* 8 bits per character */


/*
 * HARRIER_UART_x_MCTL_REG  (MCTLx) XCSR+$0C4 & XCSR+$0CC
 * HARRIER_UART_x_LSTA_REG  (LSTAx) XCSR+$0C5 & XCSR+$0CD
 * HARRIER_UART_x_MSTA_REG  (MSTAx) XCSR+$0C6 & XCSR+$0CE
 * HARRIER_UART_x_SCRT_REG  (SCRTx) XCSR+$0C7 & XCSR+$0CF
 */

#define	HARRIER_MCTL_LOOP		(1<<4)	/* loopback mode */
#define	HARRIER_MCTL_OUT2		(1<<3)	/* output 2 signal */
#define	HARRIER_MCTL_OUT1		(1<<2)	/* output 1 signal */
#define	HARRIER_MCTL_RTS		(1<<1)	/* request-to-send output */
#define	HARRIER_MCTL_DTR		(1<<0)	/* data-terminal-ready output */

#define	HARRIER_LSTA_FERR		(1<<7)	/* error in receiver FIFO */
#define	HARRIER_LSTA_TEMT		(1<<6)	/* xmitter empty */
#define	HARRIER_LSTA_THRE		(1<<5)	/* xmiterr holding reg empty */
#define	HARRIER_LSTA_BI			(1<<4)	/* break interrupt */
#define	HARRIER_LSTA_FE			(1<<3)	/* framing error */
#define	HARRIER_LSTA_PE			(1<<2)	/* parity error */
#define	HARRIER_LSTA_OE			(1<<1)	/* overrun error */
#define	HARRIER_LSTA_DR			(1<<0)	/* data ready */

#define	HARRIER_MSTA_DCD		(1<<7)	/* data carrier detect */
#define	HARRIER_MSTA_RI			(1<<6)	/* ring indicator */
#define	HARRIER_MSTA_DSR		(1<<5)	/* data set ready */
#define	HARRIER_MSTA_CTS		(1<<4)	/* clear to send */
#define	HARRIER_MSTA_DDCD		(1<<3)	/* delta data carrier detect */
#define	HARRIER_MSTA_TERI		(1<<2)	/* trailing edge ring ind */
#define	HARRIER_MSTA_DDSR		(1<<1)	/* delta data set ready */
#define	HARRIER_MSTA_DCTS		(1<<0)	/* delta clear to send */


/*
 * HARRIER_UART_CONTROL_REG	     (UCTL) XCSR+$0D0
 * HARRIER_UART_CLOCK_PRESCALER_REG  (UPS)  XCSR+$0D3
 */

#define	HARRIER_UCTL_U0BO		(1<<6)	/* UART 0 baudout */
#define	HARRIER_UCTL_U1BO		(1<<5)	/* UART 1 baudout */
#define	HARRIER_UCTL_U0GRTS		(1<<4)  /* UART 0 gated RTS */
#define	HARRIER_UCTL_U1GRTS		(1<<3)  /* UART 1 gated RTS */
#define	HARRIER_UCTL_U0TXP		(1<<2)  /* UART 0 transmitter pause */
#define	HARRIER_UCTL_U1TXP		(1<<1)  /* UART 1 transmitter pause */
#define	HARRIER_UCTL_UCOS		(1<<0)	/* UART clock select */