harrier.h

vxworks的bsp开发包(基于POWERPC的PRPMC800)

/*
 * XCSR+$149 - SDRAM multi-bit error scrub block register
 * XCSR+$14C - SDRAM multi-bit error address register
 */

#define HARRIER_SDRAM_MBE_SCRUBBLOCK_REG  (HARRIER_XCSR_BASE + 0x149)
#define HARRIER_SDRAM_MBE_ADDRESS_REG	  (HARRIER_XCSR_BASE + 0x14C)



/*
 * XCSR+$200 - bridge PCI control and status register
 * XCSR+$204 - bridge PowerPC control and status register
 */

#define HARRIER_BRIDGE_PCI_CONTROLSTATUS_REG (HARRIER_XCSR_BASE + 0x200)
#define HARRIER_BRIDGE_PPC_CONTROLSTATUS_REG (HARRIER_XCSR_BASE + 0x204)

#define HARRIER_PCI_CS_REG_OFFSET 0x200 /* offset to control status reg */


/* XCSR+$210 - PCI interrupt acknowledge register */

#define HARRIER_PCI_INTERRUPT_ACK_REG (HARRIER_XCSR_BASE + 0x210)

/*
 * XCSR+$248 - passive slave address register
 * XCSR+$24C - passive slave offset register
 * XCSR+$24E - passive slave size register
 * XCSR+$24F - passive slave attribute register
 */

#define HARRIER_PASSIVE_SLAVEADDRESS_REG    (HARRIER_XCSR_BASE + 0x248)
#define HARRIER_PASSIVE_SLAVEOFFSET_REG     (HARRIER_XCSR_BASE + 0x24C)
#define HARRIER_PASSIVE_SLAVESIZE_REG	    (HARRIER_XCSR_BASE + 0x24E)
#define HARRIER_PASSIVE_SLAVEATTRIBUTE_REG  (HARRIER_XCSR_BASE + 0x24F)

/*
 * XCSR+$250 - DMA control register
 * XCSR+$254 - DMA status register
 * XCSR+$260 - DMA source address register
 * XCSR+$264 - DMA source attribute register
 * XCSR+$268 - DMA destination address register
 * XCSR+$26C - DMA destination attribute register
 * XCSR+$270 - DMA next link address register
 * XCSR+$274 - DMA count register
 * XCSR+$280 - DMA current source address register
 * XCSR+$284 - DMA current destination address register
 * XCSR+$288 - DMA current link address register
 */

#define HARRIER_DMA_CONTROL_REG 	       (HARRIER_XCSR_BASE + 0x250)
#define HARRIER_DMA_STATUS_REG		       (HARRIER_XCSR_BASE + 0x254)
#define HARRIER_DMA_SOURCEADDR_REG	       (HARRIER_XCSR_BASE + 0x260)
#define HARRIER_DMA_SOURCEATTR_REG	       (HARRIER_XCSR_BASE + 0x264)
#define HARRIER_DMA_DESTINATIONADDR_REG        (HARRIER_XCSR_BASE + 0x268)
#define HARRIER_DMA_DESTINATIONATTR_REG        (HARRIER_XCSR_BASE + 0x26C)
#define HARRIER_DMA_NEXTLINKADDR_REG	       (HARRIER_XCSR_BASE + 0x270)
#define HARRIER_DMA_COUNT_REG		       (HARRIER_XCSR_BASE + 0x274)
#define HARRIER_DMA_CURRENTSOURCEADDRREG       (HARRIER_XCSR_BASE + 0x280)
#define HARRIER_DMA_CURRENTDESTINATIONADDR_REG (HARRIER_XCSR_BASE + 0x284)
#define HARRIER_DMA_CURRENTLINKADDR_REG        (HARRIER_XCSR_BASE + 0x288)


/*
 * XCSR+$290 - MP generic outbound message 0 register
 * XCSR+$294 - MP generic outbound message 1 register
 * XCSR+$298 - MP generic outbound doorbell register
 * XCSR+$2A0 - MP generic inbound message 0 register
 * XCSR+$2A4 - MP generic inbound message 1 register
 * XCSR+$2A8 - MP generic inbound doorbell register
 * XCSR+$2B0 - MP generic inbound doorbell mask register
 */

#define HARRIER_MP_GENERIC_OUTBOUNDMESSAGE0_REG     (HARRIER_XCSR_BASE + 0x290)
#define HARRIER_MP_GENERIC_OUTBOUNDMESSAGE1_REG     (HARRIER_XCSR_BASE + 0x294)
#define HARRIER_MP_GENERIC_OUTBOUNDDOORBELL_REG     (HARRIER_XCSR_BASE + 0x298)
#define HARRIER_MP_GENERIC_INBOUNDMESSAGE0_REG	    (HARRIER_XCSR_BASE + 0x2A0)
#define HARRIER_MP_GENERIC_INBOUNDMESSAGE1_REG	    (HARRIER_XCSR_BASE + 0x2A4)
#define HARRIER_MP_GENERIC_INBOUNDDOORBELL_REG	    (HARRIER_XCSR_BASE + 0x2A8)
#define HARRIER_MP_GENERIC_INBOUNDDOORBELLMASK_REG  (HARRIER_XCSR_BASE + 0x2B0)

/*
 * XCSR+$2C0 - MP I2O outbound free_list head register
 * XCSR+$2C4 - MP I2O outbound free_list tail register
 * XCSR+$2C8 - MP I2O outbound post_list head register
 * XCSR+$2CC - MP I2O outbound post_list tail register
 * XCSR+$2D0 - MP I2O inbound free_list head register
 * XCSR+$2D4 - MP I2O inbound free_list tail register
 * XCSR+$2D8 - MP I2O inbound post_list head register
 * XCSR+$2DC - MP I2O inbound post_list tail register
 * XCSR+$2E0 - MP I2O control register
 * XCSR+$2E4 - MP I2O queue base register
 */

#define HARRIER_MP_I2O_OUTBOUNDFREELISTHEAD_REG (HARRIER_XCSR_BASE + 0x2C0)
#define HARRIER_MP_I2O_OUTBOUNDFREELISTTAIL_REG (HARRIER_XCSR_BASE + 0x2C4)
#define HARRIER_MP_I2O_OUTBOUNDPOSTLISTHEAD_REG (HARRIER_XCSR_BASE + 0x2C8)
#define HARRIER_MP_I2O_OUTBOUNDPOSTLISTTAIL_REG (HARRIER_XCSR_BASE + 0x2CC)
#define HARRIER_MP_I2O_INBOUNDFREELISTHEAD_REG	(HARRIER_XCSR_BASE + 0x2D0)
#define HARRIER_MP_I2O_INBOUNDFREELISTTAIL_REG	(HARRIER_XCSR_BASE + 0x2D4)
#define HARRIER_MP_I2O_INBOUNDPOSTLISTHEAD_REG	(HARRIER_XCSR_BASE + 0x2D8)
#define HARRIER_MP_I2O_INBOUNDPOSTLISTTAIL_REG	(HARRIER_XCSR_BASE + 0x2DC)
#define HARRIER_MP_I2O_CONTROL_REG		(HARRIER_XCSR_BASE + 0x2E0)
#define HARRIER_MP_I2O_QUEUEBASE_REG		(HARRIER_XCSR_BASE + 0x2E4)


/* HARRIER PHB (PCI Host Bridge)*/

/*
 * XCSR+$300 - vendor ID register
 * XCSR+$302 - device ID register
 * XCSR+$304 - command register
 * XCSR+$306 - status register
 * XCSR+$308 - revision ID / class code registers
 */

#define HARRIER_PHB_VENDORID_REG	 (HARRIER_XCSR_BASE + 0x300)
#define HARRIER_PHB_DEVICEID_REG	 (HARRIER_XCSR_BASE + 0x302)
#define HARRIER_PHB_COMMAND_REG 	 (HARRIER_XCSR_BASE + 0x304)
#define HARRIER_PHB_STATUS_REG		 (HARRIER_XCSR_BASE + 0x306)
#define HARRIER_PHB_REVISIONANDCLASS_REG (HARRIER_XCSR_BASE + 0x308)

/*
 * XCSR+$30C - cache line size register
 * XCSR+$30D - master latency timer register
 * XCSR+$30E - header type register (always reads as 0x00)
 */

#define HARRIER_CACHE_LINESIZE_REG	  (HARRIER_XCSR_BASE + 0x30C)
#define HARRIER_MASTER_LATENCY_TIMER_REG  (HARRIER_XCSR_BASE + 0x30D)
#define HARRIER_HEADERTYPE_REG		  (HARRIER_XCSR_BASE + 0x30E)

#define HARRIER_CACHE_LINESIZE            0x08000000
#define HARRIER_READLATENCY               0x00400000

/* XCSR+$310 - message passing register group base address register */

#define HARRIER_MSG_PASSING_REGGROUPBASEADDR_REG (HARRIER_XCSR_BASE + 0x310)
#define HARRIER_XCSR_MPBAR HARRIER_MSG_PASSING_REGGROUPBASEADDR_REG

/* XCSR+$314 - inbound translation base address registers (4) */

#define HARRIER_INBOUND_TRANSLATION_BASE_ADDRESS_0 (HARRIER_XCSR_BASE + 0x314)
#define HARRIER_INBOUND_TRANSLATION_BASE_ADDRESS_1 (HARRIER_XCSR_BASE + 0x318)
#define HARRIER_INBOUND_TRANSLATION_BASE_ADDRESS_2 (HARRIER_XCSR_BASE + 0x31C)
#define HARRIER_INBOUND_TRANSLATION_BASE_ADDRESS_3 (HARRIER_XCSR_BASE + 0x320)

/*
 * XCSR+$32C - subsystem ID register
 * XCSR+$32E - subsystem vendor ID register
 */

#define HARRIER_SUBSYSTEM_ID_REG       (HARRIER_XCSR_BASE + 0x32C)
#define HARRIER_SUBSYSTEM_VENDORID_REG (HARRIER_XCSR_BASE + 0x32E)

/*
 * XCSR+$33C - interrupt line register
 * XCSR+$33D - interrupt pin register
 * XCSR+$33E - minimum grant register
 * XCSR+$33F - maximum latency register
 */

#define HARRIER_INTERRUPT_LINE_REG  (HARRIER_XCSR_BASE + 0x33C)
#define HARRIER_INTERRUPT_PIN_REG   (HARRIER_XCSR_BASE + 0x33D)
#define HARRIER_MINIMUM_GRANT_REG   (HARRIER_XCSR_BASE + 0x33E)
#define HARRIER_MAXIMUM_LATENCY_REG (HARRIER_XCSR_BASE + 0x33F)

/* XCSR+$344 - message passing attribute register */

#define HARRIER_MSG_PASSINGATTR_REG (HARRIER_XCSR_BASE + 0x344)

/*
 * XCSR+$348 - inbound translation register 0
 * XCSR+$350 - inbound translation register 0
 * XCSR+$358 - inbound translation register 0
 * XCSR+$360 - inbound translation register 0
 */

#define HARRIER_INBOUND_TRANSLATION_SIZE_0_REG	(HARRIER_XCSR_BASE + 0x348)
#define HARRIER_INBOUND_TRANSLATION_SIZE_1_REG	(HARRIER_XCSR_BASE + 0x350)
#define HARRIER_INBOUND_TRANSLATION_SIZE_2_REG	(HARRIER_XCSR_BASE + 0x358)
#define HARRIER_INBOUND_TRANSLATION_SIZE_3_REG	(HARRIER_XCSR_BASE + 0x360)

#define HARRIER_INBOUND_TRANSLATION_OFFSET_0_REG	(HARRIER_XCSR_BASE + 0x34A)
#define HARRIER_INBOUND_TRANSLATION_OFFSET_1_REG	(HARRIER_XCSR_BASE + 0x352)
#define HARRIER_INBOUND_TRANSLATION_OFFSET_2_REG	(HARRIER_XCSR_BASE + 0x35A)
#define HARRIER_INBOUND_TRANSLATION_OFFSET_3_REG	(HARRIER_XCSR_BASE + 0x362)

#define HARRIER_INBOUND_TRANSLATION_ATTRIBUTE_0 (HARRIER_XCSR_BASE + 0x34C)
#define HARRIER_INBOUND_TRANSLATION_ATTRIBUTE_1	(HARRIER_XCSR_BASE + 0x354)
#define HARRIER_INBOUND_TRANSLATION_ATTRIBUTE_2	(HARRIER_XCSR_BASE + 0x35C)
#define HARRIER_INBOUND_TRANSLATION_ATTRIBUTE_3	(HARRIER_XCSR_BASE + 0x364)

#define HARRIER_PCI_STATUS_REG		(HARRIER_XCSR_BASE + 0x383)
#define HARRIER_PCI_GENERAL_PURPOSE_REG (HARRIER_XCSR_BASE + 0x384)

/* XCSR+$400 - general purpose memory, 2Kilobytes */

#define HARRIER_GENERAL_PURPOSE_MEMORY_STARTADDR (HARRIER_XCSR_BASE + 0x400)


/*
 * HARRIER_REGISTER_VENDOR_ID (VENI) XCSR+$000
 * HARRIER_REGISTER_DEVICE_ID (DEVI) XCSR+$002
 */

#define HARRIER_VENI			0x1057	/* vendor ID */
#define HARRIER_DEVI			0x480B	/* device ID */
#define HARRIER_IDS			((HARRIER_DEVI<<16)|HARRIER_VENI)

/*
 * HARRIER_REGISTER_REVISION_ID (REVI) XCSR+$004 
 */

#define HARRIER_REGISTER_REVISION_ID   (HARRIER_XCSR_BASE + 0x004)
#define HARRIER_REVISION_1             0x0001
#define HARRIER_REVISION_ID_SHIFT_MASK 16

/* HARRIER_GLOBAL_CONTROL_STATUS_REG (GCSR) XCSR+$010 */

#define HARRIER_GCSR_PUR	    (1<<31) /* power-up reset */
#define HARRIER_GCSR_PUST_MASK	   (15<<24) /* power-up status mask */
#define HARRIER_GCSR_AOAO	    (1<<20) /* address only ack other */

#define HARRIER_GCSR_XBS_MASK	    (3<<18) /* burst size/mode mask */
#define HARRIER_GCSR_XBS_64	    (0<<18) /* burst size: 64 */
#define HARRIER_GCSR_XBS_128	    (1<<18) /* burst size: 128 */
#define HARRIER_GCSR_XBS_256	    (2<<18) /* burst size: 256 */
#define HARRIER_GCSR_XBS_CON	    (3<<18) /* burst mode continuous */

#define HARRIER_GCSR_BTO_MASK	    (3<<16) /* bus time-out mask */
#define HARRIER_GCSR_BTO_256	    (0<<16) /* bus time-out 256 usec */
#define HARRIER_GCSR_BTO_64	    (1<<16) /* bus time-out 64 usec */
#define HARRIER_GCSR_BTO_8	    (2<<16) /* bus time-out 8 usec */
#define HARRIER_GCSR_BTO_DIS	    (3<<16) /* bus time-out disabled */

#define HARRIER_GCSR_MID_MASK	    (3<<12) /* bus master ID mask */
#define HARRIER_GCSR_MID_CPU0	    (0<<12) /* bus master ID: CPU0 */
#define HARRIER_GCSR_MID_CPU1	    (1<<12) /* bus master ID: CPU1 */
#define HARRIER_GCSR_MID_EXTL	    (2<<12) /* bus master ID: EXTL */
#define HARRIER_GCSR_MID_HARRIER    (3<<12) /* bus master ID: Harrier */

#define HARRIER_GCSR_RAT_MASK	    (7<<8)  /* PowerPC/PCI clk ratio mask */
#define HARRIER_GCSR_RAT_1to1	    (1<<8)  /* PowerPC/PCI clk ratio 1:1 */
#define HARRIER_GCSR_RAT_2to1	    (2<<8)  /* PowerPC/PCI clk ratio 2:1 */
#define HARRIER_GCSR_RAT_3to1	    (3<<8)  /* PowerPC/PCI clk ratio 3:1 */
#define HARRIER_GCSR_RAT_3to2	    (4<<8)  /* PowerPC/PCI clk ratio 3:2 */
#define HARRIER_GCSR_RAT_5to2	    (6<<8)  /* PowerPC/PCI clk ratio 5:2 */



/* HARRIER_MISC_CONTROL_STATUS_REG   (MCSR) XCSR+$01C */

#define HARRIER_MCSR_BRDFLS	    (1<<31) /* board fail status */
#define HARRIER_MCSR_BRDFL	    (1<<30) /* board fail */
#define HARRIER_MCSR_EREADYS	    (1<<29) /* PCI bus enum ready status */
#define HARRIER_MCSR_EREADY	    (1<<28) /* PCI bus enumeration ready */
#define HARRIER_MCSR_SCON	    (1<<27) /* system controller */
#define HARRIER_MCSR_TBEN0	    (1<<26) /* time base enable 0 */
#define HARRIER_MCSR_TBEN1	    (1<<25) /* time base enable 1 */
#define HARRIER_MCSR_RSTOUT	    (1<<24) /* reset out */
#define HARRIER_MCSR_RSTINH	    (1<<16) /* reset inhibit */


/* HARRIER_EXCEPTION_ENABLE_REG	(HARRIER_XCSR_BASE + 0x40) */
#define HARRIER_XCSR_FEEN 	HARRIER_EXCEPTION_ENABLE_REG

#define HARRIER_FEEN_DMA	    (1<<15) /* enable DMA exception */
#define HARRIER_FEEN_IMDB	    (1<<14) /* enable IB doorbell exc */
#define HARRIER_FEEN_IMM0	    (1<<13) /* enable IB MP 0 exc */
#define HARRIER_FEEN_IMM1	    (1<<12) /* enable IB MP 1 exc */
#define HARRIER_FEEN_MIP	    (1<<11) /* enable MIP exception */
#define HARRIER_FEEN_UA0	    (1<<10) /* enable UART #0 exception */
#define HARRIER_FEEN_UA1	    (1<<9)  /* enable UART #1 exception */
#define HARRIER_FEEN_ABT	    (1<<8)  /* enable abort exception */


/* HARRIER_REGISTER_FUNCTIONAL_EXCEPTION_STATUS (FEST) XCSR+$044 */

#define HARRIER_FEST_DMA	    (1<<15) /* DMA transaction complete */
#define HARRIER_FEST_IMDB	    (1<<14) /* IB doorbell bit written */
#define HARRIER_FEST_IMM0	    (1<<13) /* IB message 0 written */
#define HARRIER_FEST_IMM1	    (1<<12) /* IB message 1 written */
#define HARRIER_FEST_MIP	    (1<<11) /* msg written to post_list */
#define HARRIER_FEST_UA0	    (1<<10) /* UART #0 requesting service */
#define HARRIER_FEST_UA1	    (1<<9)  /* UART #1 requesting service */
#define HARRIER_FEST_ABT	    (1<<8)  /* abort was asserted */


/* HARRIER_EXCEPTION_MASK_REG	(HARRIER_XCSR_BASE + 0x48) */
#define HARRIER_XCSR_FEMA 	HARRIER_EXCEPTION_MASK_REG

#define HARRIER_FEMA_DMA	    (1<<15) /* mask DMA exception */
#define HARRIER_FEMA_IMDB	    (1<<14) /* mask IB doorbell exc */
#define HARRIER_FEMA_IMM0	    (1<<13) /* mask IB msg passing 0 exc */
#define HARRIER_FEMA_IMM1	    (1<<12) /* mask IB msg passing 1 exc */