📄 harrier.h
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/* harrier.h - Harrier chip header file *//* Copyright 1996-2001 Motorola, Inc. All Rights Reserved *//*modification history--------------------01g,10oct01,scb Add #define's for shared memory interrupt support.01f,09aug01,scb Add #defines for PPC arbiter register (XARB).01g,17may01,blk Add support for harrier II.01f,14nov00,dmw Added defines for Harrier offsets used in romInit.01e,17oct00,krp display of SMC SDRAM addressing & control settings.01d,16oct00,dmw Added PCI bridge defines.01c,08oct00,dmw corrected I2C device offsets.01b,01sep00,dmw added inbound translation defines.01a,11jul00,krp created for the prpmc800 BSP.*//*This file contains Base address defines, register offsets and bitdefinitions for the the Harrier chip*/#ifndef INCharrierh#define INCharrierh#ifdef __cplusplus extern "C" {#endif#ifndef HARRIER_XCSR_BASE# define HARRIER_XCSR_BASE 0xFEFF0000#endif#ifndef HARRIER_XCSR_SIZE# define HARRIER_XCSR_SIZE 0x00001000#endif/* * SDRAM block descriptor registers. these are for setting the base * address, size, and enable status for a block of SDRAM. there are * eight sets of these registers for up to eight blocks of SDRAM. */#define HARRIER_REG_SDRAM_BLOCK_ADDRESSING_A (HARRIER_XCSR_BASE + 0x110)#define HARRIER_REG_SDRAM_BLOCK_ADDRESSING_B (HARRIER_XCSR_BASE + 0x114)#define HARRIER_REG_SDRAM_BLOCK_ADDRESSING_C (HARRIER_XCSR_BASE + 0x118)#define HARRIER_REG_SDRAM_BLOCK_ADDRESSING_D (HARRIER_XCSR_BASE + 0x11C)#define HARRIER_REG_SDRAM_BLOCK_ADDRESSING_E (HARRIER_XCSR_BASE + 0x120)#define HARRIER_REG_SDRAM_BLOCK_ADDRESSING_F (HARRIER_XCSR_BASE + 0x124)#define HARRIER_REG_SDRAM_BLOCK_ADDRESSING_G (HARRIER_XCSR_BASE + 0x128)#define HARRIER_REG_SDRAM_BLOCK_ADDRESSING_H (HARRIER_XCSR_BASE + 0x12C)#define HARRIER_SDRAM_BLOCK_BASEADDR_OFFSET 0#define HARRIER_SDRAM_BLOCK_SIZE_OFFSET 1#define HARRIER_SDRAM_BLOCK_ENABLE_OFFSET 2/* * registers for X-port channels. these registers are used for setting the * starting address, ending address, and attributes for an X-port channel. * the attributes register also has read-only bit fields of information on * the X-port channel. * * There are FOUR available X-port channels. */#define HARRIER_XPORT0_ADDR_RANGE_REG (HARRIER_XCSR_BASE + 0x150)#define HARRIER_XPORT1_ADDR_RANGE_REG (HARRIER_XCSR_BASE + 0x158)#define HARRIER_XPORT2_ADDR_RANGE_REG (HARRIER_XCSR_BASE + 0x160)#define HARRIER_XPORT3_ADDR_RANGE_REG (HARRIER_XCSR_BASE + 0x168)#define HARRIER_XPORT0_ATTR_REG (HARRIER_XCSR_BASE + 0x154)#define HARRIER_XPORT1_ATTR_REG (HARRIER_XCSR_BASE + 0x15C)#define HARRIER_XPORT2_ATTR_REG (HARRIER_XCSR_BASE + 0x164)#define HARRIER_XPORT3_ATTR_REG (HARRIER_XCSR_BASE + 0x16C)#define HARRIER_XPORT_STARTADDR_OFFSET 0#define HARRIER_XPORT_ENDADDR_OFFSET 2#define HARRIER_XPORT_ATTR_OFFSET 4#define HARRIER_XPORT_GENERAL_CONTROL_REG (HARRIER_XCSR_BASE + 0x170)/* * registers for I2C serial bus interface. the Harrier has two seperate * I2C interfaces for up to two I2C serial buses. */#define HARRIER_I2C_CONTROLLER0_REG (HARRIER_XCSR_BASE + 0x180)#define HARRIER_I2C_CONTROLLER1_REG (HARRIER_XCSR_BASE + 0x1A0)#define HARRIER_I2C_PRESCALER_OFFSET 0x00#define HARRIER_I2C_CONTROL_OFFSET 0x04#define HARRIER_I2C_TRANSMITTER_DATA_OFFSET 0x0C#define HARRIER_I2C_STATUS_OFFSET 0x14#define HARRIER_I2C_RECEIVER_DATA_OFFSET 0x1C/* * registers descriptors for mapping PCI memory or I/O space to * PowerPC memory space. there are four sets of these registers. *//* * offset +00 - outbound translation range starting address register * offset +02 - outbound translation range ending address register * offset +04 - outbound translation address offset register * offset +06 - outbound translation attributes register */#define HARRIER_OUTBOUND_TRANSLATION_ADDR_0_REG (HARRIER_XCSR_BASE + 0x220)#define HARRIER_OUTBOUND_TRANSLATION_ADDR_1_REG (HARRIER_XCSR_BASE + 0x228)#define HARRIER_OUTBOUND_TRANSLATION_ADDR_2_REG (HARRIER_XCSR_BASE + 0x230)#define HARRIER_OUTBOUND_TRANSLATION_ADDR_3_REG (HARRIER_XCSR_BASE + 0x238)#define HARRIER_OUTBOUND_TRANSLATION_STARTADDRESS_OFFSET 0#define HARRIER_OUTBOUND_TRANSLATION_ENDADDRESS_OFFSET 2#define HARRIER_OUTBOUND_TRANSLATION_OFFSETINFO_OFFSET 4#define HARRIER_OUTBOUND_TRANSLATION_ATTRIBUTE_OFFSET 6#define HARRIER_VENDOR_ID_REG (HARRIER_XCSR_BASE + 0x000) /* Motorola: 0x1057 */#define HARRIER_DEVICE_ID_REG (HARRIER_XCSR_BASE + 0x002) /* Harrier: 0x480B */#define HARRIER_VERSION_ID_REG (HARRIER_XCSR_BASE + 0x005)/* * XCSR+$010 - global control and status register * XCSR+$014 - PowerPC clock frequency register * XCSR+$018 - count 32-bit register * XCSR+$01C - miscellaneous control and status register */#define H_PPCCLKFRQ_OFST (0x014)#define HARRIER_GLOBAL_CONTROL_STATUS_REG (HARRIER_XCSR_BASE + 0x010)#define HARRIER_PPC_CLOCK_FREQUENCY_REG (HARRIER_XCSR_BASE + H_PPCCLKFRQ_OFST)#define HARRIER_COUNTER_32BIT_REG (HARRIER_XCSR_BASE + 0x018)#define HARRIER_MISC_CONTROL_STATUS_REG (HARRIER_XCSR_BASE + 0x01C)#define HARRIER_GP0_OFFSET (0x020)#define HARRIER_GP1_OFFSET (0x024)#define HARRIER_GP2_OFFSET (0x028)#define HARRIER_GP3_OFFSET (0x02C)#define HARRIER_GP4_OFFSET (0x030)#define HARRIER_GP5_OFFSET (0x034)#define HARRIER_GENERAL_PURPOSE0_REG (HARRIER_XCSR_BASE + HARRIER_GP0_OFFSET)#define HARRIER_GENERAL_PURPOSE1_REG (HARRIER_XCSR_BASE + HARRIER_GP1_OFFSET)#define HARRIER_GENERAL_PURPOSE2_REG (HARRIER_XCSR_BASE + HARRIER_GP2_OFFSET)#define HARRIER_GENERAL_PURPOSE3_REG (HARRIER_XCSR_BASE + HARRIER_GP3_OFFSET)#define HARRIER_GENERAL_PURPOSE4_REG (HARRIER_XCSR_BASE + HARRIER_GP4_OFFSET)#define HARRIER_GENERAL_PURPOSE5_REG (HARRIER_XCSR_BASE + HARRIER_GP5_OFFSET)/* * XCSR+$040 - functional exception enable register * XCSR+$044 - functional exception status register * XCSR+$048 - functional exception mask register * XCSR+$04C - functional exception clear register */#define HARRIER_EXCEPTION_ENABLE_REG (HARRIER_XCSR_BASE + 0x040)#define HARRIER_EXCEPTION_STATUS_REG (HARRIER_XCSR_BASE + 0x044)#define HARRIER_EXCEPTION_MASK_REG (HARRIER_XCSR_BASE + 0x048)#define HARRIER_EXCEPTION_CLEAR_REG (HARRIER_XCSR_BASE + 0x04C)#define HARRIER_ERROR_EXCEPTION_ENABLE_REG (HARRIER_XCSR_BASE + 0x050)#define HARRIER_ERROR_EXCEPTION_STATUS_REG (HARRIER_XCSR_BASE + 0x054)#define HARRIER_ERROR_EXCEPTION_CLEAR_REG (HARRIER_XCSR_BASE + 0x058)#define HARRIER_ERROR_EXCEPTION_INT_ENABLE_REG (HARRIER_XCSR_BASE + 0x05C)#define HARRIER_ERROR_EXCMACHINECHECK0_ENABLE (HARRIER_XCSR_BASE + 0x060)#define HARRIER_ERROR_EXCMACHINECHECK1_ENABLE (HARRIER_XCSR_BASE + 0x064)/* * XCSR+$06C - error diagnostics parity error injection register * XCSR+$070 - error diagnostics PowerPC address register * XCSR+$074 - error diagnostics PowerPC attribute register * XCSR+$078 - error diagnostics PCI address register * XCSR+$07C - error diagnostics PCI attribute register */#define HARRIER_ERR_DIAGS_PARITYERRORINJECT_REG (HARRIER_XCSR_BASE + 0x06C)#define HARRIER_ERR_DIAGS_PPCADDRESS_REG (HARRIER_XCSR_BASE + 0x070)#define HARRIER_ERR_DIAGS_PPCATTRIBUTE_REG (HARRIER_XCSR_BASE + 0x074)#define HARRIER_ERR_DIAGS_PCIADDRESS_REG (HARRIER_XCSR_BASE + 0x078)#define HARRIER_ERR_DIAGS_PCIATTRIBUTE_REG (HARRIER_XCSR_BASE + 0x07C)/* * XCSR+$080 - watchdog timer #0 control register * XCSR+$084 - watchdog timer #0 status register * XCSR+$088 - watchdog timer #1 control register * XCSR+$08C - watchdog timer #1 status register */#define HARRIER_WATCHDOGTIMER_CONTROL0_REG (HARRIER_XCSR_BASE + 0x080)#define HARRIER_WATCHDOGTIMER_STATUS0_REG (HARRIER_XCSR_BASE + 0x084)#define HARRIER_WATCHDOGTIMER_CONTROL1_REG (HARRIER_XCSR_BASE + 0x088)#define HARRIER_WATCHDOGTIMER_STATUS1_REG (HARRIER_XCSR_BASE + 0x08C)#define HARRIER_WTCHDG_CNTR0_OFFSET (0x080)#define HARRIER_WTCHDG_CNTR1_OFFSET (0x088)/* * XCSR+$090 - PCI arbiter register * XCSR+$094 - PowerPC arbiter register */#define HARRIER_PCI_ARBITER_REG (HARRIER_XCSR_BASE + 0x090)#define HARRIER_PPC_ARBITER_REG (HARRIER_XCSR_BASE + 0x094)/* * XCSR+$0C0 - UART #0 receiver buffer / transmitter holding / * divisor latch low register * XCSR+$0C1 - UART #0 interrupt enable / divisor latch high register * XCSR+$0C2 - UART #0 interrupt identification / FIFO control register * XCSR+$0C3 - UART #0 line control register * XCSR+$0C4 - UART #0 modem control register * XCSR+$0C5 - UART #0 line status register * XCSR+$0C6 - UART #0 modem status register * XCSR+$0C7 - UART #0 scratch register */#define HARRIER_UART_0_RTDL_REG (HARRIER_XCSR_BASE + 0x0C0)#define HARRIER_UART_0_IEDH_REG (HARRIER_XCSR_BASE + 0x0C1)#define HARRIER_UART_0_IDFC_REG (HARRIER_XCSR_BASE + 0x0C2)#define HARRIER_UART_0_LCTL_REG (HARRIER_XCSR_BASE + 0x0C3)#define HARRIER_UART_0_MCTL_REG (HARRIER_XCSR_BASE + 0x0C4)#define HARRIER_UART_0_LSTA_REG (HARRIER_XCSR_BASE + 0x0C5)#define HARRIER_UART_0_MSTA_REG (HARRIER_XCSR_BASE + 0x0C6)#define HARRIER_UART_0_SCRT_REG (HARRIER_XCSR_BASE + 0x0C7)/* * XCSR+$0C8 - UART #1 receiver buffer / transmitter holding / * divisor latch low register * XCSR+$0C9 - UART #1 interrupt enable / divisor latch high register * XCSR+$0CA - UART #1 interrupt identification / FIFO control register * XCSR+$0CB - UART #1 line control register * XCSR+$0CC - UART #1 modem control register * XCSR+$0CD - UART #1 line status register * XCSR+$0CE - UART #1 modem status register * XCSR+$0CF - UART #1 scratch register */#define HARRIER_UART_1_RTDL_REG (HARRIER_XCSR_BASE + 0x0C8)#define HARRIER_UART_1_IEDH_REG (HARRIER_XCSR_BASE + 0x0C9)#define HARRIER_UART_1_IDFC_REG (HARRIER_XCSR_BASE + 0x0CA)#define HARRIER_UART_1_LCTL_REG (HARRIER_XCSR_BASE + 0x0CB)#define HARRIER_UART_1_MCTL_REG (HARRIER_XCSR_BASE + 0x0CC)#define HARRIER_UART_1_LSTA_REG (HARRIER_XCSR_BASE + 0x0CD)#define HARRIER_UART_1_MSTA_REG (HARRIER_XCSR_BASE + 0x0CE)#define HARRIER_UART_1_SCRT_REG (HARRIER_XCSR_BASE + 0x0CF)/* * XCSR+$0D0 - UART control register * XCSR+$0D3 - UART clock prescaler register */#define HARRIER_UART_CONTROL_REG (HARRIER_XCSR_BASE + 0x0D0)#define HARRIER_UART_CLOCK_PRESCALER_REG (HARRIER_XCSR_BASE + 0x0D3)/* * XCSR+$0E0 - MPIC base address register * XCSR+$0E4 - MPIC control and status register * XCSR+$0E6 - MPIC interrupt request sample register */#define HARRIER_MPIC_BASEADDRESS_REG (HARRIER_XCSR_BASE + 0x0E0)#define HARRIER_MPIC_CONTROL_STATUS_REG (HARRIER_XCSR_BASE + 0x0E4)#define HARRIER_MPIC_INT_REQUESTSAMPLE_REG (HARRIER_XCSR_BASE + 0x0E6)/* * XCSR+$100 - SDRAM general control register * XCSR+$104 - SDRAM timing control register */#define HARRIER_SDRAM_GENERAL_CONTROL_REG (HARRIER_XCSR_BASE + 0x100)#define HARRIER_SDRAM_TIMING_CONTROL_REG (HARRIER_XCSR_BASE + 0x104)/* * XCSR+$130 - SDRAM scrub control register * XCSR+$134 - SDRAM scrub address counter */#define HARRIER_SDRAM_SCRUB_CONTROL_REG (HARRIER_XCSR_BASE + 0x130)#define HARRIER_SDRAM_SCRUB_ADDRESSCOUNTER_REG (HARRIER_XCSR_BASE + 0x134)/* * XCSR+$140 - SDRAM single-bit error syndrome register * XCSR+$141 - SDRAM single-bit error scrub block register * XCSR+$142 - SDRAM single-bit error count register * XCSR+$144 - SDRAM single-bit error address register */#define HARRIER_SDRAM_SBE_SYNDROME_REG (HARRIER_XCSR_BASE + 0x140)#define HARRIER_SDRAM_SBE_SCRUBBLOCK_REG (HARRIER_XCSR_BASE + 0x141)#define HARRIER_SDRAM_SBE_COUNT_REG (HARRIER_XCSR_BASE + 0x142)#define HARRIER_SDRAM_SBE_ADDRESS_REG (HARRIER_XCSR_BASE + 0x144)⌨️ 快捷键说明
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