tmbtnanddrv.c

pnx8950 nand flash 驱动

/*
                           SDK (Nand Driver)
                         ---------------------


   Copyright (c) 2004 Koninklijke Philips Electronics N.V. All rights reserved

   This source code and any compilation or derivative thereof is the
   proprietary information of Koninklijke Philips Electronics N.V.
   and is confidential in nature.
   Under no circumstances is this software to be exposed to or placed
   under an Open Source License of any type without the expressed
   written permission of Koninklijke Philips Electronics N.V.

   COMPANY CONFIDENTIAL

Filename  :     tmbtNandDrv.c


Rev Date       Author      Comments
--------------------------------------------------------------------------------
001 04/10/2004 A Charrett  Original
002 25/05/2005 A Charrett  Update with new cache routines and macro names.
003 27/05/2005 A Charrett  corrections after crosscheck
004 13/09/2005 A Charrett  Update for 8bit flash
005 16/09/2005 A Charrett  Remove forcing 16Bit/8Bit XIO mode
006 24/10/2005 burningh    Adding support for larger devices (4 addr cycles)
007 02/02/2006 batelaan    Ensured MMIO is declared volatile
                           (rather than using compiler -fvolatile option).
008 09/02/2006 burningh    Adding support for larger 8-bit Hynix devices
*/

/** Description

*/

/* Do not remove the following comments even if not applicable.
   This makes the fact explicit that for eg. there are no local typedefs,
   and allows consistant layout during maintenance phases     */

/*******************
* INCLUDE FILES    *
********************/
#include "tmbtNandDrv.h"
#include "tmbtNandDrv_internal.h"
#include "tmbtViper2.h"
#include "tmbtMips.h"

/*******************
* LOCAL MACROS     *
********************/
#define DMA_TIMEOUT 0xFFFF

#define NAND_SIZE_256_MBIT (32*1024*1024)

#define NAND_MFR_ID0               0
#define NAND_DEV_ID0               8
#define NAND_16BIT                16
#define NAND_NROF_BYTES_SPARE0    17
#define NAND_NROF_BYTES_MAIN0     20
#define NAND_NROF_PAGES0          24
#define NAND_NROF_BLOCKS0         28

#define NAND_MFR_ID_M             0x000000FF
#define NAND_DEV_ID_M             0x0000FF00
#define NAND_16BIT_M              0x00010000
#define NAND_NROF_BYTES_SPARE_M   0x000E0000
#define NAND_NROF_BYTES_MAIN_M    0x00F00000
#define NAND_NROF_PAGES_M         0x0F000000
#define NAND_NROF_BLOCKS_M        0xF0000000

#define NAND_MFR_SET(_ID)                 ((_ID << NAND_MFR_ID0) & NAND_MFR_ID_M)
#define NAND_DEV_SET(_ID)                 ((_ID << NAND_DEV_ID0) & NAND_DEV_ID_M)
#define NAND_16BIT_SET(_bit)              ((_bit << NAND_16BIT) & NAND_16BIT_M)
#define NAND_NROF_BYTES_SPARE_SET(_bytes) ((_bytes << NAND_NROF_BYTES_SPARE0) & NAND_NROF_BYTES_SPARE_M)
#define NAND_NROF_BYTES_MAIN_SET(_bytes)  ((_bytes << NAND_NROF_BYTES_MAIN0) & NAND_NROF_BYTES_MAIN_M)
#define NAND_NROF_PAGES_SET(_pages)       ((_pages << NAND_NROF_PAGES0) & NAND_NROF_PAGES_M)
#define NAND_NROF_BLOCKS_SET(_blocks)     ((_blocks << NAND_NROF_BLOCKS0) & NAND_NROF_BLOCKS_M)

#define NAND_MFR_GET(_DevInfo)              ((_DevInfo & NAND_MFR_ID_M) >> NAND_MFR_ID0)
#define NAND_DEV_GET(_DevInfo)              ((_DevInfo & NAND_DEV_ID_M) >> NAND_DEV_ID0)
#define NAND_16BIT_GET(_DevInfo)            ((_DevInfo & NAND_16BIT_M) >> NAND_16BIT)
#define NAND_NROF_BYTES_SPARE_GET(_DevInfo) ((_DevInfo & NAND_NROF_BYTES_SPARE_M) >> NAND_NROF_BYTES_SPARE0)
#define NAND_NROF_BYTES_MAIN_GET(_DevInfo)  ((_DevInfo & NAND_NROF_BYTES_MAIN_M)  >> NAND_NROF_BYTES_MAIN0)
#define NAND_NROF_PAGES_GET(_DevInfo)       ((_DevInfo & NAND_NROF_PAGES_M)  >> NAND_NROF_PAGES0)
#define NAND_NROF_BLOCKS_GET(_DevInfo)      ((_DevInfo & NAND_NROF_BLOCKS_M) >> NAND_NROF_BLOCKS0)

/* Macros to make it easier to read the chip definitions */
#define NAND_MFR_TOSHIBA 0x98
#define NAND_MFR_SAMSUNG 0xEC
#define NAND_MFR_ST      0x20
#define NAND_MFR_HYNIX   0xAD

#define NAND_BITS_8  0
#define NAND_BITS_16 1

#define NAND_SPARE_SIZE_8  3
#define NAND_SPARE_SIZE_16 4
#define NAND_SPARE_SIZE_32 5

#define NAND_MAIN_SIZE_512   9
#define NAND_MAIN_SIZE_1024 10
#define NAND_MAIN_SIZE_2048 11

#define NAND_NROF_PAGES_32   5
#define NAND_NROF_PAGES_64   6
#define NAND_NROF_PAGES_128  7

#define NAND_NROF_BLOCKS_512   9
#define NAND_NROF_BLOCKS_1024 10
#define NAND_NROF_BLOCKS_2048 11
#define NAND_NROF_BLOCKS_4096 12

#define NAND_CHIP(_mfr, _dev, _bits, _spare, _main, _pages, _blocks) \
        NAND_MFR_SET(_mfr) | NAND_DEV_SET(_dev) | NAND_16BIT_SET(_bits) \
      | NAND_NROF_BYTES_SPARE_SET(_spare) | NAND_NROF_BYTES_MAIN_SET(_main) \
      | NAND_NROF_PAGES_SET(_pages) | NAND_NROF_BLOCKS_SET(_blocks)

/*******************
* EXPORTED DATA    *
********************/
volatile UInt32 * gptmbtNandDrvXioBase;
volatile UInt32 * gptmbtNandDrvNandBase;

UInt32 gtmbtNandDrvCapabilities;
UInt32 gtmbtNandDrvNumOfBlocks;
UInt32 gtmbtNandDrvNumOfPages;
UInt32 gtmbtNandDrvNumOfBytesMain;
UInt32 gtmbtNandDrvNumOfBytesSpare;
UInt32 gtmbtNandDrvNumOfBytesBlock;
UInt32 gtmbtNandDrvNumOfBytesDevice;
UInt32 gtmbtNandDrv16bit;
UInt32 gtmbtNandDrvAddressCyclesRW; /* Address cycles needed for read or write */
UInt32 gtmbtNandDrvAddressCyclesBE; /* Address cycles needed for block erase */
UInt32 gtmbtNandDrv64MegDevice;

/*******************
* LOCAL TYPEDEFS   *
********************/

/**********************
* FUNCTION PROTOTYPES *
***********************/

/*******************
* STATIC DATA      *
********************/
static UInt32 gDeviceList[] = {
#ifdef NAND16BIT
    /* Toshiba, TC58DxM82x */
    NAND_CHIP(NAND_MFR_TOSHIBA, 0x75, NAND_BITS_16,
              NAND_SPARE_SIZE_16, NAND_MAIN_SIZE_512,
              NAND_NROF_PAGES_32, NAND_NROF_BLOCKS_2048),

    /* Samsung, K9F2816U0C */
    NAND_CHIP(NAND_MFR_SAMSUNG, 0x53, NAND_BITS_16,
              NAND_SPARE_SIZE_16, NAND_MAIN_SIZE_512,
              NAND_NROF_PAGES_32, NAND_NROF_BLOCKS_1024),

    /* Samsung, K9F5616U0C */
    NAND_CHIP(NAND_MFR_SAMSUNG, 0x55, NAND_BITS_16,
              NAND_SPARE_SIZE_16, NAND_MAIN_SIZE_512,
              NAND_NROF_PAGES_32, NAND_NROF_BLOCKS_2048),
#else
    /* ST, NAND128W3A */
    NAND_CHIP(NAND_MFR_ST, 0x73, NAND_BITS_8,
              NAND_SPARE_SIZE_16, NAND_MAIN_SIZE_512,
              NAND_NROF_PAGES_32, NAND_NROF_BLOCKS_1024),

    /* ST, NAND256R3A */
    NAND_CHIP(NAND_MFR_ST, 0x35, NAND_BITS_8,
              NAND_SPARE_SIZE_16, NAND_MAIN_SIZE_512,
              NAND_NROF_PAGES_32, NAND_NROF_BLOCKS_2048),

    /* ST, NAND256W3A */
    NAND_CHIP(NAND_MFR_ST, 0x75, NAND_BITS_8,
              NAND_SPARE_SIZE_16, NAND_MAIN_SIZE_512,
              NAND_NROF_PAGES_32, NAND_NROF_BLOCKS_2048),

    /* ST, NAND512R3A */
    NAND_CHIP(NAND_MFR_ST, 0x36, NAND_BITS_8,
              NAND_SPARE_SIZE_16, NAND_MAIN_SIZE_512,
              NAND_NROF_PAGES_32, NAND_NROF_BLOCKS_4096),

    /* ST, NAND512W3A */
    NAND_CHIP(NAND_MFR_ST, 0x76, NAND_BITS_8,
              NAND_SPARE_SIZE_16, NAND_MAIN_SIZE_512,
              NAND_NROF_PAGES_32, NAND_NROF_BLOCKS_4096),

    /* Hynix, HY27US08561M */
    NAND_CHIP(NAND_MFR_HYNIX, 0x35, NAND_BITS_8,
              NAND_SPARE_SIZE_16, NAND_MAIN_SIZE_512,
              NAND_NROF_PAGES_32, NAND_NROF_BLOCKS_2048),

    /* Hynix, HY27SS08561M */
    NAND_CHIP(NAND_MFR_HYNIX, 0x75, NAND_BITS_8,
              NAND_SPARE_SIZE_16, NAND_MAIN_SIZE_512,
              NAND_NROF_PAGES_32, NAND_NROF_BLOCKS_2048),

    /* Hynix, HY27US08121A */
    NAND_CHIP(NAND_MFR_HYNIX, 0x36, NAND_BITS_8,
              NAND_SPARE_SIZE_16, NAND_MAIN_SIZE_512,
              NAND_NROF_PAGES_32, NAND_NROF_BLOCKS_4096),

    /* Hynix, HY27SS08121A */
    NAND_CHIP(NAND_MFR_HYNIX, 0x76, NAND_BITS_8,
              NAND_SPARE_SIZE_16, NAND_MAIN_SIZE_512,
              NAND_NROF_PAGES_32, NAND_NROF_BLOCKS_4096),
#endif
    0 /* End Of List */

};

/***************************
* FUNCTION IMPLEMENTATIONS *
****************************/

/******************************************************************************/
/** +++ tmbtNandDrvInit

    Initialise the NAND flash driver.

    +++ Parameter         Flow    Description
        pMmiobasePhys     IN      Physical Memory location of MMIO base.

    +++ Return value