sdram_init.c

这是一个G.711在DSP上运行的程序.已经通过调试

void WaitMsec(int dely);

void initemif()
{
    /*
    ioport unsigned int *io800  =(unsigned int *)0x800;
    ioport unsigned int *io801  =(unsigned int *)0x801;
    ioport unsigned int *io802  =(unsigned int *)0x802;
    ioport unsigned int *io803  =(unsigned int *)0x803;
    ioport unsigned int *io804  =(unsigned int *)0x804;
    ioport unsigned int *io806  =(unsigned int *)0x806;
    ioport unsigned int *io807  =(unsigned int *)0x807;
    ioport unsigned int *io808  =(unsigned int *)0x808;
    ioport unsigned int *io809  =(unsigned int *)0x809;
    ioport unsigned int *io80a  =(unsigned int *)0x80a;
    ioport unsigned int *io80c  =(unsigned int *)0x80c;
    ioport unsigned int *io80d  =(unsigned int *)0x80d;
    ioport unsigned int *io80e  =(unsigned int *)0x80e;
    ioport unsigned int *io80f  =(unsigned int *)0x80f;
    ioport unsigned int *io810  =(unsigned int *)0x810;
    ioport unsigned int *io811  =(unsigned int *)0x811;
    ioport unsigned int *io81a  =(unsigned int *)0x81a;
    ioport unsigned int *io81b  =(unsigned int *)0x81b;
    ioport unsigned int *io81c  =(unsigned int *)0x81c;
    ioport unsigned int *io81d  =(unsigned int *)0x81d;
    ioport unsigned int *io81e  =(unsigned int *)0x81e;
    ioport unsigned int *io81f  =(unsigned int *)0x81f;
    ioport unsigned int *io822  =(unsigned int *)0x822;
    ioport unsigned int *io824  =(unsigned int *)0x824;
    
    *io800  =0x07e4;
    *io801  =0x0001;
    *io802  =0x4619;
    *io803  =0x0190;
    *io804  =0x7f93;
    *io806  =0x07e4;
    *io807  =0x0001;
    *io808  =0x4329;
    *io809  =0x00d0;
    *io80a  =0x7f43;
    *io80c  =0x6000;
    *io80d  =0x0611;
    *io80e  =0xd492;
    *io80f  =0x0008;
    *io810  =0xb528;
    *io811  =0x0007;
    *io81a  =0x07e4;
    *io81b  =0x0001;
    *io81c  =0x07e4;
    *io81d  =0x0001;
    *io81e  =0x07e4;
    *io81f  =0x0001;
    *io822  =0x000a;
    *io824  =0x000a;*/
    ioport unsigned int *EMIF_GCTL1  	 =(unsigned int *)0x800;
    ioport unsigned int *EMIF_GCTL2  	 =(unsigned int *)0x801;
    ioport unsigned int *EMIF_CE11   	 =(unsigned int *)0x802;
    ioport unsigned int *EMIF_CE12   	 =(unsigned int *)0x803; 
    ioport unsigned int *EMIF_CE01   	 =(unsigned int *)0x804;
    ioport unsigned int *EMIF_CE02   	 =(unsigned int *)0x805;
    ioport unsigned int *EMIF_CE21   	 =(unsigned int *)0x808;
    ioport unsigned int *EMIF_CE22   	 =(unsigned int *)0x809;
    ioport unsigned int *EMIF_CE31   	 =(unsigned int *)0x80A;
    ioport unsigned int *EMIF_CE32   	 =(unsigned int *)0x80B;
    ioport unsigned int *EMIF_SDCNT1  	 =(unsigned int *)0x80C;
    ioport unsigned int *EMIF_SDCNT2  	 =(unsigned int *)0x80D;
    ioport unsigned int *EMIF_SDREF1  	 =(unsigned int *)0x80E;
    ioport unsigned int *EMIF_SDREF2  	 =(unsigned int *)0x80F;
    ioport unsigned int *EMIF_SDEXT1  	 =(unsigned int *)0x810;
    ioport unsigned int *EMIF_SDEXT2  	 =(unsigned int *)0x811;
    ioport unsigned int *EMIF_CE1SECCTL1 =(unsigned int *)0x822;
    ioport unsigned int *EMIF_CE1SECCTL2 =(unsigned int *)0x823;
    ioport unsigned int *EMIF_CE0SECCTL1 =(unsigned int *)0x824;
    ioport unsigned int *EMIF_CE0SECCTL2 =(unsigned int *)0x825;
    ioport unsigned int *EMIF_CE2SECCTL1 =(unsigned int *)0x828;
    ioport unsigned int *EMIF_CE2SECCTL2 =(unsigned int *)0x829;
    ioport unsigned int *EMIF_CE3SECCTL1 =(unsigned int *)0x82A;
    ioport unsigned int *EMIF_CE3SECCTL2 =(unsigned int *)0x82B;
    ioport unsigned int *EMIF_CECTL1     =(unsigned int *)0x840;
    ioport unsigned int *EMIF_CECTL2  	 =(unsigned int *)0x841;
    *EMIF_GCTL1		 =0x2F7C;
    *EMIF_GCTL2		 =0x0009;
    *EMIF_CE11		 =0xFF13;
    *EMIF_CE12		 =0xFFFF;
    *EMIF_CE01		 =0xFF93;
    *EMIF_CE02		 =0xFFFF;
    *EMIF_CE21		 =0xFF23;
    *EMIF_CE22		 =0xFFFF;
    *EMIF_CE31		 =0xFF03;
    *EMIF_CE32		 =0xFFFF;
    *EMIF_SDCNT1	 =0xF000;
    *EMIF_SDCNT2	 =0x0648;
    *EMIF_SDREF1	 =0x1001;
    *EMIF_SDREF2	 =0x0000;
    *EMIF_SDEXT1	 =0x5F3F;
    *EMIF_SDEXT2	 =0x0017;
    *EMIF_CE1SECCTL1 =0x0002;
    *EMIF_CE1SECCTL2 =0x0000;
    *EMIF_CE0SECCTL1 =0x0002;
    *EMIF_CE0SECCTL2 =0x0000;
    *EMIF_CE2SECCTL1 =0x0002;
    *EMIF_CE2SECCTL2 =0x0000;
    *EMIF_CE3SECCTL1 =0x0002;
    *EMIF_CE3SECCTL2 =0x0000;
    *EMIF_CECTL1 	 =0x0000;
    *EMIF_CECTL2 	 =0x0000;
}

void CLK_init( void )
{
   ioport unsigned int *PLLCSR  	 =(unsigned int *)0x1C80;
   ioport unsigned int *CK3SEL  	 =(unsigned int *)0x1C82;
   ioport unsigned int *PLLM  	     =(unsigned int *)0x1C88;
   ioport unsigned int *PLLDIV0  	 =(unsigned int *)0x1C8A;
   ioport unsigned int *PLLDIV1  	 =(unsigned int *)0x1C8C;
   ioport unsigned int *PLLDIV2  	 =(unsigned int *)0x1C8E;
   ioport unsigned int *PLLDIV3  	 =(unsigned int *)0x1C90;
   ioport unsigned int *OSCDIV1  	 =(unsigned int *)0x1C92;
   ioport unsigned int *WKEN  	     =(unsigned int *)0x1C98;
   ioport unsigned int *CLKOUTSR  	 =(unsigned int *)0x8400;
   ioport unsigned int *CLKMD  	     =(unsigned int *)0x8C00;
   *PLLCSR=0x0000;     //switch bypass by setting pllen to 0
   *PLLCSR=0x0008;     //switch pll to reset by setting pllrst to 1
   *CLKMD=0;           //select oscout for clock input
   *WKEN=0x1f;         //no interrupt can wake up the oscillator
   *PLLM=0x0003;       //pll=20M*PLLM
   *PLLDIV0=0x8000;    //pll=pll/(PLLDIV0[4:0]+1)
   *PLLDIV1=0x8000;    //sysclk1,fast peripherals:dma,hpi,timer
   *PLLDIV2=0x8000;    //sysclk2,slow peripherals:mcbsp,i2c,uart
   *PLLDIV3=0x8003;    //sysclk3,emif
   *CLKOUTSR=0x6;      //select clkout,0x2:sysclk1,0x4:sysclk2,0x6:sysclk3
   *OSCDIV1=0x8000;    //set no divice to core
   *CK3SEL=0x000b;     //select point "C" to core,so core frequency=pll
   WaitMsec(1);
   *PLLCSR=0x0000;     //release pll by setting pllrst to 0
   do
   {
       asm(" nop");             
   }while((*PLLCSR&0x0020)!=0x0020);  //wait for pll lock
   
   *PLLCSR=0x0001;      //set to pll mode
   
   
}

void WaitMsec(int dely)
{
    int ii,jj,kk;
    kk=0;
    for(ii=0;ii<dely;ii++)
    {
        for(jj=0;jj<1024;jj++)
        {
             kk++;
             kk--;
        }
    }
}