ethernet.c

iar 安装使用的方法。其中包括一些工程模板

//*****************************************************************************
//
// ethernet.c - Driver for the Integrated Ethernet Controller
//
// Copyright (c) 2006-2008 Luminary Micro, Inc.  All rights reserved.
// 
// Software License Agreement
// 
// Luminary Micro, Inc. (LMI) is supplying this software for use solely and
// exclusively on LMI's microcontroller products.
// 
// The software is owned by LMI and/or its suppliers, and is protected under
// applicable copyright laws.  All rights are reserved.  You may not combine
// this software with "viral" open-source software in order to form a larger
// program.  Any use in violation of the foregoing restrictions may subject
// the user to criminal sanctions under applicable laws, as well as to civil
// liability for the breach of the terms and conditions of this license.
// 
// THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
// OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
// MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
// LMI SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
// CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
// 
// This is part of revision 2752 of the Stellaris Peripheral Driver Library.
//
//*****************************************************************************

//*****************************************************************************
//
//! \addtogroup ethernet_api
//! @{
//
//*****************************************************************************

#include "../hw_ints.h"
#include "../hw_memmap.h"
#include "../hw_types.h"
#include "../hw_ethernet.h"
#include "debug.h"
#include "interrupt.h"
#include "sysctl.h"
#include "ethernet.h"

//*****************************************************************************
//
//! Initializes the Ethernet controller for operation.
//!
//! \param ulBase is the base address of the controller.
//! \param ulEthClk is the rate of the clock supplied to the Ethernet module.
//!
//! This function will prepare the Ethernet controller for first time use in
//! a given hardware/software configuration.  This function should be called
//! before any other Ethernet API functions are called.
//!
//! The peripheral clock will be the same as the processor clock.  This will be
//! the value returned by SysCtlClockGet(), or it can be explicitly hard-coded
//! if it is constant and known (to save the code/execution overhead of a call
//! to SysCtlClockGet()).
//!
//! This function replaces the original EthernetInit() API and performs the
//! same actions.  A macro is provided in <tt>ethernet.h</tt> to map the
//! original API to this API.
//!
//! \note If the device configuration is changed (for example, the system clock
//! is reprogrammed to a different speed), then the Ethernet controller must be
//! disabled by calling the EthernetDisable() function and the controller must
//! be reinitialized by calling the EthernetInitExpClk() function again.  After
//! the controller has been reinitialized, the controller should be
//! reconfigured using the appropriate Ethernet API calls.
//!
//! \return None.
//
//*****************************************************************************
void
EthernetInitExpClk(unsigned long ulBase, unsigned long ulEthClk)
{
    unsigned long ulDiv;

    //
    // Check the arguments.
    //
    ASSERT(ulBase == ETH_BASE);

    //
    // Set the Management Clock Divider register for access to the PHY
    // register set (via EthernetPHYRead/Write).
    //
    // The MDC clock divided down from the system clock using the following
    // formula.  A maximum of 2.5MHz is allowed for F(mdc).
    //
    //      F(mdc) = F(sys) / (2 * (div + 1))
    //      div = (F(sys) / (2 * F(mdc))) - 1
    //      div = (F(sys) / 2 / F(mdc)) - 1
    //
    // Note: Because we should round up, to ensure we don't violate the
    // maximum clock speed, we can simplify this as follows:
    //
    //      div = F(sys) / 2 / F(mdc)
    //
    // For example, given a system clock of 6.0MHz, and a div value of 1,
    // the mdc clock would be programmed as 1.5 MHz.
    //
    ulDiv = (ulEthClk / 2) / 2500000;
    HWREG(ulBase + MAC_O_MDV) = (ulDiv & MAC_MDV_DIV_M);
}

//*****************************************************************************
//
//! Sets the configuration of the Ethernet controller.
//!
//! \param ulBase is the base address of the controller.
//! \param ulConfig is the configuration for the controller.
//!
//! After the EthernetInitExpClk() function has been called, this API function
//! can be used to configure the various features of the Ethernet controller.
//!
//! The Ethernet controller provides three control registers that are used
//! to configure the controller's operation.  The transmit control register
//! provides settings to enable full duplex operation, to auto-generate the
//! frame check sequence, and to pad the transmit packets to the minimum
//! length as required by the IEEE standard.  The receive control register
//! provides settings to enable reception of packets with bad frame check
//! sequence values and to enable multi-cast or promiscuous modes.  The
//! timestamp control register provides settings that enable support logic in
//! the controller that allow the use of the General Purpose Timer 3 to capture
//! timestamps for the transmitted and received packets.
//!
//! The \e ulConfig parameter is the logical OR of the following values:
//!
//! - \b ETH_CFG_TS_TSEN - Enable TX and RX interrupt status as CCP timer
//! inputs
//! - \b ETH_CFG_RX_BADCRCDIS - Disable reception of packets with a bad CRC
//! - \b ETH_CFG_RX_PRMSEN - Enable promiscuous mode reception (all packets)
//! - \b ETH_CFG_RX_AMULEN - Enable reception of multicast packets
//! - \b ETH_CFG_TX_DPLXEN - Enable full duplex transmit mode
//! - \b ETH_CFG_TX_CRCEN - Enable transmit with auto CRC generation
//! - \b ETH_CFG_TX_PADEN - Enable padding of transmit data to minimum size
//!
//! These bit-mapped values are programmed into the transmit, receive, and/or
//! timestamp control register.
//!
//! \return None.
//
//*****************************************************************************
void
EthernetConfigSet(unsigned long ulBase, unsigned long ulConfig)
{
    unsigned long ulTemp;

    //
    // Check the arguments.
    //
    ASSERT(ulBase == ETH_BASE);
    ASSERT((ulConfig & ~(ETH_CFG_TX_DPLXEN | ETH_CFG_TX_CRCEN |
                         ETH_CFG_TX_PADEN | ETH_CFG_RX_BADCRCDIS |
                         ETH_CFG_RX_PRMSEN | ETH_CFG_RX_AMULEN |
                         ETH_CFG_TS_TSEN)) == 0);

    //
    // Setup the Transmit Control Register.
    //
    ulTemp  = HWREG(ulBase + MAC_O_TCTL);
    ulTemp &= ~(MAC_TCTL_DUPLEX | MAC_TCTL_CRC | MAC_TCTL_PADEN);
    ulTemp |= ulConfig & 0x0FF;
    HWREG(ulBase + MAC_O_TCTL) = ulTemp;

    //
    // Setup the Receive Control Register.
    //
    ulTemp  = HWREG(ulBase + MAC_O_RCTL);
    ulTemp &= ~(MAC_RCTL_BADCRC | MAC_RCTL_PRMS | MAC_RCTL_AMUL);
    ulTemp |= (ulConfig >> 8) & 0x0FF;
    HWREG(ulBase + MAC_O_RCTL) = ulTemp;

    //
    // Setup the Time Stamp Configuration register.
    //
    ulTemp = HWREG(ulBase + MAC_O_TS);
    ulTemp &= ~(MAC_TS_TSEN);
    ulTemp |= (ulConfig >> 16) & 0x0FF;
    HWREG(ulBase + MAC_O_TS) = ulTemp;
}

//*****************************************************************************
//
//! Gets the current configuration of the Ethernet controller.
//!
//! \param ulBase is the base address of the controller.
//!
//! This function will query the control registers of the Ethernet controller
//! and return a bit-mapped configuration value.
//!
//! \sa The description of the EthernetConfigSet() function provides detailed
//! information for the bit-mapped configuration values that will be returned.
//!
//! \return Returns the bit-mapped Ethernet controller configuration value.
//
//*****************************************************************************
unsigned long
EthernetConfigGet(unsigned long ulBase)
{
    unsigned long ulConfig;

    //
    // Check the arguments.
    //
    ASSERT(ulBase == ETH_BASE);

    //
    // Read and return the Ethernet controller configuration parameters,
    // properly shifted into the appropriate bit field positions.
    //
    ulConfig = HWREG(ulBase + MAC_O_TS) << 16;
    ulConfig |= (HWREG(ulBase + MAC_O_RCTL) & ~(MAC_RCTL_RXEN)) << 8;
    ulConfig |= HWREG(ulBase + MAC_O_TCTL) & ~(MAC_TCTL_TXEN);
    return(ulConfig);
}

//*****************************************************************************
//
//! Sets the MAC address of the Ethernet controller.
//!
//! \param ulBase is the base address of the controller.
//! \param pucMACAddr is the pointer to the array of MAC-48 address octets.
//!
//! This function will program the IEEE-defined MAC-48 address specified in
//! \e pucMACAddr into the Ethernet controller.  This address is used by the
//! Ethernet controller for hardware-level filtering of incoming Ethernet
//! packets (when promiscuous mode is not enabled).
//!
//! The MAC-48 address is defined as 6 octets, illustrated by the following
//! example address.  The numbers are shown in hexadecimal format.
//!
//!         AC-DE-48-00-00-80
//!
//! In this representation, the first three octets (AC-DE-48) are the
//! Organizationally Unique Identifier (OUI).  This is a number assigned by
//! the IEEE to an organization that requests a block of MAC addresses.  The
//! last three octets (00-00-80) are a 24-bit number managed by the OUI owner
//! to uniquely identify a piece of hardware within that organization that is
//! to be connected to the Ethernet.
//!
//! In this representation, the octets are transmitted from left to right,
//! with the ``AC'' octet being transmitted first and the ``80'' octet being
//! transmitted last.  Within an octet, the bits are transmitted LSB to MSB.
//! For this address, the first bit to be transmitted would be ``0'', the LSB
//! of ``AC'', and the last bit to be transmitted would be ``1'', the MSB of
//! ``80''.
//!
//! \return None.
//
//*****************************************************************************
void
EthernetMACAddrSet(unsigned long ulBase, unsigned char *pucMACAddr)
{
    unsigned long ulTemp;
    unsigned char *pucTemp = (unsigned char *)&ulTemp;

    //
    // Check the arguments.
    //
    ASSERT(ulBase == ETH_BASE);
    ASSERT(pucMACAddr != 0);

    //
    // Program the MAC Address into the device.  The first four bytes of the
    // MAC Address are placed into the IA0 register.  The remaining two bytes
    // of the MAC address are placed into the IA1 register.
    //
    pucTemp[0] = pucMACAddr[0];
    pucTemp[1] = pucMACAddr[1];
    pucTemp[2] = pucMACAddr[2];
    pucTemp[3] = pucMACAddr[3];
    HWREG(ulBase + MAC_O_IA0) = ulTemp;
    ulTemp = 0;
    pucTemp[0] = pucMACAddr[4];
    pucTemp[1] = pucMACAddr[5];
    HWREG(ulBase + MAC_O_IA1) = ulTemp;
}

//*****************************************************************************
//
//! Gets the MAC address of the Ethernet controller.
//!
//! \param ulBase is the base address of the controller.
//! \param pucMACAddr is the pointer to the location in which to store the
//! array of MAC-48 address octets.
//!
//! This function will read the currently programmed MAC address into the
//! \e pucMACAddr buffer.
//!
//! \sa Refer to EthernetMACAddrSet() API description for more details about
//! the MAC address format.
//!
//! \return None.
//
//*****************************************************************************
void
EthernetMACAddrGet(unsigned long ulBase, unsigned char *pucMACAddr)
{
    unsigned long ulTemp;
    unsigned char *pucTemp = (unsigned char *)&ulTemp;

    //
    // Check the arguments.
    //
    ASSERT(ulBase == ETH_BASE);
    ASSERT(pucMACAddr != 0);

    //
    // Read the MAC address from the device.  The first four bytes of the
    // MAC address are read from the IA0 register.  The remaining two bytes
    // of the MAC addres
    //
    ulTemp = HWREG(ulBase + MAC_O_IA0);
    pucMACAddr[0] = pucTemp[0];
    pucMACAddr[1] = pucTemp[1];
    pucMACAddr[2] = pucTemp[2];
    pucMACAddr[3] = pucTemp[3];
    ulTemp = HWREG(ulBase + MAC_O_IA1);
    pucMACAddr[4] = pucTemp[0];
    pucMACAddr[5] = pucTemp[1];
}

//*****************************************************************************
//
//! Enables the Ethernet controller for normal operation.
//!
//! \param ulBase is the base address of the controller.
//!
//! Once the Ethernet controller has been configured using the
//! EthernetConfigSet() function and the MAC address has been programmed using
//! the EthernetMACAddrSet() function, this API function can be called to
//! enable the controller for normal operation.
//!
//! This function will enable the controller's transmitter and receiver, and
//! will reset the receive FIFO.
//!
//! \return None.
//
//*****************************************************************************
void
EthernetEnable(unsigned long ulBase)
{
    //
    // Check the arguments.
    //
    ASSERT(ulBase == ETH_BASE);

    //
    // Reset the receive FIFO.
    //
    HWREG(ulBase + MAC_O_RCTL) |= MAC_RCTL_RSTFIFO;

    //
    // Enable the Ethernet receiver.
    //
    HWREG(ulBase + MAC_O_RCTL) |= MAC_RCTL_RXEN;

    //
    // Enable Ethernet transmitter.
    //
    HWREG(ulBase + MAC_O_TCTL) |= MAC_TCTL_TXEN;

    //
    // Reset the receive FIFO again, after the receiver has been enabled.
    //
    HWREG(ulBase + MAC_O_RCTL) |= MAC_RCTL_RSTFIFO;
}

//*****************************************************************************
//
//! Disables the Ethernet controller.
//!
//! \param ulBase is the base address of the controller.
//!
//! When terminating operations on the Ethernet interface, this function should
//! be called.  This function will disable the transmitter and receiver, and
//! will clear out the receive FIFO.
//!
//! \return None.
//
//*****************************************************************************
void
EthernetDisable(unsigned long ulBase)
{
    //
    // Check the arguments.
    //
    ASSERT(ulBase == ETH_BASE);

    //
    // Reset the receive FIFO.
    //
    HWREG(ulBase + MAC_O_RCTL) |= MAC_RCTL_RSTFIFO;

    //
    // Disable the Ethernet transmitter.
    //
    HWREG(ulBase + MAC_O_TCTL) &= ~(MAC_TCTL_TXEN);

    //
    // Disable the Ethernet receiver.
    //
    HWREG(ulBase + MAC_O_RCTL) &= ~(MAC_RCTL_RXEN);

    //
    // Reset the receive FIFO again, after the receiver has been disabled.
    //
    HWREG(ulBase + MAC_O_RCTL) |= MAC_RCTL_RSTFIFO;
}

//*****************************************************************************
//
//! Check for packet available from the Ethernet controller.
//!
//! \param ulBase is the base address of the controller.
//!
//! The Ethernet controller provides a register that contains the number of
//! packets available in the receive FIFO.  When the last bytes of a packet are
//! successfully received (that is, the frame check sequence bytes), the packet
//! count is incremented.  Once the packet has been fully read (including the
//! frame check sequence bytes) from the FIFO, the packet count will be
//! decremented.
//!
//! \return Returns \b true if there are one or more packets available in the
//! receive FIFO, including the current packet being read, and \b false