📄 hw_ethernet.h
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#define PHY_MR3_OUI_S 10
#define PHY_MR3_MN_S 4
#define PHY_MR3_RN_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the PHY_MR4 register.
//
//*****************************************************************************
#define PHY_MR4_NP 0x00008000 // Next Page.
#define PHY_MR4_RF 0x00002000 // Remote Fault.
#define PHY_MR4_A3 0x00000100 // Technology Ability Field[3].
#define PHY_MR4_A2 0x00000080 // Technology Ability Field[2].
#define PHY_MR4_A1 0x00000040 // Technology Ability Field[1].
#define PHY_MR4_A0 0x00000020 // Technology Ability Field[0].
#define PHY_MR4_S_M 0x0000001F // Selector Field.
#define PHY_MR4_S_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the PHY_MR5 register.
//
//*****************************************************************************
#define PHY_MR5_NP 0x00008000 // Next Page.
#define PHY_MR5_ACK 0x00004000 // Acknowledge.
#define PHY_MR5_RF 0x00002000 // Remote Fault.
#define PHY_MR5_A_M 0x00001FE0 // Technology Ability Field.
#define PHY_MR5_S_M 0x0000001F // Selector Field.
#define PHY_MR5_S_8023 0x00000001 // IEEE Std 802.3
#define PHY_MR5_S_8029 0x00000002 // IEEE Std 802.9 ISLAN-16T
#define PHY_MR5_S_8025 0x00000003 // IEEE Std 802.5
#define PHY_MR5_S_1394 0x00000004 // IEEE Std 1394
#define PHY_MR5_A_S 5
//*****************************************************************************
//
// The following are defines for the bit fields in the PHY_MR6 register.
//
//*****************************************************************************
#define PHY_MR6_PDF 0x00000010 // Parallel Detection Fault.
#define PHY_MR6_LPNPA 0x00000008 // Link Partner is Next Page Able.
#define PHY_MR6_PRX 0x00000002 // New Page Received.
#define PHY_MR6_LPANEGA 0x00000001 // Link Partner is Auto-Negotiation
// Able.
//*****************************************************************************
//
// The following are defines for the bit fields in the MAC_O_DATA register.
//
//*****************************************************************************
#define MAC_DATA_TXDATA_M 0xFFFFFFFF // Transmit FIFO Data.
#define MAC_DATA_RXDATA_M 0xFFFFFFFF // Receive FIFO Data.
#define MAC_DATA_RXDATA_S 0
#define MAC_DATA_TXDATA_S 0
//*****************************************************************************
//
// The following are defines for the bit fields in the PHY_MR16 register.
//
//*****************************************************************************
#define PHY_MR16_RPTR 0x00008000 // Repeater Mode.
#define PHY_MR16_INPOL 0x00004000 // Interrupt Polarity.
#define PHY_MR16_TXHIM 0x00001000 // Transmit High Impedance Mode.
#define PHY_MR16_SQEI 0x00000800 // SQE Inhibit Testing.
#define PHY_MR16_NL10 0x00000400 // Natural Loopback Mode.
#define PHY_MR16_APOL 0x00000020 // Auto-Polarity Disable.
#define PHY_MR16_RVSPOL 0x00000010 // Receive Data Polarity.
#define PHY_MR16_PCSBP 0x00000002 // PCS Bypass.
#define PHY_MR16_RXCC 0x00000001 // Receive Clock Control.
//*****************************************************************************
//
// The following are defines for the bit fields in the PHY_MR17 register.
//
//*****************************************************************************
#define PHY_MR17_JABBER_IE 0x00008000 // Jabber Interrupt Enable.
#define PHY_MR17_RXER_IE 0x00004000 // Receive Error Interrupt Enable.
#define PHY_MR17_PRX_IE 0x00002000 // Page Received Interrupt Enable.
#define PHY_MR17_PDF_IE 0x00001000 // Parallel Detection Fault
// Interrupt Enable.
#define PHY_MR17_LPACK_IE 0x00000800 // LP Acknowledge Interrupt Enable.
#define PHY_MR17_LSCHG_IE 0x00000400 // Link Status Change Interrupt
// Enable.
#define PHY_MR17_RFAULT_IE 0x00000200 // Remote Fault Interrupt Enable.
#define PHY_MR17_ANEGCOMP_IE 0x00000100 // Auto-Negotiation Complete
// Interrupt Enable.
#define PHY_MR17_JABBER_INT 0x00000080 // Jabber Event Interrupt.
#define PHY_MR17_RXER_INT 0x00000040 // Receive Error Interrupt.
#define PHY_MR17_PRX_INT 0x00000020 // Page Receive Interrupt.
#define PHY_MR17_PDF_INT 0x00000010 // Parallel Detection Fault
// Interrupt.
#define PHY_MR17_LPACK_INT 0x00000008 // LP Acknowledge Interrupt.
#define PHY_MR17_LSCHG_INT 0x00000004 // Link Status Change Interrupt.
#define PHY_MR17_RFAULT_INT 0x00000002 // Remote Fault Interrupt.
#define PHY_MR17_ANEGCOMP_INT 0x00000001 // Auto-Negotiation Complete
// Interrupt.
//*****************************************************************************
//
// The following are defines for the bit fields in the PHY_MR18 register.
//
//*****************************************************************************
#define PHY_MR18_ANEGF 0x00001000 // Auto-Negotiation Failure.
#define PHY_MR18_DPLX 0x00000800 // Duplex Mode.
#define PHY_MR18_RATE 0x00000400 // Rate.
#define PHY_MR18_RXSD 0x00000200 // Receive Detection.
#define PHY_MR18_RX_LOCK 0x00000100 // Receive PLL Lock.
//*****************************************************************************
//
// The following are defines for the bit fields in the PHY_MR19 register.
//
//*****************************************************************************
#define PHY_MR19_TXO_M 0x0000C000 // Transmit Amplitude Selection.
#define PHY_MR19_TXO_00DB 0x00000000 // Gain set for 0.0dB of insertion
// loss
#define PHY_MR19_TXO_04DB 0x00004000 // Gain set for 0.4dB of insertion
// loss
#define PHY_MR19_TXO_08DB 0x00008000 // Gain set for 0.8dB of insertion
// loss
#define PHY_MR19_TXO_12DB 0x0000C000 // Gain set for 1.2dB of insertion
// loss
//*****************************************************************************
//
// The following are defines for the bit fields in the PHY_MR23 register.
//
//*****************************************************************************
#define PHY_MR23_LED1_M 0x000000F0 // LED1 Source.
#define PHY_MR23_LED1_LINK 0x00000000 // Link OK
#define PHY_MR23_LED1_RXTX 0x00000010 // RX or TX Activity (Default LED1)
#define PHY_MR23_LED1_TX 0x00000020 // TX Activity
#define PHY_MR23_LED1_RX 0x00000030 // RX Activity
#define PHY_MR23_LED1_COL 0x00000040 // Collision
#define PHY_MR23_LED1_100 0x00000050 // 100BASE-TX mode
#define PHY_MR23_LED1_10 0x00000060 // 10BASE-T mode
#define PHY_MR23_LED1_DUPLEX 0x00000070 // Full-Duplex
#define PHY_MR23_LED1_LINKACT 0x00000080 // Link OK & Blink=RX or TX
// Activity
#define PHY_MR23_LED0_M 0x0000000F // LED0 Source.
#define PHY_MR23_LED0_LINK 0x00000000 // Link OK (Default LED0)
#define PHY_MR23_LED0_RXTX 0x00000001 // RX or TX Activity
#define PHY_MR23_LED0_TX 0x00000002 // TX Activity
#define PHY_MR23_LED0_RX 0x00000003 // RX Activity
#define PHY_MR23_LED0_COL 0x00000004 // Collision
#define PHY_MR23_LED0_100 0x00000005 // 100BASE-TX mode
#define PHY_MR23_LED0_10 0x00000006 // 10BASE-T mode
#define PHY_MR23_LED0_DUPLEX 0x00000007 // Full-Duplex
#define PHY_MR23_LED0_LINKACT 0x00000008 // Link OK & Blink=RX or TX
// Activity
//*****************************************************************************
//
// The following are defines for the bit fields in the PHY_MR24 register.
//
//*****************************************************************************
#define PHY_MR24_PD_MODE 0x00000080 // Parallel Detection Mode.
#define PHY_MR24_AUTO_SW 0x00000040 // Auto-Switching Enable.
#define PHY_MR24_MDIX 0x00000020 // Auto-Switching Configuration.
#define PHY_MR24_MDIX_CM 0x00000010 // Auto-Switching Complete.
#define PHY_MR24_MDIX_SD_M 0x0000000F // Auto-Switching Seed.
#define PHY_MR24_MDIX_SD_S 0
//*****************************************************************************
//
// The following definitions are deprecated.
//
//*****************************************************************************
#ifndef DEPRECATED
//*****************************************************************************
//
// The following are deprecated defines for the MAC register offsets in the
// Ethernet Controller.
//
//*****************************************************************************
#define MAC_O_IS 0x00000000 // Interrupt Status Register
#define MAC_O_MADD 0x00000028 // Management Address Register
//*****************************************************************************
//
// The following are deprecated defines for the reset values of the MAC
// registers.
//
//*****************************************************************************
#define MAC_RV_MDV 0x00000080
#define MAC_RV_IM 0x0000007F
#define MAC_RV_THR 0x0000003F
#define MAC_RV_RCTL 0x00000008
#define MAC_RV_IA0 0x00000000
#define MAC_RV_TCTL 0x00000000
#define MAC_RV_DATA 0x00000000
#define MAC_RV_MRXD 0x00000000
#define MAC_RV_TR 0x00000000
#define MAC_RV_IS 0x00000000
#define MAC_RV_NP 0x00000000
#define MAC_RV_MCTL 0x00000000
#define MAC_RV_MTXD 0x00000000
#define MAC_RV_IA1 0x00000000
#define MAC_RV_IACK 0x00000000
#define MAC_RV_MADD 0x00000000
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the MAC_IS
// register.
//
//*****************************************************************************
#define MAC_IS_PHYINT 0x00000040 // PHY Interrupt
#define MAC_IS_MDINT 0x00000020 // MDI Transaction Complete
#define MAC_IS_RXER 0x00000010 // RX Error
#define MAC_IS_FOV 0x00000008 // RX FIFO Overrun
#define MAC_IS_TXEMP 0x00000004 // TX FIFO Empy
#define MAC_IS_TXER 0x00000002 // TX Error
#define MAC_IS_RXINT 0x00000001 // RX Packet Available
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the MAC_IA0
// register.
//
//*****************************************************************************
#define MAC_IA0_MACOCT4 0xFF000000 // 4th Octet of MAC address
#define MAC_IA0_MACOCT3 0x00FF0000 // 3rd Octet of MAC address
#define MAC_IA0_MACOCT2 0x0000FF00 // 2nd Octet of MAC address
#define MAC_IA0_MACOCT1 0x000000FF // 1st Octet of MAC address
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the MAC_IA1
// register.
//
//*****************************************************************************
#define MAC_IA1_MACOCT6 0x0000FF00 // 6th Octet of MAC address
#define MAC_IA1_MACOCT5 0x000000FF // 5th Octet of MAC address
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the MAC_TXTH
// register.
//
//*****************************************************************************
#define MAC_THR_THRESH 0x0000003F // Transmit Threshold Value
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the MAC_MCTL
// register.
//
//*****************************************************************************
#define MAC_MCTL_REGADR 0x000000F8 // Address for Next MII Transaction
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the MAC_MDV
// register.
//
//*****************************************************************************
#define MAC_MDV_DIV 0x000000FF // Clock Divider for MDC for TX
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the MAC_MTXD
// register.
//
//*****************************************************************************
#define MAC_MTXD_MDTX 0x0000FFFF // Data for Next MII Transaction
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the MAC_MRXD
// register.
//
//*****************************************************************************
#define MAC_MRXD_MDRX 0x0000FFFF // Data Read from Last MII Trans.
//*****************************************************************************
//
// The following are deprecated defines for the bit fields in the MAC_NP
// register.
//
//*****************************************************************************
#define MAC_NP_NPR 0x0000003F // Number of RX Frames in FIFO
#endif
#endif // __HW_ETHERNET_H__
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