f2407.h

2407的例子代码

#define    MBX1D     (unsigned int*) 0x720F   //CAN 2 of 8 bytes of mailbox 1

#define    MSGID2L   (unsigned int*) 0x7210   //CAN message ID for mailbox 2 (lower 16 bits)
#define    MSGID2   (unsigned int*) 0x7211   //CAN message ID for mailbox 2 (upper 16 bits)
#define    MSGCTRL2  (unsigned int*) 0x7212   //CAN RTR and DLC for mailbox 2
#define    MBX2A     (unsigned int*) 0x7214   //CAN 2 of 8 bytes of mailbox 2
#define    MBX2B     (unsigned int*) 0x7215   //CAN 2 of 8 bytes of mailbox 2
#define    MBX2C     (unsigned int*) 0x7216   //CAN 2 of 8 bytes of mailbox 2
#define    MBX2D     (unsigned int*) 0x7217   //CAN 2 of 8 bytes of mailbox 2

#define    MSGID3L   (unsigned int*) 0x7218   //CAN message ID for mailbox 3 (lower 16 bits)
#define    MSGID3   (unsigned int*) 0x7219   //CAN message ID for mailbox 3 (upper 16 bits)
#define    MSGCTRL3  (unsigned int*) 0x721A   //CAN RTR and DLC for mailbox 3
#define    MBX3A     (unsigned int*) 0x721C   //CAN 2 of 8 bytes of mailbox 3
#define    MBX3B     (unsigned int*) 0x721D   //CAN 2 of 8 bytes of mailbox 3
#define    MBX3C     (unsigned int*) 0x721E   //CAN 2 of 8 bytes of mailbox 3
#define    MBX3D     (unsigned int*) 0x721F   //CAN 2 of 8 bytes of mailbox 3

#define    MSGID4L   (unsigned int*) 0x7220   //CAN message ID for mailbox 4 (lower 16 bits)
#define    MSGID4   (unsigned int*) 0x7221   //CAN message ID for mailbox 4 (upper 16 bits)
#define    MSGCTRL4  (unsigned int*) 0x7222   //CAN RTR and DLC for mailbox 4
#define    MBX4A     (unsigned int*) 0x7224   //CAN 2 of 8 bytes of mailbox 4
#define    MBX4B     (unsigned int*) 0x7225   //CAN 2 of 8 bytes of mailbox 4
#define    MBX4C     (unsigned int*) 0x7226   //CAN 2 of 8 bytes of mailbox 4
#define    MBX4D     (unsigned int*) 0x7227   //CAN 2 of 8 bytes of mailbox 4

#define    MSGID5L   (unsigned int*) 0x7228   //CAN message ID for mailbox 5 (lower 16 bits)
#define    MSGID5   (unsigned int*) 0x7229   //CAN message ID for mailbox 5 (upper 16 bits)
#define    MSGCTRL5  (unsigned int*) 0x722A   //CAN RTR and DLC for mailbox 5
#define    MBX5A     (unsigned int*) 0x722C   //CAN 2 of 8 bytes of mailbox 5
#define    MBX5B     (unsigned int*) 0x722D   //CAN 2 of 8 bytes of mailbox 5
#define    MBX5C     (unsigned int*) 0x722E   //CAN 2 of 8 bytes of mailbox 5
#define    MBX5D     (unsigned int*) 0x722F   //CAN 2 of 8 bytes of mailbox 5

//Event Manager A (EVA) registers
#define    GPTCONA   (unsigned int*) 0x7400   //GP timer control reg A  
#define    T1CNT     (unsigned int*) 0x7401   //GP timer 1 counter reg 
#define    T1CMPR    (unsigned int*) 0x7402   //GP timer 1 compare reg 
#define    T1PR      (unsigned int*) 0x7403   //GP timer 1 period reg 
#define    T1CON     (unsigned int*) 0x7404   //GP timer 1 control reg 
#define    T2CNT     (unsigned int*) 0x7405   //GP timer 2 counter reg 
#define    T2CMPR    (unsigned int*) 0x7406   //GP timer 2 compare reg 
#define    T2PR      (unsigned int*) 0x7407   //GP timer 2 period reg 
#define    T2CON     (unsigned int*) 0x7408   //GP timer 2 control reg 
#define    COMCONA   (unsigned int*) 0x7411   //Compare control reg A
#define    ACTRA     (unsigned int*) 0x7413   //Compare action control reg A
#define    DBTCONA   (unsigned int*) 0x7415   //Dead-band timer control reg A 
#define    CMPR1     (unsigned int*) 0x7417   //compare reg 1 
#define    CMPR2     (unsigned int*) 0x7418   //compare reg 2 
#define    CMPR3     (unsigned int*) 0x7419   //compare reg 3 
#define    CAPCONA   (unsigned int*) 0x7420   //Capture control reg A 
#define    CAPFIFOA  (unsigned int*) 0x7422   //Capture FIFO status reg A 
#define    CAP1FIFO  (unsigned int*) 0x7423   //Capture Channel 1 FIFO top 
#define    CAP2FIFO  (unsigned int*) 0x7424   //Capture Channel 2 FIFO top 
#define    CAP3FIFO  (unsigned int*) 0x7425   //Capture Channel 3 FIFO top 
#define    CAP1FBOT  (unsigned int*) 0x7427   //Bottom reg of capture FIFO stack 1 
#define    CAP2FBOT  (unsigned int*) 0x7427   //Bottom reg of capture FIFO stack 2 
#define    CAP3FBOT  (unsigned int*) 0x7427   //Bottom reg of capture FIFO stack 3 
#define    EVAIMRA   (unsigned int*) 0x742C   //EVA interrupt mask reg A
#define    EVAIMRB   (unsigned int*) 0x742D   //EVA interrupt mask reg B
#define    EVAIMRC   (unsigned int*) 0x742E   //EVA interrupt mask reg C
#define    EVAIFRA   (unsigned int*) 0x742F   //EVA interrupt flag reg A
#define    EVAIFRB   (unsigned int*) 0x7430   //EVA interrupt flag reg B
#define    EVAIFRC   (unsigned int*) 0x7431   //EVA interrupt flag reg C

//Event Manager B (EVB) registers
#define    GPTCONB   (unsigned int*) 0x7500   //GP timer control reg B 
#define    T3CNT     (unsigned int*) 0x7501   //GP timer 3 counter reg
#define    T3CMPR    (unsigned int*) 0x7502   //GP timer 3 compare reg
#define    T3PR      (unsigned int*) 0x7503   //GP timer 3 period reg
#define    T3CON     (unsigned int*) 0x7504   //GP timer 3 control reg
#define    T4CNT     (unsigned int*) 0x7505   //GP timer 4 counter reg
#define    T4CMPR    (unsigned int*) 0x7506   //GP timer 4 compare reg
#define    T4PR      (unsigned int*) 0x7507   //GP timer 4 period reg
#define    T4CON     (unsigned int*) 0x7508   //GP timer 4 control reg
#define    COMCONB   (unsigned int*) 0x7511   //Compare control register B
#define    ACTRB     (unsigned int*) 0x7513   //Compare action control register B
#define    DBTCONB   (unsigned int*) 0x7515   //Dead-band timer control reg B
#define    CMPR4     (unsigned int*) 0x7517   //Compare reg 4 
#define    CMPR5     (unsigned int*) 0x7518   //Compare reg 5
#define    CMPR6     (unsigned int*) 0x7519   //Compare reg 6
#define    CAPCONB   (unsigned int*) 0x7520   //Capture control reg B 
#define    CAPFIFOB  (unsigned int*) 0x7522   //Capture FIFO status reg B
#define    CAP4FIFO  (unsigned int*) 0x7523   //Capture channel 4 FIFO top 
#define    CAP5FIFO  (unsigned int*) 0x7524   //Capture channel 5 FIFO top 
#define    CAP6FIFO  (unsigned int*) 0x7525   //Capture channel 6 FIFO top 
#define    CAP4FBOT  (unsigned int*) 0x7527   //Bottom reg of capture FIFO stack 4 
#define    CAP5FBOT  (unsigned int*) 0x7527   //Bottom reg of capture FIFO stack 5 
#define    CAP6FBOT  (unsigned int*) 0x7527   //Bottom reg of capture FIFO stack 6 
#define    EVBIMRA   (unsigned int*) 0x752C   //EVB interrupt mask reg A
#define    EVBIMRB   (unsigned int*) 0x752D   //EVB interrupt mask reg B
#define    EVBIMRC   (unsigned int*) 0x752E   //EVB interrupt mask reg C
#define    EVBIFRA   (unsigned int*) 0x752F   //EVB interrupt flag reg A
#define    EVBIFRB   (unsigned int*) 0x7530   //EVB interrupt flag reg B
#define    EVBIFRC   (unsigned int*) 0x7531   //EVB interrupt flag reg C

//I/O space mapped registers
#define    FCMR      portff0f  //Flash control mode reg
#define    WSGR      portffff  //Wait-state generator reg
ioport     FCMR;     //Flash control mode register
ioport     WSGR;     //Wait-state generator control register
//************************************************
//Other useful definitions below (not addresses) *
//************************************************
//Bit codes for test bit instruction (BIT)
#define BIT0    0x0001
#define BIT1    0x0002
#define BIT2    0x0004
#define BIT3    0x0008
#define BIT4    0x0010
#define BIT5    0x0020
#define BIT6    0x0040
#define BIT7    0x0080
#define BIT8    0x0100
#define BIT9    0x0200
#define BIT10   0x0400
#define BIT11   0x0800
#define BIT12   0x1000
#define BIT13   0x2000
#define BIT14   0x4000
#define BIT15   0x8000

//////////////////////////////////////////////////////////////////////////
#define SetRegBit(ADDR,BITi) (*((unsigned int*)(ADDR))|=(BITi))
#define ClrRegBit(ADDR,BITi) (*((unsigned int*)(ADDR))&=(~BITi))
#endif