📄 rsim_params
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##### Global Parameters #####numnodes 1 # number of nodesnumcpus 1 # number of processors per nodekernel ../../lamix/lamix # Lamix kernel filenamememory 512M # size of memory, affects only file cache size##### CPU Parameters #####clkperiod 5000 # CPU clock period in picosecondsactivelist 64 # number of active instruction, ROB sizefetchqueue 8 # size of fetch queue/instruction bufferfetchrate 4 # instructions fetched per cycledecoderate 4 # instructions decoded per cyclegraduationrate 4 # instructions graduated per cycleflushrate 4 # instructions flushed per cycle after except.maxaluops 16 # maximum number of pending ALU instructionsmaxfpuops 16 # maximum number of pending FPU instructionsmaxmemops 16 # maximum number of pending memory instructionsshadowmappers 8 # number of unresolved branchesbpbtype 2bit # type of branch predictor (2bit,agree,static)bpbsize 512 # size of branch predictor bufferrassize 4 # size of return address stacklatint 1 # integer instruction latencylatshift 1 # integer shift latencylatmul 3 # integer multiply latencylatdiv 9 # integer divide latencylatflt 3 # floating point operation latencylatfconv 4 # FP conversion latencylatfmov 1 # FP move latencylatfdiv 10 # FP divide latencylatfsqrt 10 # FP sqare root latencyrepint 1 # integer instruction repeat raterepshift 1 # integer shift repeat raterepmul 1 # integer multiply repeat raterepdiv 1 # integer divide repeat raterepflt 1 # FP instruction repeat raterepfconv 2 # FP conversion repeat raterepfmov 1 # FP move repeat raterepfdiv 6 # FP divide repeat raterepfsqrt 6 # FP suare root repeat ratenumaddrs 1 # number of address generation unitsnumalus 2 # number of integer functional unitsnumfpus 2 # number of FP functional unitsstorebuffer 16 # size of processor store bufferdtlbtype direct # data TLB type (direct, set_assoc, # fully_assoc,perfect)dtlbsize 128 # data TLB sizedtlbassoc 1 # data TLB associativitydtlbtag 0 # enable tagged data TLBitlbtype direct # instr.TLB type (direct, set_assoc, # fully_assoc, perfect)itlbsize 128 # instr. TLB sizeitlbassoc 1 # instr. TLB associativityitlbtag 0 # enable tagged instr. TLB##### Cache Parameters #####cache_frequency 1 # frequency relative to CPU corecache_collect_stats 1 # collect statisticscache_mshr_coal 8 # max. number of misses coalesced into a MSHRL1IC_perfect 0 # perfect L1 I-cache (100% hit rate)L1IC_prefetch 0 # L1 I-cache prefetches next line on missL1IC_size 32 # L1 I-cache cache size in kbytesL1IC_assoc 1 # L1 I-Cache associativityL1IC_line_size 32 # L1 I-cache line size in bytesL1IC_ports 1 # number of L1 I-cache portsL1IC_tag_latency 1 # L1 I-cache access latencyL1IC_tag_repeat 1 # L1 I-cache access repeat rateL1IC_mshr 8 # L1 I-cache miss status holding register sizeL1DC_perfect 0 # perfect L1 D-cache (100% hit rate)L1DC_prefetch 0 # L1 D-cache prefetches next line on missL1DC_writeback 1 # L1 D-cache writeback/writethrough?L1DC_wbuf_size 8 # size of L1 D-cache write buferL1DC_size 32 # L1 D-cache cache size in kbytesL1DC_assoc 1 # L1 D-Cache associativityL1DC_line_size 32 # L1 D-cache line size in bytesL1DC_ports 1 # number of L1 D-cache portsL1DC_tag_latency 1 # L1 D-cache access latencyL1DC_tag_repeat 1 # L1 D-cache access repeat rateL1DC_mshr 8 # L1 D-cache miss status holding register sizeL2C_perfect 0 # perfect L2 cacheL2C_prefetch 0 # L2 cache prefetches next line on missL2C_size 512 # L2 cache size in kbytesL2C_assoc 4 # L2 cache associativityL2C_line_size 128 # L2 cache line sizeL2C_ports 1 # number of L2 cache portsL2C_tag_latency 3 # L2 cache tag access delayL2C_tag_repeat 1 # L2 cache tag access repeat rateL2C_data_latency 5 # L2 cache data access delayL2C_data_repeat 1 # L2 cache data access repeat rateL2C_mshr 8 L2 cache miss status holding register size##### Uncached Buffer Parameters #####ubuftype comb # combining or nocombining bufferubufsize 8 # number of uncache buffer entriesubufflush 1 # threshold to flush uncached bufferubufentrysize 8 # size of uncached buffer entry in 32 bit words##### Bus Parameters #####bus_frequency 1 # bus frequency relative to CPU corebus_width 8 # bus width in bytesbus_arbdelay 1 # arbitration delay in cyclesbus_turnaround 1 # number of turnaround cyclesbus_mindelay 0 # minimum delay between start of transactionsbus_critical 1 # enable critical-word-first transferbus_total_requests 8 # number of outstanding split-transaction reqs.bus_cpu_requests 4 # number of outstanding CPU requests (per CPU)bus_io_requests 4 # number of outstanding I/O requests (per I/O)##### General I/O Parameters #####io_latency 1 # latency of I/O device bus interface # including PCI bridge and bus##### Realtime Clock Parameters ####rtc_start_date 9/10/2000 # initial date of realtime clockrtc_start_time 13:58:29 # initial time of realtime clock##### SCSI Controller Parameters #####numscsi 1 # number of SCSI controllers per nodeahc_scbs 32 # number of control blocks on Adaptec cntrl.##### SCSI Bus Parameters #####scsi_frequency 10 # SCSI bus frequency in MHzscsi_width 2 # SCSI bus width in bytesscsi_arb_delay 24 # SCSI bus arbitration delay in bus cyclesscsi_bus_free 8 # minimum SCSI bus free time in cyclesscsi_req_delay 13 # lumped delay to transfer a request in cyclesscsi_timeout 10000 # SCSI bus timeout in cycles##### SCSI Disk Parameters #####numdisks 1 # number disks per SCSI busdisk_params <none> # disk parameter file namedisk_name IBM/Ultrastar_9LP # name of disk modeldisk_seek_single 0.7 # single-track seek timedisk_seek_av 6.5 # average seek timedisk_seek_full 14.0 # full stroke seek timedisk_seek_method disk_seek_curve # method to model seek time # disk_seek_none, disk_seek_const, # disk_seek_line, disk_seek_curvedisk_write_settle 1.3 # write settle timedisk_head_switch 0.85 # head switch timedisk_cntl_ov 40 # controller overhead in microsecondsdisk_rpm 7200 # rotational speeddisk_cyl 8420 # number of cylindersdisk_heads 10 # number of headsdisk_sect 209 # number of sectors per trackdisk_cylinder_skew 20 # cylinder skew in sectorsdisk_track_skew 35 # track skew in sectorsdisk_request_q 32 # request queue sizedisk_response_q 32 # response queue sizedisk_cache_size 1024 # disk cache size in kbytesdisk_cache_seg 16 # number of cache segmentsdisk_cache_write_seg 2 # number of write segmentsdisk_prefetch 1 # enable prefetchingdisk_fast_write 0 # enable fast writesdisk_buffer_full 0.75 # buffer full ratio to disconnectdisk_buffer_empty 0.75 # buffer empty ratio to reconnect##### Main Memory Controller Parameters #####mmc_sim_on 1 # enable detailed memory simulation # alternative name: mmc_sim # alternative values: fixed, pipelined, detailedmmc_latency 20 # fixed latency if detailed sim. is turned offmmc_frequency 1 # memory controller frequency relative to CPUmmc_debug 0 # enable debugging outputmmc_collect_stats 1 # collect statisticsmmc_writebacks ? # number of buffered writebacks # default is numcpus + number of coherent I/Os### DRAM backend parametersdram_sim_on 1 # enable detailed DRAM simulationdram_latency 18 # fixed latency if detailed sim. is turned offdram_frequency 1 # DRAM frequency relative to CPUdram_scheduler 1 # enable detailed DRAM timingdram_debug 0 # enable debug outputdram_collect_stats 1 # collect statisticsdram_trace_on 0 # enable trace collectiondram_trace_max 0 # set upper limit on number of trace itemsdram_trace_file dram_trace # name of trace filedram_num_smcs 4 # num. data buffers/multiplexers & data bussesdram_num_jetways 2 # number of data buffers/multiplexersdram_num_banks 16 # number of physical DRAM banksdram_banks_per_chip 2 # number of chip-internal banksdram_rd_busses 4 # number of data bussesdram_sa_bus_cycles 1 # number of cycles of an address bus transferdram_sd_bus_cycles 1 # number of cycles of a data bus item transferdram_sd_bus_width 32 # width of data bus in bitsdram_critical_word 1 # enable critical-word-first transferdram_bank_depth 16 # size of request queue in SMCdram_interleaving 0 # block/cacheline and cont/modulodram_max_bwaiters 256 # number of outstanding requestsdram_hotrow_policy 0 # open-row policydram_width 16 # width of DRAM chip = width of DRAM data busdram_mini_access 16 # minimum DRAM access sizedram_block_size 128 # block interleaving sizedram_type SDRAM # type of DRAM (SDRAM or RDRAM)### SDRAM Parameterssdram_tCCD 1 # CAS to CAS delaysdram_tRRD 2 # bank to bank delaysdram_tRP 3 # precharge timesdram_tRAS 7 # RAS latency, row access timesdram_tRCD 3 # RAS to CAS delaysdram_tAA 3 # CAS latency, column access timesdram_tDAL 5 # data-in to precharge timesdram_tDPL 2 # data-in to active timesdram_tPACKET 1 # number of cycles to transfer one 'packet'sdram_row_size 512 # size of an open row in bytessdram_row_hold_time 750000 # maximum time to keep row opensdram_refresh_delay 2048 # number of cycles for one refreshsdram_refresh_period 750000 # refresh period in cycles ### RDRAM Parametersrdram_tRC 28 # delay between ACT commandsrdram_tRR 8 # delay between RD commandsrdram_tRP 8 # delay between PRER and ACT commandrdram_tCBUB1 4 # read to write command delayrdram_tCBUB2 8 # write to read command delayrdram_tRCD 7 # RAS to CAS delayrdram_tCAC 8 # CAS delay (ACT to data-out)rdram_tCWD 6 # CAS to write delayrdram_tPACKET 4 # number of cycles to transfer one packetrdram_row_size 512 # size of an open row in bytesrdram_row_hold_time 750000 # maximum time to keep row openrdram_refresh_delay 2048 # number of cycles for one refreshrdram_refresh_period 750000 # refresh periods in cycles⌨️ 快捷键说明
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