procstate.h

ml-rsim 多处理器模拟器 支持类bsd操作系统

/*
 * Copyright (c) 2002 The Board of Trustees of the University of Illinois and
 *                    William Marsh Rice University
 * Copyright (c) 2002 The University of Utah
 * Copyright (c) 2002 The University of Notre Dame du Lac
 *
 * All rights reserved.
 *
 * Based on RSIM 1.0, developed by:
 *   Professor Sarita Adve's RSIM research group
 *   University of Illinois at Urbana-Champaign and
     William Marsh Rice University
 *   http://www.cs.uiuc.edu/rsim and http://www.ece.rice.edu/~rsim/dist.html
 * ML-RSIM/URSIM extensions by:
 *   The Impulse Research Group, University of Utah
 *   http://www.cs.utah.edu/impulse
 *   Lambert Schaelicke, University of Utah and University of Notre Dame du Lac
 *   http://www.cse.nd.edu/~lambert
 *   Mike Parker, University of Utah
 *   http://www.cs.utah.edu/~map
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal with the Software without restriction, including without
 * limitation the rights to use, copy, modify, merge, publish, distribute,
 * sublicense, and/or sell copies of the Software, and to permit persons to
 * whom the Software is furnished to do so, subject to the following
 * conditions:
 *
 * 1. Redistributions of source code must retain the above copyright notice,
 *    this list of conditions and the following disclaimers. 
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimers in the
 *    documentation and/or other materials provided with the distribution.
 * 3. Neither the names of Professor Sarita Adve's RSIM research group,
 *    the University of Illinois at Urbana-Champaign, William Marsh Rice
 *    University, nor the names of its contributors may be used to endorse
 *    or promote products derived from this Software without specific prior
 *    written permission. 
 * 4. Neither the names of the ML-RSIM project, the URSIM project, the
 *    Impulse research group, the University of Utah, the University of
 *    Notre Dame du Lac, nor the names of its contributors may be used to
 *    endorse or promote products derived from this software without specific
 *    prior written permission. 
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS WITH THE SOFTWARE. 
 */

#ifndef __RSIM_PROCSTATE_H__
#define __RSIM_PROCSTATE_H__


#define SIZE_OF_SPARC_INSTRUCTION       4

#undef PAGE_SIZE
#define PAGE_SIZE                    0x00001000


#ifdef __cplusplus

#include <stdio.h>
#include <stdlib.h>
#include <memory.h>
#include <time.h>

#include "Processor/proc_config.h"
#include "Processor/registers.h"
#include "Processor/funcunits.h"
#include "Processor/instruction.h"
#include "Processor/instance.h"
#include "Processor/heap.h"
#include "Processor/hash.h"
#include "Processor/allocator.h"
#include "Processor/memq.h"
#include "Processor/fetch_queue.h"
#include "Processor/queue.h"
#include "Processor/stallq.h"
#include "Processor/tagcvt.h"
#include "Processor/circq.h"
#include "Processor/active.h"
#include "Processor/freelist.h"
#include "Processor/tlb.h"
#include "Processor/pagetable.h"

extern "C"
{
#include "Caches/system.h"
#include "Caches/req.h"
#include "Caches/cache.h"
} 



struct MapTable;
struct BranchQElement;

extern int  DEBUG_TIME;  /* time to enable debugging on */

extern ProcState **AllProcs;
extern int       aliveprocs;


extern int MAX_ACTIVE_NUMBER; // Maximum number of elements in the active list
extern int MAX_ACTIVE_INSTS;

#define MAX_MAX_ACTIVE_NUMBER 4096 

extern int FETCH_QUEUE_SIZE;    // 8

extern int FETCHES_PER_CYCLE;   // 4
extern int DECODES_PER_CYCLE;   // 4
extern int GRADUATES_PER_CYCLE; // 4
extern int EXCEPT_FLUSHES_PER_CYCLE;

extern int MAX_SPEC;            // Maximum number of speculations allowed

extern int MAX_ALU_OPS;         // max unissued integer ops in proc at a time 
extern int MAX_FPU_OPS;         // max unissued FP ops in proc at a time 
extern int MAX_MEM_OPS;         // max mem ops in mem queue 
extern int MAX_STORE_BUF;       // max number of unissued stores


/* number of functional units of each type */
extern int ALU_UNITS, FPU_UNITS, MEM_UNITS, ADDR_UNITS;


#define DEFMAX_ALU_OPS        16
#define DEFMAX_FPU_OPS        16
#define DEFMAX_MEM_OPS 	      16
#define DEFMAX_STORE_BUF      16

#define MAX_NUM_WINS 32
#define MIN_NUM_WINS 4
#define MAX_NUM_TRAPS 16


#define NO_OF_LOG_INT_REGS (MAX_NUM_WINS*16 + MAX_NUM_TRAPS*4 + END_OF_REGISTERS - 20)
#define NO_OF_LOG_FP_REGS  32 
#define NO_OF_PHY_INT_REGS (NO_OF_LOG_INT_REGS + MAX_ACTIVE_NUMBER)
#define NO_OF_PHY_FP_REGS  (NO_OF_LOG_FP_REGS + MAX_ACTIVE_NUMBER)



/******************************************************************/
/****************** MembarInfo structure definition ***************/
/******************************************************************/
struct MembarInfo
{
  long long tag;        /* instruction tag                        */
  int SS;               /* store store membar?                    */
  int LS;               /* load store membar?                     */
  int SL;               /* store load membar?                     */
  int LL;               /* load load membar?                      */
  int MEMISSUE;         /* blocks all memory issue                */
  int SYNC;             /* blocks instruction initiation (decode) */
  
  int operator == (struct MembarInfo x)
  {
    return tag == x.tag;
  } 

  int operator <= (struct MembarInfo x)
  {
    return tag <= x.tag;
  }
  
  int operator >= (struct MembarInfo x)
  {
    return tag >= x.tag;
  }
  
  int operator < (struct MembarInfo x)
  {
    return tag < x.tag;
  }
  
  int operator > (struct MembarInfo x)
  {
    return tag > x.tag;
  }
  
  int operator != (struct MembarInfo x)
  {
    return tag != x.tag;
  }
};


/******************************************************************/
/****************** Some useful structure definition **************/
/******************************************************************/

/*
 * tagged_inst structure definition.
 * Used for detecting changes to instance tag 
 */
struct tagged_inst
{
  instance *inst;
  long long inst_tag;

  tagged_inst() {}

  tagged_inst(instance * i):inst(i), inst_tag(i->tag) {}

  int ok() const 
  {
    return inst_tag == inst->tag;
  }
};


/* 
 * Statistics: Efficiency characterization. For more details, refer to
 *  BennetFlynn1995  TR 
 */
enum eff_loss_stall
{
  eNOEFF_LOSS,      /* no efficiency loss                      */
  eBR,              /* branch-related efficiency losses        */
  eBADBR,           /* branch-related efficiency losses        */
  eSHADOW,          /* loss due to shadow mappers full         */
  eRENAME,          /* loss due to inadequate rename           */
  eMEMQFULL,        /* loss due to memory queue full           */
  eISSUEQFULL,      /* loss due to issue queue full            */
  eNUM_EFF_STALLS   /* number of classes of efficiency loss    */
};


/********************************************************************/
/******************* ProcState class  definition ********************/
/********************************************************************/

struct ProcState
{
  /* The ProcState class represents the state of an individual processor, 
     and is separate for the different processors in the MP case   */

  static int  numprocs;            /* number of processors                 */

  
  /****************** Configuraton parameter ********************/

  int         proc_id;             /* processor id                         */
  int         fetch_rate;          /* instruction fetches per cycle        */
  int         decode_rate;         /* decode rate of proc                  */
  int         graduate_rate;       /* graduate rate of proc                */
  int         max_active_list;     /* instruction window size              */
  FILE       *corefile;            /* corefile file pointer                */

  
  /****************** ???????????  ********************/
  
  long long   instruction_count;   /* total number of instructions         */
  long long   graduation_count;    /* number of graduated instrns          */
  long long   curr_cycle;          /* current simulated cycle              */

  page_table *PageTable;


  /******** instruction fetching, decoding, and graduation *******/

  int         halt;                /* halt processor until next interrupt  */
  
  unsigned    pc;                  /* the current pc                       */
  unsigned    npc;                 /* the next pc to fetch from            */

  unsigned    pstate;              /* copies of supervisor state registers */
  int         tl;                  /* for faster access                    */
  int         pil;
  int         itlb_random;
  int         itlb_wired;
  int         dtlb_random;
  int         dtlb_wired;