tlb.cc

ml-rsim 多处理器模拟器 支持类bsd操作系统

	  data = entries[index].data;
	  ctx  = entries[index].context;
	  
	  if ((tlb_tag(tag) == tlb_tag(addr)) &&
	      tlb_valid(tag) &&
	      ((tagged && ctx == context) || !tagged))
	    {
	      *attributes = tlb_attr(data);

	      if (write && tlb_rdonly(data))
		return(TLB_FAULT);

	      if (!priv && tlb_priv(data))
		return(TLB_FAULT);
	      
              if (tlb_mvalid(data))
		*address = tlb_data(data) | tlb_offset(addr);
	      else
		return(TLB_FAULT);

	      return(TLB_HIT);
	    }
	  
	  n++;
	  index = (index + 1) % size;
	}
      while (n < size);

      //-----------------------------------------------------------------------
      // not found:
      // read L0 page table entry (context + upper 10 address bits)
      data = tlb_read_word(proc, instr_tag,
			   proc->log_int_reg_file[arch_to_log(proc,
							      proc->cwp,
							      PRIV_TLB_CONTEXT)] +
			   (addr >> 20) & ~3);
      if (!tlb_mvalid(data))           // L0 entry not valid: fault
	return(TLB_FAULT);

      // read L1 entry (L0 + middle 10 address bits)
      data = tlb_read_word(proc, instr_tag,
			   (data & ~3) | ((addr >> 10) & 0xFFC));
      if (!tlb_mvalid(data))           // L1 not valid: fault
	return(TLB_FAULT);

      entries[index].tag     = (addr & ~(PAGE_SIZE-1)) | 1;
      entries[index].data    = data;
      entries[index].context = context;

      if (write && tlb_rdonly(data))
	return(TLB_FAULT);

      if (!priv && tlb_priv(data))
	return(TLB_FAULT);

      *attributes = tlb_attr(data);
      *address = tlb_data(data) | tlb_offset(addr);

      return(TLB_HIT);


      
      //-----------------------------------------------------------------------
      // fully associative TLB
      // search through entire TLB

    case TLB_FULLY_ASSOC:
      n = 0;
      do
	{
	  tag  = entries[index].tag;
	  data = entries[index].data;
	  ctx  = entries[index].context;

	  if ((tlb_tag(tag) == tlb_tag(addr)) &&
	      tlb_valid(tag) &&
	      ((tagged && ctx == context) || !tagged))
	    {
	      *attributes = tlb_attr(data);

	      if (write && tlb_rdonly(data))
		return(TLB_FAULT);

	      if (!priv && tlb_priv(data))
		return(TLB_FAULT);

              if (tlb_mvalid(data))
		*address = tlb_data(data) | tlb_offset(addr);
	      else
		return(TLB_FAULT);

	      return(TLB_HIT);
	    }
	  
	  n++;
	  index = (index + 1) % size;
	}
      while (n < size);
      
      return(TLB_MISS);


      
      //-----------------------------------------------------------------------
      // set associative TLB
      // compute start index as page-number modulo TLB size
      // round down to associativity
      // look for match within set
      // upon hit: set hit entry to associativity-1 (youngest entry)
      //           decrement every age above the hit entries original age
      //           leave rest unchanged
      
    case TLB_SET_ASSOC:
      n    = PAGE_SIZE;
      base = addr;
      while (n != 1)
	{
	  n = n >> 1;
	  base = base >> 1;
	}
      base = base % (size / associativity);
      base *= associativity;

      n = 0;
      do
	{
	  tag  = entries[base + n].tag;
	  data = entries[base + n].data;
	  ctx  = entries[base + n].context;

	  if ((tlb_tag(tag) == tlb_tag(addr)) &&
	      tlb_valid(tag) &&
	      ((tagged && ctx == context) || (!tagged)))
	    {
	      *attributes = tlb_attr(data);

	      if (write && tlb_rdonly(data))
		return(TLB_FAULT);
	      
	      if (!priv && tlb_priv(data))
		return(TLB_FAULT);
	      
	      if (tlb_mvalid(data))
		*address = tlb_data(data) | tlb_offset(addr);
	      else
		return(TLB_FAULT);
	      
	      old_age = entries[base+n].age;
	      entries[base+n].age = associativity-1;
	      for (i = 0; i < associativity; i++)
		{
		  if (i == n)
		    continue;
		  if (entries[base+i].age > old_age)
		    entries[base+i].age--;
		}
	      
	      return(TLB_HIT);
	    }
	  n++;
	}
      while (n < associativity);

      return(TLB_MISS);


      
      //-----------------------------------------------------------------------
      // direct mapped TLB
      // compute index as page-number modulo TLB-size
  
    case TLB_DIRECT_MAPPED:
      n    = PAGE_SIZE;
      base = addr;
      while (n != 1)
	{
	  n = n >> 1;
	  base = base >> 1;
	}
      base = base % size;

      if ((tlb_tag(entries[base].tag) == tlb_tag(addr)) &&
	  (tlb_valid(entries[base].tag)) &&
	  ((tagged && entries[base].context == context) || (!tagged)))
	{
	  *attributes = tlb_attr(entries[base].data);

	  if (write && tlb_rdonly(entries[base].data))
	    return(TLB_FAULT);
	      
	  if (!priv && tlb_priv(entries[base].data))
	    return(TLB_FAULT);

	  if (tlb_mvalid(entries[base].data))
	    *address = tlb_data(entries[base].data) | tlb_offset(addr);
	  else
	    return(TLB_FAULT);
	  
	  return(TLB_HIT);
	}

      return(TLB_MISS);


    default:
      return(TLB_FAULT);
    }
}




//=============================================================================
// Callback routine for hardware table walk, called by cache when request
// completes.
// If L0 access done: check entry and start L1 access
// If L1 access done: write TLB entry and resume processor
//=============================================================================

extern "C" void Perform_TLB_Fill(REQ *req)
{
  TLB *tlb = (TLB*)req->d.mem.aux;
  tlb->Perform_Fill(req);
}


void TLB::Perform_Fill(REQ *req)
{
  if (fill_data == 0)
    {
      fill_data = tlb_read_word(proc, fill_tag, req->paddr);

      if (!tlb_mvalid(fill_data))
	{
	  WriteEntry(fill_index, tlb_tag(fill_addr) | 1, fill_context, 0);
	  proc->DELAY = 0;
	}

      DCache_recv_tlbfill(proc->proc_id, Perform_TLB_Fill,
			  (unsigned char*)&fill_data,
			  (fill_data & ~3) | ((fill_addr >> 10) & 0xFFC),
			  this);
      
      return;
    }

  WriteEntry(fill_index,
	     tlb_tag(fill_addr) | 1,
	     fill_context,
	     fill_data);
  proc->DELAY = 0;
}



//=============================================================================
// Initiate TLB hardware fill
// Kick off L0 request to cache, using Perform_TLB_Fill as completion callback
//=============================================================================

void TLB::Fill(unsigned int addr, int idx, unsigned int ctx, long long tag)
{
  fill_addr    = addr;
  fill_index   = idx;
  fill_data    = 0;
  fill_context = ctx;
  fill_tag     = tag;

  DCache_recv_tlbfill(proc->proc_id, Perform_TLB_Fill,
		      (unsigned char*)&fill_data,
		      proc->log_int_reg_file[arch_to_log(proc,
							 proc->cwp,
							 PRIV_TLB_CONTEXT)] +
		      ((addr >> 20) & ~3), this);
}




//=============================================================================
// Access physical memory to read a word (page table entry)
// Check processor memory or store queue for older, pending stores
// Forward data if match, otherwise read physical memory
//=============================================================================

unsigned int tlb_read_word(ProcState *proc, long long tag, unsigned int addr)
{
  instance *conf;
  unsigned int data;
  int found;
  MemQLink<instance *> *ldindex = NULL;      

  found = 0;
  
#ifndef STORE_ORDERING
  //  proc->StoreQueue.GetMin(conf);
  while ((ldindex = proc->StoreQueue.GetNext(ldindex)) != NULL)
#else
    //  proc->MemQueue.GetMin(conf);
  while ((ldindex = proc->MemQueue.GetNext(ldindex)) != NULL)
#endif
    {
      conf = ldindex->d;

      if ((!IsStore(conf)) || (!conf->addr_ready) || (conf->busybits))
	continue;

      if (conf->tag >= tag)
	break;

      if ((conf->code.instruction == iSTW) && (addr == conf->addr))
	{
	  data = conf->rs1vali;
	  found = 1;
	}

      if (conf->code.instruction == iSTD)
	{
	  if (addr == conf->addr)
	    {
	      data = conf->rs1valipair.a;
	      found = 1;
	    }
	  else if (addr + sizeof(int) == conf->addr)
	    {
	      data = conf->rs1valipair.b;
	      found = 1;
	    }
	}
    }

  if (found)
    return(data);
  else
    return(read_int(proc->proc_id / ARCH_cpus, addr));
}