procstate.cc

ml-rsim 多处理器模拟器 支持类bsd操作系统

  int i;
#ifndef NOSTAT
  StatrecReport(nid, FetchQueueStats);
  StatrecReport(nid, ActiveListStats);

  StatrecReport(nid, SpecStats);
#ifndef STORE_ORDERING
  StatrecReport(nid, VSB);
  StatrecReport(nid, LoadQueueSize);
#else
  StatrecReport(nid, MemQueueSize);
#endif
#endif
  
  YS__statmsg(nid,
	      "\n------------------------------------------------------------------------\n");
  YS__statmsg(nid, "Branch Prediction Statistics\n\n");

  if (BPB_TYPE == TWOBIT)
    YS__statmsg(nid, "Two bit predictor; %i entries\n\n", BPB_SIZE);
  if (BPB_TYPE == TWOBITAGREE)
    YS__statmsg(nid, "Two bit agree predictor; %i entries\n\n", BPB_SIZE);
  if (BPB_TYPE == STATIC)
    YS__statmsg(nid, "Static predictor\n");

  YS__statmsg(nid, "%lld good predictions;  %lld bad predictions\n",
	 bpb_good_predicts, bpb_bad_predicts);
  YS__statmsg(nid, "Prediction accuracy: %.4f%%\n\n",
	 100.0 * double(bpb_good_predicts) / (bpb_good_predicts + bpb_bad_predicts));

  
  YS__statmsg(nid,
	      "\n------------------------------------------------------------------------\n");
  YS__statmsg(nid, "Return Address Stack Statistics\n\n");

  if (RAS_STKSZ > 0)
    {
      YS__statmsg(nid, "RAS size: %i\n", RAS_STKSZ);
      YS__statmsg(nid, "%lld good predictions;  %lld bad predictions\n",
		  ras_good_predicts, ras_bad_predicts);
      YS__statmsg(nid, "Prediction accuracy: %.4f%%\n",
		  100.0 * double(ras_good_predicts) / (ras_good_predicts + ras_bad_predicts));
      YS__statmsg(nid, "%lld RAS Underflows;  %lld RAS Overflows\n",
		  ras_underflows, ras_overflows);
    }
  else
    YS__statmsg(nid, "No RAS\n");
  
  
  YS__statmsg(nid,
	      "\n------------------------------------------------------------------------\n");

  YS__statmsg(nid,
	      "Loads issued: %lld, speced: %lld, limbos: %lld, unlimbos: %lld, "
	      "redos: %lld, kills: %lld\n", ldissues, ldspecs, limbos,
	      unlimbos, redos, kills);
  YS__statmsg(nid,
	      "Memory unit fwds: %lld, Virtual store buffer fwds: %lld "
	      "Partial overlaps: %lld\n", fwds, vsbfwds, partial_overlaps);

#ifndef NOSTAT
  StatrecReport(nid, BadPredFlushes);

  StatrecReport(nid, ExceptFlushed);

  for (i = 0; i < numUTYPES; i++)
    if (i != uMEM)     /* cache port utilization not really meaningul like
			  others..  */
      YS__statmsg(nid, "%s\t%12.1f%%\n", fuusage_names[i],
		  StatrecMean(FUUsage[i]) / double (MaxUnits[i]) * 100.0);


#ifdef DETAILED_STATS_LAT_CONTR
  for (i = 0; i < numUTYPES; i++)
    StatrecReport(nid, FUUsage[i]);

  for (i = 0; i < lNUM_LAT_TYPES; i++)
    StatrecReport(nid, lat_contrs[i]);

  StatrecReport(nid, partial_otime);
  StatrecReport(nid, readacc);
  StatrecReport(nid, writeacc);
  StatrecReport(nid, rmwacc);
  StatrecReport(nid, readiss);
  StatrecReport(nid, writeiss);
  StatrecReport(nid, rmwiss);
  StatrecReport(nid, readact);
  StatrecReport(nid, writeact);
  StatrecReport(nid, rmwact);
#endif

  StatrecReport(nid, in_except);

  long long drd  = StatrecSamples(readacc);
  long long dwt  = StatrecSamples(writeacc);
  long long drmw = StatrecSamples(rmwacc);

#if 0
  double dmds = drd + dwt + drmw;

  for (i = 0; i < (int) reqNUM_REQ_STAT_TYPE; i++)
    {
      long long d = StatrecSamples(demand_read[i]);
      YS__statmsg(nid,
		  "Demand read %s -- Num %lld (%.3f,%.3f) Mean %.3f/%.3f/%.3f"
		  " Stddev %.3f/%.3f/%.3f\n",
		  Req_stat_type[i],
		  d,
		  (double)d/(double)drd,
		  (double)d / (double)dmds,
		  StatrecMean(demand_read_act[i]),
		  StatrecMean(demand_read[i]),
		  StatrecMean(demand_read_iss[i]),
		  StatrecSdv(demand_read_act[i]),
		  StatrecSdv(demand_read[i]),
		  StatrecSdv(demand_read_iss[i]));
    }
  
  for (i = 0; i < (int) reqNUM_REQ_STAT_TYPE; i++)
    {
      long long d = StatrecSamples(demand_write[i]);
      YS__statmsg(nid,
		  "Demand write %s -- Num %lld (%.3f,%.3f) Mean %.3f/%.3f/%.3f"
		  " Stddev %.3f/%.3f/%.3f\n",
		  Req_stat_type[i],
		  d,
		  (double)d / (double)dwt,
		  (double)d / (double)dmds,
		  StatrecMean(demand_write_act[i]),
		  StatrecMean(demand_write[i]),
		  StatrecMean(demand_write_iss[i]),
		  StatrecSdv(demand_write_act[i]),
		  StatrecSdv(demand_write[i]),
		  StatrecSdv(demand_write_iss[i]));
    }
  
  for (i = 0; i < (int) reqNUM_REQ_STAT_TYPE; i++)
    {
      long long d = StatrecSamples(demand_rmw[i]);
      YS__statmsg(nid,
		  "Demand rmw %s -- Num %lld (%.3f,%.3f) Mean %.3f/%.3f/%.3f"
		  "Stddev %.3f/%.3f/%.3f\n",
		  Req_stat_type[i],
		  d,
		  (double)d / (double)drmw,
		  (double)d / (double)dmds,
		  StatrecMean(demand_rmw_act[i]),
		  StatrecMean(demand_rmw[i]),
		  StatrecMean(demand_rmw_iss[i]),
		  StatrecSdv(demand_rmw_act[i]),
		  StatrecSdv(demand_rmw[i]),
		  StatrecSdv(demand_rmw_iss[i]));
    }
  
  for (i = 0; i < (int) reqNUM_REQ_STAT_TYPE; i++)
    {
      long long d = StatrecSamples(pref_sh[i]);
      YS__statmsg(nid,
		  "Pref sh %s -- Num %lld Mean %.3f Stddev %.3f\n",
		  Req_stat_type[i],
		  d,
		  StatrecMean(pref_sh[i]),
		  StatrecSdv(pref_sh[i]));
    }
  
  for (i = 0; i < (int) reqNUM_REQ_STAT_TYPE; i++)
    {
      long long d = StatrecSamples(pref_excl[i]);
      YS__statmsg(nid,
		  "Pref excl %s -- Num %lld Mean %.3f Stddev %.3f\n",
		  Req_stat_type[i],
		  d,
		  StatrecMean(pref_excl[i]),
		  StatrecSdv(pref_excl[i]));
    }
#endif
#endif
  
  YS__statmsg(nid, "\n");

  for (i = 0; i < lNUM_LAT_TYPES; i++)
    YS__statmsg(nid,
		"Avail loss from %s   %12.3f\n", lattype_names[i],
		avail_active_full_losses[i] /
		(double (decode_rate) * (curr_cycle - start_time)));

  YS__statmsg(nid, "\n");

  for (i = 0; i < eNUM_EFF_STALLS; i++)   // don't count 0 since this is OK 
    YS__statmsg(nid,
		"Efficiency loss from %s   %12.3f\n", eff_loss_names[i],
		double (eff_losses[i]) / double (avail_fetch_slots));

  double ifetch = instruction_count - start_icount;

  YS__statmsg(nid, "\n");

#ifndef NOSTAT
  YS__statmsg(nid,
	      "Utility losses from misspecs  %.3f excepts: %.3f\n",
	      StatrecSum(BadPredFlushes) / ifetch,
	      StatrecSum(ExceptFlushed) / ifetch);
#endif
  
  YS__statmsg(nid,
	      "\n\n");
}




void ProcState::report_phase_fast(int pid)
{
  int nid = pid / ARCH_cpus;
  
  YS__statmsg(nid,
	      "STAT Processor: %d EndPhase: %d Issued: %lld Graduated: %lld\n",
	      proc_id,
	      stats_phase,
	      instruction_count - start_icount,
	      graduates);
  
  YS__statmsg(nid,
	      "STAT Execution time: %lld Start time: %lld Since last grad: %lld\n",
	      curr_cycle - start_time,
	      start_time,
	      curr_cycle - last_graduated);

#ifndef NOSTAT
  for (int i = 0; i < lNUM_LAT_TYPES; i++)
    YS__statmsg(nid,
		"STAT %s: Grads %lld Ratio %.4f\n",
		lattype_names[i],
		StatrecSamples(lat_contrs[i]),
		double(StatrecSamples(lat_contrs[i])) * StatrecMean(lat_contrs[i]) /
    double(curr_cycle - start_time));
#endif
	
  YS__statmsg(nid,
	      "STAT Branch prediction rate: %.4f\n",
	      double(bpb_good_predicts) / double(bpb_good_predicts + bpb_bad_predicts));
  
  YS__statmsg(nid,
	      "STAT Return prediction rate: %.4f\n",
	      double(ras_good_predicts) / double(ras_good_predicts + ras_bad_predicts));

#ifndef NOSTAT
  YS__statmsg(nid,
	      "STAT Reads Mean (ACT): %.3f Stddev: %.3f\n",
	      StatrecMean(readact),
	      StatrecSdv(readact));
  
  YS__statmsg(nid,
	      "STAT Writes Mean (ACT): %.3f Stddev: %.3f\n",
	      StatrecMean(writeact),
	      StatrecSdv(writeact));
  
  YS__statmsg(nid,
	      "STAT RMW Mean (ACT): %.3f Stddev: %.3f\n",
	      StatrecMean(rmwact),
	      StatrecSdv(rmwact));
  
  YS__statmsg(nid,
	      "STAT Reads Mean (EA): %.3f Stddev: %.3f\n",
	      StatrecMean(readacc),
	      StatrecSdv(readacc));
  
  YS__statmsg(nid,
	      "STAT Writes Mean (EA): %.3f Stddev: %.3f\n",
	      StatrecMean(writeacc),
	      StatrecSdv(writeacc));
  
  YS__statmsg(nid,
	      "STAT RMW Mean (EA): %.3f Stddev: %.3f\n",
	      StatrecMean(rmwacc),
	      StatrecSdv(rmwacc));
  
  YS__statmsg(nid,
	      "STAT Reads Mean (ISS): %.3f Stddev: %.3f\n",
	      StatrecMean(readiss),
	      StatrecSdv(readiss));
  
  YS__statmsg(nid,
	      "STAT Writes Mean (ISS): %.3f Stddev: %.3f\n",
	      StatrecMean(writeiss),
	      StatrecSdv(writeiss));
  
  YS__statmsg(nid,
	      "STAT RMW Mean (ISS): %.3f Stddev: %.3f\n",
	      StatrecMean(rmwiss),
	      StatrecSdv(rmwiss));
  
  YS__statmsg(nid,
	      "STAT ExceptionWait Mean: %.3f Stddev: %.3f\n",
	      StatrecMean(in_except),
	      StatrecSdv(in_except));
#endif
  
  double avail = double(avail_fetch_slots) /
    (double(decode_rate) * double(curr_cycle - start_time));
  
  double eff  = double(instruction_count - start_icount) / double(avail_fetch_slots);
  double util = double(graduates) / double(instruction_count - start_icount);
  
  YS__statmsg(nid,
	      "STAT Availability: %.3f Efficiency: %.3f Utility: %.3f\n",
	      avail,
	      eff,
	      util);
  
  YS__statmsg(nid, "\n");
}



/*************************************************************************/
/* state::end_phase : Full statistics dump at the end of a phase         */
/*************************************************************************/

void ProcState::endphase(int nid)
{
  report_stats(nid);
  reset_stats();
}


/*************************************************************************/
/* state::newphase: Reset phase collection statistics at new phase       */
/*************************************************************************/

void ProcState::newphase(int phase)
{
  reset_stats();       // to kill the statistics collected in the interphases
  stats_phase = phase;
}



/*************************************************************************/
/* state::reset_stats : Reset phase collection statistics                */
/*************************************************************************/

void ProcState::reset_stats()
{
  int i;

  start_time = curr_cycle;
  start_icount = instruction_count;
  graduates = 0;
  bpb_good_predicts = bpb_bad_predicts = 0;
  ras_good_predicts = ras_bad_predicts = 0;
  ras_underflows = ras_overflows = 0;

#ifndef NOSTAT
  StatrecReset(BadPredFlushes);
#endif
  
  for (int n = 0; n < MAX_EXCEPT; n++)
    {
      exceptions[n] = 0;
      graduated[n] = 0;
      cycles[n] = 0;
      start_cycle[n] = curr_cycle;
      start_graduated[n] = 0;
    }

  total_halted = 0;
  mem_refs = 0;

  ldissues = ldspecs = limbos = unlimbos = redos = 0;
  kills = vsbfwds = fwds = partial_overlaps = 0;
  avail_fetch_slots = 0;
  stats_phase = -1;

#ifndef NOSTAT
  StatrecReset(ExceptFlushed);
  StatrecReset(SpecStats);

  for (i = 0; i < numUTYPES; i++)
    StatrecReset(FUUsage[i]);

#ifndef STORE_ORDERING
  StatrecReset(VSB);
  StatrecReset(LoadQueueSize);
#else
  StatrecReset(MemQueueSize);
#endif

  StatrecReset(ActiveListStats);
  StatrecReset(FetchQueueStats);

  // size of active list
  StatrecReset(readacc);
  StatrecReset(writeacc);
  StatrecReset(rmwacc);
  StatrecReset(readact);
  StatrecReset(writeact);
  StatrecReset(rmwact);
  StatrecReset(readiss);
  StatrecReset(writeiss);
  StatrecReset(rmwiss);
  StatrecReset(in_except);

#if 0
  for (i = 0; i < reqNUM_REQ_STAT_TYPE; i++)
    {
      StatrecReset(demand_read[i]);
      StatrecReset(demand_write[i]);
      StatrecReset(demand_rmw[i]);

      StatrecReset(demand_read_act[i]);
      StatrecReset(demand_write_act[i]);
      StatrecReset(demand_rmw_act[i]);

      StatrecReset(demand_read_iss[i]);
      StatrecReset(demand_write_iss[i]);
      StatrecReset(demand_rmw_iss[i]);

      StatrecReset(pref_sh[i]);
      StatrecReset(pref_excl[i]);
   }
#endif

  for (int lat_ctr = 0; lat_ctr < int (lNUM_LAT_TYPES); lat_ctr++)
    StatrecReset(lat_contrs[lat_ctr]);

  StatrecReset(partial_otime);
#endif

  avail_fetch_slots = 0;
  
  for (i = 0; i < int (lNUM_LAT_TYPES); i++)
    avail_active_full_losses[i] = 0;

  for (i = 0; i < int (eNUM_EFF_STALLS); i++)
    eff_losses[i] = 0;
}