procstate.cc

ml-rsim 多处理器模拟器 支持类bsd操作系统

  
  stats_phase = 0;     // start out in a convenient phase #0

  limbos = 0;
  unlimbos = 0;
  redos = 0;
  kills = 0;
  vsbfwds = 0;
  fwds = 0;
  partial_overlaps = 0;
  avail_fetch_slots = 0;

#ifndef NOSTAT
  // total number of instructions flushed on bad predicts
  BadPredFlushes = NewStatrec(proc_id / ARCH_cpus,
			      "Bad prediction flushes",
			      POINT, MEANS, NOHIST, 8, 0, MAX_ACTIVE_INSTS);
  
  // total number of instructions flushed on exceptions
  ExceptFlushed = NewStatrec(proc_id / ARCH_cpus,
			     "Exception flushes",
			     POINT, MEANS, NOHIST, 8, 0, MAX_ACTIVE_INSTS);

  SpecStats = NewStatrec(proc_id / ARCH_cpus,
			 "Speculation level", POINT, MEANS, NOHIST,
			 MAX_SPEC, 0, MAX_SPEC);

  FUUsage[int (uALU)] = NewStatrec(proc_id / ARCH_cpus,
				   fuusage_names[uALU],
				   POINT, MEANS, HIST, ALU_UNITS,
				   0, ALU_UNITS);
  FUUsage[int (uFP)] = NewStatrec(proc_id / ARCH_cpus,
				  fuusage_names[uFP],
				  POINT, MEANS, HIST, FPU_UNITS, 0, FPU_UNITS);
  FUUsage[int (uMEM)] = NewStatrec(proc_id / ARCH_cpus,
				   fuusage_names[uMEM],
				   POINT, MEANS, HIST, MEM_UNITS,
				   0, MEM_UNITS);
  FUUsage[int (uADDR)] = NewStatrec(proc_id / ARCH_cpus,
				    fuusage_names[uADDR],
				    POINT, MEANS, HIST, ADDR_UNITS,
				    0, ADDR_UNITS);

  
#ifndef STORE_ORDERING
  VSB = NewStatrec(proc_id / ARCH_cpus,
		   "Virtual Store Buffer size",
		   POINT, MEANS, NOHIST, 10, 0, 100);
  LoadQueueSize = NewStatrec(proc_id / ARCH_cpus,
			     "Load queue size",
			     POINT, MEANS, HIST, 8, 0, MAX_MEM_OPS);
#else
  MemQueueSize = NewStatrec(proc_id / ARCH_cpus,
			    "Mem queue size",
			    POINT, MEANS, HIST, MAX_MEM_OPS / 8,
			    0, MAX_MEM_OPS);
#endif

  // size of fetch queue
  FetchQueueStats = NewStatrec(proc_id / ARCH_cpus,
			       "Fetch queue size",
			       POINT, MEANS, HIST, min(8, fetch_queue_size), 0,
			       fetch_queue_size);

  // size of active list
  ActiveListStats = NewStatrec(proc_id / ARCH_cpus,
			       "Active list size", POINT, MEANS,
			       HIST, 8, 0, MAX_ACTIVE_INSTS);

  readacc   = NewStatrec(proc_id / ARCH_cpus,
			 "Read accesses",
			 POINT, MEANS, NOHIST, 5, 0, 10);
  writeacc  = NewStatrec(proc_id / ARCH_cpus,
			 "Write accesses",
			 POINT, MEANS, NOHIST, 5, 0,10);
  rmwacc    = NewStatrec(proc_id / ARCH_cpus,
			 "RMW accesses",
			 POINT, MEANS, NOHIST, 5, 0, 10);

  readiss   = NewStatrec(proc_id / ARCH_cpus,
			 "Read accesses (from issue)",
			 POINT, MEANS, NOHIST, 5, 0, 10);
  writeiss  = NewStatrec(proc_id / ARCH_cpus,
			 "Write accesses (from issue)",
			 POINT, MEANS, NOHIST, 5, 0, 10);
  rmwiss    = NewStatrec(proc_id / ARCH_cpus,
			 "RMW accesses (from issue)",
			 POINT, MEANS, NOHIST, 5, 0, 10);

  readact   = NewStatrec(proc_id / ARCH_cpus,
			 "Read active",
			 POINT, MEANS, NOHIST, 5, 0, 10);
  writeact  = NewStatrec(proc_id / ARCH_cpus,
			 "Write active",
			 POINT, MEANS, NOHIST, 5, 0, 10);
  rmwact    = NewStatrec(proc_id / ARCH_cpus,
			 "RMW active",
			 POINT, MEANS, NOHIST, 5, 0, 10);

  
#if 0
  for (i = 0; i < reqNUM_REQ_STAT_TYPE; i++)
    {
      demand_read[i]      = NewStatrec(proc_id / ARCH_cpus,
				       "Demand read",
				       POINT, MEANS, NOHIST, 0, 0, 0);
      demand_write[i]     = NewStatrec(proc_id / ARCH_cpus,
				       "Demand write",
				       POINT, MEANS, NOHIST, 0, 0, 0);
      demand_rmw[i]       = NewStatrec(proc_id / ARCH_cpus,
				       "Demand rmw",
				       POINT, MEANS, NOHIST, 0, 0, 0);

      demand_read_iss[i]  = NewStatrec(proc_id / ARCH_cpus,
				       "Demand read (issued)",
				       POINT, MEANS, NOHIST, 0, 0, 0);
      demand_write_iss[i] = NewStatrec(proc_id / ARCH_cpus,
				       "Demand write (issued)",
				       POINT, MEANS, NOHIST, 0, 0, 0);
      demand_rmw_iss[i]   = NewStatrec(proc_id / ARCH_cpus,
				       "Demand rmw (issued)",
				       POINT, MEANS, NOHIST, 0, 0, 0);

      demand_read_act[i]  = NewStatrec(proc_id / ARCH_cpus,
				       "Demand read (active)",
				       POINT, MEANS, NOHIST, 0, 0, 0);
      demand_write_act[i] = NewStatrec(proc_id / ARCH_cpus,
				       "Demand write (active)",
				       POINT, MEANS, NOHIST, 0, 0, 0);
      demand_rmw_act[i]   = NewStatrec(proc_id / ARCH_cpus,
				       "Demand rmw (active)",
				       POINT, MEANS, NOHIST, 0, 0, 0);

      pref_sh[i]          = NewStatrec(proc_id / ARCH_cpus,
				       "pref clean",
				       POINT, MEANS, NOHIST, 0, 0, 0);
      pref_excl[i]        = NewStatrec(proc_id / ARCH_cpus,
				       "pref excl",
				       POINT, MEANS, NOHIST, 0, 0, 0);
    }
#endif

  in_except = NewStatrec(proc_id / ARCH_cpus,
			 "Waiting for exceptions",
			 POINT, MEANS, NOHIST, 5, 0, 50);


  for (int lat_ctr = 0; lat_ctr < int (lNUM_LAT_TYPES); lat_ctr++)
    lat_contrs[lat_ctr] = NewStatrec(proc_id / ARCH_cpus,
				     lattype_names[lat_ctr],
				     POINT, MEANS, NOHIST, 0, 0, 0);

  partial_otime = NewStatrec(proc_id / ARCH_cpus,
			     "Partial Overlap time",
			     POINT, MEANS, NOHIST, 0, 0, 0);
#endif

  
  avail_fetch_slots = 0;
  for (i = 0; i < int (lNUM_LAT_TYPES); i++)
    avail_active_full_losses[i] = 0;

  for (i = 0; i < int (eNUM_EFF_STALLS); i++)
    eff_losses[i] = 0;

  UnitSetup(this, 0);
}




/*************************************************************************/
/* reset_lists  : Initialize the register files and the mappers          */
/*************************************************************************/
 

int ProcState::reset_lists()
{
  int i;
  /* Set busy register lists and free register lists */

  instances.reset();
 
  copymappernext = 0;
  unpredbranch   = 0;
  unstall_the_rest(this);
  
  intregbusy[intmapper[ZEROREG]] = 0;

  memset((char *)fpregbusy, 0, NO_OF_PHY_FP_REGS * sizeof(char));
  memset((char *)intregbusy, 0, NO_OF_PHY_INT_REGS * sizeof(char));
  
  // Free all the inuse registers
  free_int_list->reset();
  free_fp_list->reset();
  
  /* Initialize the mappers */
  for (i = 0; i < NO_OF_LOG_FP_REGS; i++)
    fpmapper[i] = free_fp_list->getfreereg();
  //    fpmapper[i] = i;

  intmapper[ZEROREG] = ZEROREG;
  for (i = 1; i < NO_OF_LOG_INT_REGS; i++)
    intmapper[i] = free_int_list->getfreereg();
  //    intmapper[i] = i;

  // Reallocate and initialize physical registers to logical values
  for (i = 0; i < NO_OF_LOG_FP_REGS; i++)
    phy_fp_reg_file[fpmapper[i]] = log_fp_reg_file[i];
  for (i = 0; i < NO_OF_LOG_INT_REGS; i++)
    phy_int_reg_file[intmapper[i]] = log_int_reg_file[i];
  //  memcpy(phy_fp_reg_file,
  //         log_fp_reg_file,
  //         NO_OF_LOG_FP_REGS * sizeof(double));
  //  memcpy(phy_int_reg_file,
  //         log_int_reg_file,
  //         NO_OF_LOG_INT_REGS * sizeof(int));
  
  /* Note :The CURRENT WINDOW POINTER REMAINS UNCHANGED */
  
  return 0;
}



extern "C"
{
int Proc_stat_report(int nid, int pid);
void Proc_stat_clear(int nid, int pid);

int Proc_stat_report(int nid, int pid)
{
  if (AllProcs[nid * ARCH_cpus + pid] == NULL)
    return 0;

  AllProcs[nid * ARCH_cpus + pid]->report_stats(nid);
  
  return 1;
}



void Proc_stat_clear(int nid, int pid)
{
  if (AllProcs[nid * ARCH_cpus + pid] != NULL)
    AllProcs[nid * ARCH_cpus + pid]->reset_stats();
}
}



/***************************************************************************/
/***************************************************************************/

void ProcState::report_stats(int nid)
{
  YS__statmsg(nid,
	      "Processor Clock:   %12.1f MHz (%.3f ns period)\n\n",
	      1000000.0 / (double)CPU_CLK_PERIOD,
	      (double)CPU_CLK_PERIOD / 1000.0);
  
  YS__statmsg(nid,
	      "Start cycle:            %12lld    Start instruction count: %12lld\n",
	      start_time,
	      start_icount);
  YS__statmsg(nid,
	      "End cycle:              %12lld    End instruction count:   %12lld\n",
	      curr_cycle,
	      instruction_count);
  YS__statmsg(nid,
	      "Total cycles:           %12lld    Real time:               ",
	      curr_cycle - start_time);
  PrintTime((curr_cycle - start_time) * (double)CPU_CLK_PERIOD / 1.0e12,
	    statfile[nid]);
  YS__statmsg(nid, "\n");
  YS__statmsg(nid,
	      "Non-halted cycles:      %12lld    CPU Utilization:        %8.2lf %%\n",
	      curr_cycle - start_time - total_halted,
	      100.0 * (double)(curr_cycle - start_time - total_halted) /
	      (double)(curr_cycle - start_time));
  YS__statmsg(nid,
	      "Instructions decoded:   %12lld    Decode IPC:             %8.2f\n",
	      instruction_count - start_icount,
	      (float)(instruction_count - start_icount) /
	      (float)(curr_cycle - start_time - total_halted));
  YS__statmsg(nid,
	      "Instructions graduated: %12lld    Graduate IPC:           %8.2f\n",
	      graduates,
	      (float)(graduates) / (float)(curr_cycle - start_time - total_halted));


  
  YS__statmsg(nid,
	      "\n------------------------------------------------------------------------\n");
  YS__statmsg(nid,
	      "INSTRUCTION BREAKDOWN\n\n");
  YS__statmsg(nid,
	      "Class                     Count         Cycles   Instructions       IPC\n");
  
  for (int n = 0; n < MAX_EXCEPT; n++)
    {
      if ((exceptions[n] > 0) || (n == 0))
        {
	  if (n == 0)
	    YS__statmsg(nid,
			"%s            --",
			enames[n]);
	  else
	    YS__statmsg(nid,
			"%s  %12lld",
			enames[n],
			exceptions[n]);

          if (cycles[n] > 0)
            YS__statmsg(nid,
			"   %12lld   %12lld   %8.3f\n",
			cycles[n],
			graduated[n],
			(float)((float)graduated[n]/(float)cycles[n]));
          else
            YS__statmsg(nid,
			"\n");
 
        }
    }



  YS__statmsg(nid,
	      "\n------------------------------------------------------------------------\n"); 
  YS__statmsg(nid, "TLB STATISTICS\n\n");

  if (!TLB_UNIFIED)
    {
      YS__statmsg(nid, "Instruction TLB: ");
      if (ITLB_TYPE == TLB_FULLY_ASSOC)
	YS__statmsg(nid,
		    "Fully Associative; %i entries",
		    ITLB_SIZE);
 
      if (ITLB_TYPE == TLB_SET_ASSOC)
	YS__statmsg(nid,
		    "%i Way Set Associative; %i entries",
		    ITLB_ASSOCIATIVITY, ITLB_SIZE);
 
      if (ITLB_TYPE == TLB_DIRECT_MAPPED)
	YS__statmsg(nid,
		    "Direct Mapped; %i entries",
		    ITLB_SIZE);
      
      if (ITLB_TYPE == TLB_PERFECT)
	YS__statmsg(nid,
		    "Perfect (100%% hit rate)\n\n");
      else
	{
	  if (ITLB_TAGGED)
	    YS__statmsg(nid, "; tagged");
	YS__statmsg(nid,
		    "\n\n%lld Total ITLB accesses; %lld ITLB Misses; %.4f%% ITLB Hit Rate\n\n",
		    graduates,
		    exceptions[ITLB_MISS],
		    100.0 - 100.0 * (double)exceptions[ITLB_MISS]/(double)graduates);
	}

      
      YS__statmsg(nid, "Data TLB: ");
      
      if (DTLB_TYPE == TLB_FULLY_ASSOC)
	YS__statmsg(nid,
		    "Fully Associative; %i entries",
		    DTLB_SIZE);
 
      if (DTLB_TYPE == TLB_SET_ASSOC)
	YS__statmsg(nid,
		    "%i Way Set Associative; %i entries",
		    DTLB_ASSOCIATIVITY, DTLB_SIZE);
 
      if (DTLB_TYPE == TLB_DIRECT_MAPPED)
	YS__statmsg(nid,
		    "Direct Mapped; %i entries",
		    DTLB_SIZE);
 
      if (DTLB_TYPE == TLB_PERFECT)
	YS__statmsg(nid,
		    "Perfect (100%% hit rate)\n\n");
      else
	{
	  if (DTLB_TAGGED)
	    YS__statmsg(nid, "; tagged");
	  YS__statmsg(nid,
		      "\n\n%lld Total DTLB accesses; %lld DTLB Misses; %.4f%% DTLB Hit Rate\n\n",
		      mem_refs,
		      exceptions[DTLB_MISS],
		      100.0 - 100.0 * (double)exceptions[DTLB_MISS]/(double)mem_refs);
	}
    }
  
  else       // unified TLB
    {
      YS__statmsg(nid, "Unified TLB: ");
      if (DTLB_TYPE == TLB_FULLY_ASSOC)
	YS__statmsg(nid,
		    "Fully Associative; %i entries",
		    DTLB_SIZE);
 
      if (DTLB_TYPE == TLB_SET_ASSOC)
	YS__statmsg(nid,
		    "%i Way Set Associative; %i entries",
		    DTLB_ASSOCIATIVITY, DTLB_SIZE);
 
      if (DTLB_TYPE == TLB_DIRECT_MAPPED)
	YS__statmsg(nid,
		    "Direct Mapped; %i entries",
		    DTLB_SIZE);
      
      if (DTLB_TYPE == TLB_PERFECT)
	YS__statmsg(nid,
		    "Perfect (100%% hit rate)\n\n");
      else
	{
	  if (DTLB_TAGGED)
	    YS__statmsg(nid, "; tagged");
	  YS__statmsg(nid,
		      "\n\n%lld Total ITLB accesses; %lld ITLB Misses; Miss Rate %.4f%%\n",
		      graduates,
		      exceptions[ITLB_MISS],
		      100.0 * (double)exceptions[ITLB_MISS]/(double)graduates);
      
	  YS__statmsg(nid,
		      "%lld Total DTLB accesses; %lld DTLB Misses; Miss Rate %.4f%%\n",
		      mem_refs,
		      exceptions[DTLB_MISS],
		      100.0 * (double)exceptions[DTLB_MISS]/(double)mem_refs);

	  YS__statmsg(nid,
		      "%.2lf%% Unified TLB Hit Rate\n\n",
		      100.0 - 100.0 * (double)exceptions[DTLB_MISS] /
		      (double)(graduates + mem_refs));
	}
    }




  //-------------------------------------------------------------------------