procstate.cc

ml-rsim 多处理器模拟器 支持类bsd操作系统

/*
 * Copyright (c) 2002 The Board of Trustees of the University of Illinois and
 *                    William Marsh Rice University
 * Copyright (c) 2002 The University of Utah
 * Copyright (c) 2002 The University of Notre Dame du Lac
 *
 * All rights reserved.
 *
 * Based on RSIM 1.0, developed by:
 *   Professor Sarita Adve's RSIM research group
 *   University of Illinois at Urbana-Champaign and
     William Marsh Rice University
 *   http://www.cs.uiuc.edu/rsim and http://www.ece.rice.edu/~rsim/dist.html
 * ML-RSIM/URSIM extensions by:
 *   The Impulse Research Group, University of Utah
 *   http://www.cs.utah.edu/impulse
 *   Lambert Schaelicke, University of Utah and University of Notre Dame du Lac
 *   http://www.cse.nd.edu/~lambert
 *   Mike Parker, University of Utah
 *   http://www.cs.utah.edu/~map
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal with the Software without restriction, including without
 * limitation the rights to use, copy, modify, merge, publish, distribute,
 * sublicense, and/or sell copies of the Software, and to permit persons to
 * whom the Software is furnished to do so, subject to the following
 * conditions:
 *
 * 1. Redistributions of source code must retain the above copyright notice,
 *    this list of conditions and the following disclaimers. 
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimers in the
 *    documentation and/or other materials provided with the distribution.
 * 3. Neither the names of Professor Sarita Adve's RSIM research group,
 *    the University of Illinois at Urbana-Champaign, William Marsh Rice
 *    University, nor the names of its contributors may be used to endorse
 *    or promote products derived from this Software without specific prior
 *    written permission. 
 * 4. Neither the names of the ML-RSIM project, the URSIM project, the
 *    Impulse research group, the University of Utah, the University of
 *    Notre Dame du Lac, nor the names of its contributors may be used to
 *    endorse or promote products derived from this software without specific
 *    prior written permission. 
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS WITH THE SOFTWARE. 
 */

#include <malloc.h>

extern "C"
{
#include "sim_main/simsys.h"
#include "Caches/system.h"
#include "Caches/cache.h"
}

#include "Processor/procstate.h"
#include "Processor/mainsim.h"
#include "Processor/branchpred.h"
#include "Processor/simio.h"
#include "Processor/fastnews.h"
#include "Processor/tagcvt.hh"
#include "Processor/active.hh"
#include "Processor/procstate.hh"
#include "Processor/memunit.h"
#include "Processor/exec.h"
#include "Processor/branchpred.hh"
#include "Processor/pagetable.h"



#define min(a, b)               ((a) > (b) ? (b) : (a))



int   ProcState::numprocs = 0;
int   aliveprocs = 0;


ProcState  **AllProcs;



/* set the names for factors leading to efficiency loss (see state.h) */

const char *eff_loss_names[eNUM_EFF_STALLS] =
{
  "OK                   ",
  "Branch in cycle      ",
  "Unpredicted branch   ",
  "Shadow mappers full  ",
  "Rename registers full",
  "Memory queue full    ",
  "Issue queue full     "
};


const char *fuusage_names[numUTYPES] =
{
  "ALU utilization       ",
  "FPU utilization       ",
  "Addr. gen. utilization",
  "Cache port utilization"
};


static void ResetInst(instance * inst)
{
  inst->tag   = -1;
  inst->inuse = 0;
}




/***********************************************************************/
/* ******************** state class constructor ********************** */
/***********************************************************************/

ProcState::ProcState(int proc):
  active_list  (MAX_ACTIVE_NUMBER),
  tag_cvt      (MAX_ACTIVE_INSTS + 3),
  FreeingUnits (ALU_UNITS + FPU_UNITS + ADDR_UNITS + MEM_UNITS),
  instances    (MAX_ACTIVE_INSTS + FETCH_QUEUE_SIZE + 1, ResetInst),
  meminstances (MAX_ACTIVE_INSTS),
  bqes         (MAX_SPEC + 2),
  mappers      (MAX_SPEC + 1),
  ministallqs  ((MAX_ACTIVE_INSTS + 1) * 7),
  actives      (MAX_ACTIVE_NUMBER + 3),
  tagcvts      (MAX_ACTIVE_INSTS + 3)
{
  int i, j, n;

  proc_id = proc;
  aliveprocs++;
  halt = 0;
  
#ifdef COREFILE
  char proc_file_name[80];
  sprintf(proc_file_name, "corefile.%d", proc_id);
  corefile = fopen(proc_file_name, "w");
#else
  corefile = NULL;
#endif

  l1i_argptr = L1ICaches[proc_id];
  l1d_argptr = L1DCaches[proc_id];
  l2_argptr  = L2Caches[proc_id];
  wb_argptr  = WBuffers[proc_id];

  fetch_rate      = FETCHES_PER_CYCLE;
  decode_rate     = DECODES_PER_CYCLE;
  graduate_rate   = GRADUATES_PER_CYCLE;
  max_active_list = MAX_ACTIVE_NUMBER;

  exit = 0;                  /* don't exit yet */
  interrupt_pending = 0;     /* no interrupt   */

  PageTable = PageTables[proc_id / ARCH_cpus];

  
  // Initialize privileged state --------------------------------------------

  pc = 0;

  pstate = 0;
  PSTATE_SET_PRIV(pstate);
  PSTATE_CLR_ITE(pstate);
  PSTATE_CLR_DTE(pstate);
  PSTATE_CLR_AG(pstate);
  PSTATE_CLR_IE(pstate);
  PSTATE_SET_FPE(pstate);

  tl = 0;
  pil = 0;
  
  itlb_wired  = dtlb_wired = 0;

  if (ToPowerOf2(NUM_WINS) != NUM_WINS)
    YS__errmsg(proc_id / ARCH_cpus,
	       "NumWins (%i) must be power of 2\n", NUM_WINS);
  
  cwp = 0;
  cansave = NUM_WINS - 2;
  canrestore = 0;
  otherwin   = 0;
  cleanwin   = NUM_WINS;
  tick_base  = 0ll;

  
  // Initialize FP state ----------------------------------------------------

  fp_trap_type    = 0;
  fp754_trap_mask = 0;
  fp754_aexc      = 0;
  fp754_cexc      = 0;
  
  
  //-------------------------------------------------------------------------
  
  instruction_count = 0;
  curr_cycle        = 0;
  graduation_count  = 0;
  last_graduated    = 0;

  /* initialize the free lists and busy lists */
  //  short *origfpfree = new short[NO_OF_PHY_FP_REGS];
  //  for (i = 0, j = NO_OF_LOG_FP_REGS; j < NO_OF_PHY_FP_REGS; i++, j++)
  //    origfpfree[i] = j;

  free_fp_list = new freelist(NO_OF_PHY_FP_REGS);//, origfpfree,
  //NO_OF_PHY_FP_REGS - NO_OF_LOG_FP_REGS);

  //  short *origintfree = new short[NO_OF_PHY_INT_REGS];
  //  for (i = 0, j = NO_OF_LOG_INT_REGS; j < NO_OF_PHY_INT_REGS; i++, j++)
  //    origintfree[i] = j;

  free_int_list = new freelist(NO_OF_PHY_INT_REGS);//, origintfree,
  //			       NO_OF_PHY_INT_REGS - NO_OF_LOG_INT_REGS);
  
  intregbusy = new char[NO_OF_PHY_INT_REGS];
  fpregbusy  = new char[NO_OF_PHY_FP_REGS];
  memset(fpregbusy,
	 0,
	 NO_OF_PHY_FP_REGS * sizeof(char));
  memset(intregbusy,
	 0,
	 NO_OF_PHY_INT_REGS * sizeof(char));

  memset(log_int_reg_file,
         0,
         sizeof(log_int_reg_file));
  memset(log_fp_reg_file,
         0,
         sizeof(log_fp_reg_file));
  memset(phy_int_reg_file,
         0,
         sizeof(phy_int_reg_file));
  memset(phy_fp_reg_file,
         0,
         sizeof(phy_fp_reg_file));

  setup_arch_to_log_table(this);
  

  //---------------------------------------------------------------------------
  // setup TLBs

  if ((TLB_UNIFIED == 0) && ((ITLB_SIZE == 0) || (DTLB_SIZE == 0)))
    {
      TLB_UNIFIED = 1;
      if (DTLB_SIZE == 0)
	{
	  DTLB_TYPE          = ITLB_TYPE;
	  DTLB_SIZE          = ITLB_SIZE;
	  DTLB_ASSOCIATIVITY = ITLB_ASSOCIATIVITY;
	  DTLB_TAGGED        = ITLB_TAGGED;
	}
      else
	{
	  ITLB_TYPE          = DTLB_TYPE;
	  ITLB_SIZE          = DTLB_SIZE;
	  ITLB_ASSOCIATIVITY = DTLB_ASSOCIATIVITY;
	  ITLB_TAGGED        = DTLB_TAGGED;
	}
    }

  if (ITLB_SIZE == 0)
    {
      if (DTLB_SIZE == 0)
	YS__errmsg(proc_id / ARCH_cpus,
		   "At least one TLB size must be non-zero!");

      dtlb = new TLB(this, DTLB_TYPE, DTLB_SIZE, DTLB_ASSOCIATIVITY,
		     DTLB_TAGGED);
      itlb = new TLB(dtlb);
    }
  else
    {
      itlb = new TLB(this, ITLB_TYPE, ITLB_SIZE, ITLB_ASSOCIATIVITY,
		     ITLB_TAGGED);

      if (DTLB_SIZE == 0)
	dtlb = new TLB(itlb);
      else
	dtlb = new TLB(this, DTLB_TYPE, DTLB_SIZE, DTLB_ASSOCIATIVITY,
		       DTLB_TAGGED);
    }

  
  //------------------------------------------------------------------------
  
  /* Initialize the mappers */
  activemaptable = NewMapTable(this);
  if (activemaptable == NULL)
    YS__errmsg(proc_id / ARCH_cpus, "Got a NULL map table entry!!");

  fpmapper  = activemaptable->fmap;
  intmapper = activemaptable->imap;
  for (i = 0; i < NO_OF_LOG_FP_REGS; i++)
    fpmapper[i] = free_fp_list->getfreereg();
  //    fpmapper[i] = i;

  intmapper[0] = 0;
  for (i = 1; i < NO_OF_LOG_INT_REGS; i++)
    intmapper[i] = free_int_list->getfreereg();
  //    intmapper[i] = i;

  //---------------------------------------------------------------------------
  // initialize registers
  
  dtlb_random = DTLB_SIZE - 1;
  itlb_random = ITLB_SIZE - 1;
  
  log_int_reg_file[arch_to_log(this, cwp, PRIV_PSTATE)] = 
    phy_int_reg_file[intmapper[arch_to_log(this, cwp, PRIV_PSTATE)]] = pstate;

  log_int_reg_file[arch_to_log(this, cwp, PRIV_PIL)] =
    phy_int_reg_file[intmapper[arch_to_log(this, cwp, PRIV_PIL)]] = pil;

  log_int_reg_file[arch_to_log(this, cwp, PRIV_TL)] =
    phy_int_reg_file[intmapper[arch_to_log(this, cwp, PRIV_TL)]] = tl;
  
  log_int_reg_file[arch_to_log(this, cwp, PRIV_VER)] =
    phy_int_reg_file[intmapper[arch_to_log(this, cwp, PRIV_VER)]] =
    (42 << 24) | (NUM_TRAPS << 8) | NUM_WINS-1;

  // initialize user & supervisor tick register
 
  log_int_reg_file[arch_to_log(this, cwp, PRIV_TICK)] =
    phy_int_reg_file[intmapper[arch_to_log(this, cwp, PRIV_TICK)]] = 0;
 
  log_int_reg_file[arch_to_log(this, cwp, STATE_TICK)] =
    phy_int_reg_file[intmapper[arch_to_log(this, cwp, STATE_TICK)]] = 0;
  
  log_int_reg_file[arch_to_log(this, cwp, STATE_FPRS)] =
    phy_int_reg_file[intmapper[arch_to_log(this, cwp, STATE_FPRS)]] = FPRS_FEF;
  
  // initialize page table base, random & wired register

  log_int_reg_file[arch_to_log(this, cwp, PRIV_TLB_CONTEXT)] =
    phy_int_reg_file[intmapper[arch_to_log(this, cwp, PRIV_TLB_CONTEXT)]] = 0;
 
  log_int_reg_file[arch_to_log(this, cwp, PRIV_ITLB_RANDOM)] =
    phy_int_reg_file[intmapper[arch_to_log(this, cwp, PRIV_ITLB_RANDOM)]] =
    itlb_random;
 
  log_int_reg_file[arch_to_log(this, cwp, PRIV_DTLB_RANDOM)] =
    phy_int_reg_file[intmapper[arch_to_log(this, cwp, PRIV_DTLB_RANDOM)]] =
    dtlb_random;
 
  log_int_reg_file[arch_to_log(this, cwp, PRIV_ITLB_WIRED)] =
    phy_int_reg_file[intmapper[arch_to_log(this, cwp, PRIV_ITLB_WIRED)]] =
    itlb_wired;
 
  log_int_reg_file[arch_to_log(this, cwp, PRIV_DTLB_WIRED)] =
    phy_int_reg_file[intmapper[arch_to_log(this, cwp, PRIV_DTLB_WIRED)]] =
    dtlb_wired;

  //------------------------------------------------------------------------
  /* Initialize Ready Queues */
  for (i = 0; i < numUTYPES; i++)
    {
      ReadyQueues[i].start(MAX_ACTIVE_INSTS);
      active_instr[i] = 0;
    }

  max_active_instr[uALU] = MAX_ALU_OPS;
  max_active_instr[uFP]  = MAX_FPU_OPS;
  max_active_instr[uMEM] = MAX_MEM_OPS;

  ldissues = 0;

  DELAY = 1;
  stall_the_rest = 0;
  type_of_stall_rest = eNOEFF_LOSS;
  stalledeff = 0;

  fetch_queue_size = FETCH_QUEUE_SIZE;   // number of entries in the fetch q 

  fetch_pc   = 0;                        // the next pc to be fetched
  fetch_done = 1;
  fetch_queue = new Queue<fetch_queue_entry>;
  inst_save = NULL;

  in_exception = NULL;

  // Prediction
  copymappernext = 0;
  unpredbranch = 0;
  BPBSetup();                            // setup branch prediction buffer
  RASSetup();                            // setup RAS


  // Prefetch
  if (Prefetch)
    {
      typedef instance *instp;
      max_prefs = MEM_UNITS;
      prefrdy = new instp[MEM_UNITS];
    }

#ifndef STORE_ORDERING
  StoresToMem = 0;
  SStag = LStag = SLtag = LLtag = MEMISSUEtag = -1;
#endif
  ReadyUnissuedStores = 0;
  sync = 0;

  //-------------------------------------------------------------------------
  // Statistics

  start_time = 0;
  start_icount = 0;
  graduates = 0;
  bpb_good_predicts = 0;
  bpb_bad_predicts  = 0;
  ras_good_predicts = 0;
  ras_bad_predicts  = 0;
  ras_underflows    = 0;
  ras_overflows     = 0;

  ldspecs = 0;
  last_counted = 0;

  for (n = 0; n < MAX_EXCEPT; n++)
    {
      exceptions[n] = 0;
      graduated[n] = 0;
      cycles[n] = 0;
      start_cycle[n] = 0;
      start_graduated[n] = 0;
    }

  total_halted = 0;
  mem_refs = 0;
 
  sim_start_time = time(NULL);