memprocess.cc

ml-rsim 多处理器模拟器 支持类bsd操作系统

/*
 * Copyright (c) 2002 The Board of Trustees of the University of Illinois and
 *                    William Marsh Rice University
 * Copyright (c) 2002 The University of Utah
 * Copyright (c) 2002 The University of Notre Dame du Lac
 *
 * All rights reserved.
 *
 * Based on RSIM 1.0, developed by:
 *   Professor Sarita Adve's RSIM research group
 *   University of Illinois at Urbana-Champaign and
     William Marsh Rice University
 *   http://www.cs.uiuc.edu/rsim and http://www.ece.rice.edu/~rsim/dist.html
 * ML-RSIM/URSIM extensions by:
 *   The Impulse Research Group, University of Utah
 *   http://www.cs.utah.edu/impulse
 *   Lambert Schaelicke, University of Utah and University of Notre Dame du Lac
 *   http://www.cse.nd.edu/~lambert
 *   Mike Parker, University of Utah
 *   http://www.cs.utah.edu/~map
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal with the Software without restriction, including without
 * limitation the rights to use, copy, modify, merge, publish, distribute,
 * sublicense, and/or sell copies of the Software, and to permit persons to
 * whom the Software is furnished to do so, subject to the following
 * conditions:
 *
 * 1. Redistributions of source code must retain the above copyright notice,
 *    this list of conditions and the following disclaimers. 
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimers in the
 *    documentation and/or other materials provided with the distribution.
 * 3. Neither the names of Professor Sarita Adve's RSIM research group,
 *    the University of Illinois at Urbana-Champaign, William Marsh Rice
 *    University, nor the names of its contributors may be used to endorse
 *    or promote products derived from this Software without specific prior
 *    written permission. 
 * 4. Neither the names of the ML-RSIM project, the URSIM project, the
 *    Impulse research group, the University of Utah, the University of
 *    Notre Dame du Lac, nor the names of its contributors may be used to
 *    endorse or promote products derived from this software without specific
 *    prior written permission. 
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS WITH THE SOFTWARE. 
 */

#include <limits.h>

#define min(a, b)               ((a) > (b) ? (b) : (a))

extern "C"
{
#include "sim_main/simsys.h"
#include "Caches/req.h"
} 

#include "Processor/procstate.h"
#include "Processor/mainsim.h"
#include "Processor/branchpred.h"
#include "Processor/simio.h"
#include "Processor/fastnews.h"
#include "Processor/tagcvt.hh"
#include "Processor/active.hh"
#include "Processor/procstate.hh"
#include "Processor/memunit.h"
#include "Processor/exec.h"
#include "Processor/branchpred.hh"
#include "Processor/pagetable.h"

#include "Processor/fetch_queue.h"
#include "Processor/fastnews.h"

#include "Processor/memunit.hh"
#include "Processor/stallq.hh"


/*
 * IssuePrefetch : Send prefetches down to the memory heirarchy
 */
int IssuePrefetch(ProcState *proc, unsigned addr, int level, int excl, 
		  long long inst_tag)
{
#ifdef COREFILE
  if (proc->curr_cycle > DEBUG_TIME)
    fprintf(corefile, "Processor %d sending out %s prefetch on address %d\n",
	    proc->proc_id, excl ? "exclusive" : "shared", addr);
#endif


  DCache_recv_addr(proc->proc_id, NULL, inst_tag, addr,
		   excl ? WRITE : READ, 4, 0, level);

  return 0;
}



/*****************************************************************************/
/* Uncached Buffer - conditional flush support functions                     */
/*****************************************************************************/
 
extern "C" int IsFlushCond(instance *inst)
{
  return (inst->code.instruction == iSWAP);
}



extern "C" int CheckFlushCond(REQ* req, int count)
{
  return(req->d.proc_data.inst->rs1vali == count);
}
 

extern "C" unsigned GetProcContext(int node, int pnum)
{
  ProcState *proc = AllProcs[node * ARCH_cpus + pnum];
  
  return(proc->log_int_reg_file[arch_to_log(proc, proc->cwp,
						   PRIV_TLB_CONTEXT)]);
}

 
extern "C" void UpdateFlushCond(REQ* req, int val)
{
  req->d.proc_data.inst->rdvali = val;

  req->hit_type = IOHIT;
  req->miss_type1 = req->miss_type2 = UNCACHED;
  req->d.proc_data.inst->global_perform = 1;
}



extern "C" void CompleteFlushCond(REQ* req, int count)
{
  req->d.proc_data.inst->rdvali = count;
  
  req->hit_type = IOHIT;
  req->miss_type1 = req->miss_type2 = UNCACHED;
  req->d.proc_data.inst->global_perform = 1;
  MemDoneHeapInsert(req, (HIT_TYPE)(req->hit_type));
}



/*****************************************************************************/
/* MemDoneHeapInsert :  Wrapper around MemDoneHeap.Insert + updates stats    */
/*****************************************************************************/

extern "C" void MemDoneHeapInsert(REQ *req, HIT_TYPE hit_type)       
{
  ProcState *proc    = AllProcs[req->d.proc_data.proc_id];
  instance  *inst    = req->d.proc_data.inst;
  long long inst_tag = req->d.proc_data.inst_tag;

  if (req->prefetch)
    return;
  
#if 0
#ifdef COREFILE
  if (YS__Simtime > DEBUG_TIME)
    fprintf(simout, "RSIM processor completes address %X tag %lld "
	    "inst_tag %d @ %g\n",
	    req->address, req->tag, req->d.proc_data.inst_tag, YS__Simtime);
#endif
#endif

  if (inst->tag == inst_tag)
    {
      /* otherwise, it's been reassigned as a result of exception */
      proc->MemDoneHeap.insert(proc->curr_cycle, inst, inst_tag);
      inst->miss = hit_type;
      inst->latepf = req->prefetched_late;
      return;
    }
}



/*****************************************************************************/
/* MemDoneHeapInsertSpec :  Wrapper around MemDoneHeap.Insert (speculative)  */
/*****************************************************************************/
 
 
extern "C" void* MemDoneHeapInsertSpec(REQ *req, HIT_TYPE hit_type)
{
  ProcState *proc    = AllProcs[req->d.proc_data.proc_id];
  instance *inst     = req->d.proc_data.inst;
  instance *new_inst;
  long long inst_tag = req->d.proc_data.inst_tag;


  new_inst = new instance(inst);

  if (!req->prefetch)
    {

#if 0      
#ifdef COREFILE
      if (YS__Simtime > DEBUG_TIME)
        fprintf(simout,
                "RSIM processor completes address %ld tag %lld inst_tag %ld @ %g\n",
                req->address,
                req->tag,
                req->d.proc_data.inst_tag,
                YS__Simtime);
#endif
#endif
 
      
      // otherwise, it's been reassigned as a result of exception, or flushed
      if (inst->tag == inst_tag)
        {
          inst->global_perform = 1;
 
          proc->MemDoneHeap.insert(proc->curr_cycle, inst, inst_tag);
 
          // if (req->handled != reqL1HIT)
	  inst->miss = hit_type;
	  inst->latepf = req->prefetched_late;
        }
    }
 
  return new_inst;
}


/*****************************************************************************/
/* ReturnMemopSpec :  Return instance copy made by 'MemDoneHeapInsertSpec'   */
/*****************************************************************************/
 
 
extern "C" void ReturnMemopSpec(REQ *req)
{
  instance *inst = req->d.proc_data.inst;

  delete inst;
}




/*****************************************************************************/
/* GlobalPerform : Make the effect of reads and writes visible to the        */
/*               : simulator (read/write the unix address space)             */
/*****************************************************************************/

extern "C" void PerformData(REQ * req)
{
  instance *inst = req->d.proc_data.inst;

  if (inst == NULL ||
      //      inst->global_perform ||
      req->prefetch)