instruction.h

ml-rsim 多处理器模拟器 支持类bsd操作系统

  FSUBs = 0x45,
  FSUBd,
  FSUBq, 
  FMULs = 0x49,
  FMULd,
  FMULq, 
  FDIVs = 0x4d,
  FDIVd,
  FDIVq, 
  FsMULd= 0x69, 
  FdMULq= 0x6e, 
  FsTOx = 0x81,
  FdTOx,
  FqTOx,
  FxTOs, 
  FxTOd = 0x88, 
  FxToq = 0x8c, 
  FiTOs = 0xc4, 
  FdTOs = 0xc6,
  FqTOs,
  FiTOd,
  FsTOd, 
  FqTOd = 0xcb,
  FiTOq,
  FsTOq,
  FdTOq, 
  FsTOi = 0xd1,
  FdTOi,
  FqTOi
};



/* 
 * Within FPop2, look at opf, bits 13-5 
 */
enum FPop2_ops
{
  FMOVs0 = 0x01,
  FMOVd0,
  FMOVq0, 
  FMOVs1 = 0x41,
  FMOVd1,
  FMOVq1, 
  FMOVs2 = 0x81,
  FMOVd2,
  FMOVq2, 
  FMOVs3 = 0xc1,
  FMOVd3,
  FMOVq3, 

  FMOVsi = 0x101,
  FMOVdi,
  FMOVqi, 
  FMOVsx = 0x181,
  FMOVdx,
  FMOVqx, 

  FCMPs  = 0x51,
  FCMPd,
  FCMPq, 
  FCMPEs = 0x55,
  FCMPEd,
  FCMPEq, 

  FMOVRsZ   = 0x25,
  FMOVRdZ,
  FMOVRqZ, 
  FMOVRsLEZ = 0x45,
  FMOVRdLEZ,
  FMOVRqLEZ, 
  FMOVRsLZ  = 0x65,
  FMOVRdLZ,
  FMOVRqLZ, 

  FMOVRsNZ  = 0xa5,
  FMOVRdNZ,
  FMOVRqNZ, 
  FMOVRsGZ  = 0xc5,
  FMOVRdGZ,
  FMOVRqGZ, 
  FMOVRsGEZ = 0xe5,
  FMOVRdGEZ,
  FMOVRqGEZ
};




/* within MEM, look at op3, which is bits 24-19 */
enum mem_ops
{
  LDUW,
  LDUB,
  LDUH,
  LDD,
  STW,
  STB,
  STH,
  STD, 
  LDSW,
  LDSB,
  LDSH,
  LDX,
  memRES1,
  LDSTUB,
  STX,
  SWAP, 
  LDUWA,
  LDUBA,
  LDUHA,
  LDDA,
  STWA,
  STBA,
  STHA,
  STDA, 
  LDSWA,
  LDSBA,
  LDSHA,
  LDXA,
  memRES2,
  LDSTUBA,
  STXA,
  SWAPA, 
  LDF,
  LDFSR,
  LDQF,
  LDDF,
  STF,
  STFSR,
  STQF,
  STDF, 
  memRES3,
  memRES4,
  memRES5,
  memRES6,
  memRES7, 
  PREFETCH,
  memRES8,
  memRES9, 
  LDFA,
  memRES10,
  LDQFA,
  LDDFA,
  STFA,
  memRES11,
  STQFA,
  STDFA, 
  memRES12,
  memRES13,
  memRES14,
  memRES15, 
  CASA,
  PREFETCHA,
  CASXA,
  memRES16 
};




/* 
 * cond field used in branches, bits 28-25 
 */
enum bp_conds
{
  Nb,
  Eb,
  LEb,
  Lb,
  LEUb,
  CSb,
  NEGb,
  VSb,
  Ab,
  NEb,
  Gb,
  GEb,
  GUb,
  CCb, 
  POSb,
  VCb
};



enum fp_conds
{
  Nf,
  NEf,
  LGf,
  ULf,
  Lf,
  UGf,
  Gf,
  Uf,
  Af,
  Ef,
  UEf,
  GEf,
  UGEf,
  LEf,
  ULEf,
  Of
};




/* 
 * the rcond field used in BPr, MOVr, and FMOVr 
 */
enum rcond
{
  rRES1,
  Zr,
  LEr,
  Lr,
  rRES2,
  Nr,
  Gr,
  GEr
};




/***************************************************************************/
/******************* Memory barrier related definitions ********************/
/***************************************************************************/

#define iMEMBAR 	iarithSPECIAL1
#define MB_StoreStore 	8
#define MB_LoadStore 	4
#define MB_StoreLoad 	2
#define MB_LoadLoad 	1

#define MB_LOOKASIDE    1
#define MB_MEMISSUE 	2
#define MB_SYNC         4

#define PREF_NRD 	0
#define PREF_1RD 	1
#define PREF_NWT 	2
#define PREF_1WT 	3




/***************************************************************************/
/*************** Window pointer change enumerated type defintion ***********/
/***************************************************************************/

#define WPC_RESTORE  -1
#define WPC_NONE      0
#define WPC_SAVE      1
#define WPC_FLUSHW  100

#if 0
enum WPC
{
  WPC_RESTORE = -1,          /* decrement the current window pointer (cwp) */
  WPC_NONE    = 0,           /* retain the same current window pointer     */
  WPC_SAVE    = 1,           /* increment the current window pointer       */
  WPC_FLUSHW  = 100          /* flush window - does not really change cwp  */
};
#endif


/***************************************************************************/
/********** Static instruction structure definition ************************/
/***************************************************************************/

struct instr
{
  INSTRUCTION instruction;

  /* WRITTEN REGISTERS */
  char rd;	              /* destination register                      */
  char rcc; 	              /* destination condition code register       */

  /* READ REGISTERS */
  char rs1;	              /* source register 1                         */
  char rs2;	              /* source register 2                         */
  char rscc;	              /* source condition code register            */

  /* AUXILIARY DATA */  
  char aux1;				
  char taken;	              /* taken hint for branches                   */
  char annul;	              /* annul bit for branches                    */

  /* BIT FIELDS */
  REGTYPE rd_regtype; 	      /* is rd a floating point?                   */
  REGTYPE rs1_regtype;	      /* is rs1 a floating point?                  */
  REGTYPE rs2_regtype;	      /* is rs2 a floating point?                  */
  char cond_branch; 	      /* indicate conditional branch               */
  char uncond_branch;         /* indicate non-conditional branch
		       	          0 for other, 
				  1 for address calc needed, 
				  2 for immediate address, 
				  3 for "call", 
				  4 for probable return (addr calc needed) */

  char wpchange; 	/* (was WPC) indicate instructions that change window
			   pointer +1 for save, -1 for restore */

  char sync;

  int  aux2;
  int  imm;		      /* immediate field                           */

  
  /* member functions */

  instr(): instruction(iRESERVED), aux1(0), aux2(0), imm(0)
  {
    rd = rcc = rs1 = rs2 = rscc = 0;
    rd_regtype = rs1_regtype = rs2_regtype = REG_INT;
    taken = annul = cond_branch = uncond_branch = 0;
    wpchange = WPC_NONE;
    sync = 0;
  }

  
  instr(INSTRUCTION i): instruction(i), aux1(0), aux2(0), imm(0)
  {
    rd = rcc = rs1 = rs2 = rscc = 0;
    rd_regtype = rs1_regtype = rs2_regtype = REG_INT;
    taken = annul = cond_branch = uncond_branch = 0;
    wpchange = WPC_NONE;
    sync = 0;
  }

  
  instr(INSTRUCTION in_instruction,
	char in_rd, char in_rcc, char in_rs1, char in_rs2, char in_rscc,
	char in_aux1, int in_aux2, int in_imm, 
	REGTYPE in_rd_regtype, REGTYPE in_rs1_regtype, REGTYPE in_rs2_regtype,
	char in_taken, char in_annul,
	char in_cond_branch, char in_uncond_branch, 
	char in_wpchange, char in_sync)
  {
    instruction = in_instruction;

    rd            = in_rd;
    rcc           = in_rcc;
    rs1           = in_rs1;
    rs2           = in_rs2;
    rscc          = in_rscc;
    aux1          = in_aux1;
    aux2          = in_aux2;
    imm           = in_imm;

    rd_regtype    = in_rd_regtype;
    rs1_regtype   = in_rs1_regtype;
    rs2_regtype   = in_rs2_regtype;
    taken         = in_taken;
    annul         = in_annul;
    cond_branch   = in_cond_branch;
    uncond_branch = in_uncond_branch;
    wpchange      = in_wpchange;
    sync          = in_sync;
  }

  
  /* writing instruction to a file */
  void output(FILE *out) 
  {
    fwrite((const char*)this, (size_t)sizeof(instr), 1, out);
  }

  
  /* reading instruction from a file */
  void input(FILE *in) 
  {
    fread((char *)this, (size_t)sizeof(instr), 1, in);
  }

  
  void copy(instr *i)
  {
    long long *src, *dest;
    int n;

    src  = (long long*)this;
    dest = (long long*)i;

    for (n = 0; n < sizeof(instr) / sizeof(long long); n++)
      dest[n] = src[n];
  }
  
  
  /* printing a file */
  void print()
  {
#if 0
#ifdef COREFILE
    extern FILE *corefile;
    if (GetSimTime() > DEBUG_TIME)
      fprintf(corefile, "%-12.11s%d\t%d\t%d\t%d\t%d\t%d\t%d\n", 
	      inames[instruction], rd, rcc, rs1, rs2, aux1, aux2, imm);
#endif
#endif
  }
};





#define Extract(v, hi, lo) ((v >> lo) & (((unsigned)-1) >> (31-hi+lo)))

typedef int  (*IMF)(instr *, unsigned); /* instruction manipulation function */
typedef void (*IEF)(instr *);           /* instruction execution function */

extern IMF toplevelop[4];        /* top level classification of instructions */
extern IMF brop2[8];             /* branch operations */
extern INSTRUCTION ibrop2[8];
extern IMF arithop[64];          /* arithmetic operations */
extern INSTRUCTION iarithop[64];
extern IMF fpop1[512];           /* floating point operations */
extern INSTRUCTION ifpop1[512];
extern IMF fpop2[512];           /* floating point operations -- (move, etc) */
extern INSTRUCTION ifpop2[512];
extern IMF memop3[64];           /* memory operations */
extern INSTRUCTION imemop3[64];

#endif