📄 instruction.h
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/* * Copyright (c) 2002 The Board of Trustees of the University of Illinois and * William Marsh Rice University * Copyright (c) 2002 The University of Utah * Copyright (c) 2002 The University of Notre Dame du Lac * * All rights reserved. * * Based on RSIM 1.0, developed by: * Professor Sarita Adve's RSIM research group * University of Illinois at Urbana-Champaign and William Marsh Rice University * http://www.cs.uiuc.edu/rsim and http://www.ece.rice.edu/~rsim/dist.html * ML-RSIM/URSIM extensions by: * The Impulse Research Group, University of Utah * http://www.cs.utah.edu/impulse * Lambert Schaelicke, University of Utah and University of Notre Dame du Lac * http://www.cse.nd.edu/~lambert * Mike Parker, University of Utah * http://www.cs.utah.edu/~map * * Permission is hereby granted, free of charge, to any person obtaining a * copy of this software and associated documentation files (the "Software"), * to deal with the Software without restriction, including without * limitation the rights to use, copy, modify, merge, publish, distribute, * sublicense, and/or sell copies of the Software, and to permit persons to * whom the Software is furnished to do so, subject to the following * conditions: * * 1. Redistributions of source code must retain the above copyright notice, * this list of conditions and the following disclaimers. * 2. Redistributions in binary form must reproduce the above copyright * notice, this list of conditions and the following disclaimers in the * documentation and/or other materials provided with the distribution. * 3. Neither the names of Professor Sarita Adve's RSIM research group, * the University of Illinois at Urbana-Champaign, William Marsh Rice * University, nor the names of its contributors may be used to endorse * or promote products derived from this Software without specific prior * written permission. * 4. Neither the names of the ML-RSIM project, the URSIM project, the * Impulse research group, the University of Utah, the University of * Notre Dame du Lac, nor the names of its contributors may be used to * endorse or promote products derived from this software without specific * prior written permission. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * THE CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR * OTHER DEALINGS WITH THE SOFTWARE. */#ifndef __RSIM_INSTRUCTION_H__#define __RSIM_INSTRUCTION_H__/**************************************************************************//**** All INSTRUCTIONS enumerated -- SPARC architecture-specific **********//**************************************************************************/typedef unsigned char INSTRUCTION;#define iRESERVED (INSTRUCTION)0#define iCALL (INSTRUCTION)1#define iILLTRAP (INSTRUCTION)2#define iBPcc (INSTRUCTION)3#define iBicc (INSTRUCTION)4#define iBPr (INSTRUCTION)5#define iSETHI (INSTRUCTION)6#define iFBPfcc (INSTRUCTION)7#define iFBfcc (INSTRUCTION)8#define iADD (INSTRUCTION)9#define iAND (INSTRUCTION)10#define iOR (INSTRUCTION)11#define iXOR (INSTRUCTION)12#define iSUB (INSTRUCTION)13#define iANDN (INSTRUCTION)14#define iORN (INSTRUCTION)15#define iXNOR (INSTRUCTION)16#define iADDC (INSTRUCTION)17#define iMULX (INSTRUCTION)18#define iUMUL (INSTRUCTION)19#define iSMUL (INSTRUCTION)20#define iSUBC (INSTRUCTION)21#define iUDIVX (INSTRUCTION)22#define iUDIV (INSTRUCTION)23#define iSDIV (INSTRUCTION)24#define iADDcc (INSTRUCTION)25#define iANDcc (INSTRUCTION)26#define iORcc (INSTRUCTION)27#define iXORcc (INSTRUCTION)28#define iSUBcc (INSTRUCTION)29#define iANDNcc (INSTRUCTION)30#define iORNcc (INSTRUCTION)31#define iXNORcc (INSTRUCTION)32#define iADDCcc (INSTRUCTION)33#define iUMULcc (INSTRUCTION)34#define iSMULcc (INSTRUCTION)35#define iSUBCcc (INSTRUCTION)36#define iUDIVcc (INSTRUCTION)37#define iSDIVcc (INSTRUCTION)38#define iTADDcc (INSTRUCTION)39#define iTSUBcc (INSTRUCTION)40#define iTADDccTV (INSTRUCTION)41#define iTSUBccTV (INSTRUCTION)42#define iMULScc (INSTRUCTION)43#define iSLL (INSTRUCTION)44#define iSRL (INSTRUCTION)45#define iSRA (INSTRUCTION)46#define iarithSPECIAL1 (INSTRUCTION)47 /* includes RDY, RDCCR, MEMBAR, etc */#define iRDPR (INSTRUCTION)48#define iFLUSHW (INSTRUCTION)49#define iMOVcc (INSTRUCTION)50#define iSDIVX (INSTRUCTION)51#define iPOPC (INSTRUCTION)52#define iMOVR (INSTRUCTION)53#define iarithSPECIAL2 (INSTRUCTION)54 /* WRY, etc */#define iSAVRESTD (INSTRUCTION)55#define iWRPR (INSTRUCTION)56#define iIMPDEP1 (INSTRUCTION)57#define iIMPDEP2 (INSTRUCTION)58#define iJMPL (INSTRUCTION)59#define iRETURN (INSTRUCTION)60#define iTcc (INSTRUCTION)61#define iFLUSH (INSTRUCTION)62#define iSAVE (INSTRUCTION)63#define iRESTORE (INSTRUCTION)64#define iDONERETRY (INSTRUCTION)65#define iFMOVs (INSTRUCTION)66#define iFMOVd (INSTRUCTION)67#define iFMOVq (INSTRUCTION)68#define iFNEGs (INSTRUCTION)69#define iFNEGd (INSTRUCTION)70#define iFNEGq (INSTRUCTION)71#define iFABSs (INSTRUCTION)72#define iFABSd (INSTRUCTION)73 #define iFABSq (INSTRUCTION)74#define iFSQRTs (INSTRUCTION)75#define iFSQRTd (INSTRUCTION)76#define iFSQRTq (INSTRUCTION)77#define iFADDs (INSTRUCTION)78#define iFADDd (INSTRUCTION)79#define iFADDq (INSTRUCTION)80#define iFSUBs (INSTRUCTION)81 #define iFSUBd (INSTRUCTION)82#define iFSUBq (INSTRUCTION)83#define iFMULs (INSTRUCTION)84#define iFMULd (INSTRUCTION)85#define iFMULq (INSTRUCTION)86#define iFDIVs (INSTRUCTION)87#define iFDIVd (INSTRUCTION)88#define iFDIVq (INSTRUCTION)89 #define iFsMULd (INSTRUCTION)90#define iFdMULq (INSTRUCTION)91#define iFsTOx (INSTRUCTION)92#define iFdTOx (INSTRUCTION)93#define iFqTOx (INSTRUCTION)94#define iFxTOs (INSTRUCTION)95#define iFxTOd (INSTRUCTION)96#define iFxToq (INSTRUCTION)97 #define iFiTOs (INSTRUCTION)98#define iFdTOs (INSTRUCTION)99#define iFqTOs (INSTRUCTION)100#define iFiTOd (INSTRUCTION)101#define iFsTOd (INSTRUCTION)102#define iFqTOd (INSTRUCTION)103#define iFiTOq (INSTRUCTION)104#define iFsTOq (INSTRUCTION)105 #define iFdTOq (INSTRUCTION)106#define iFsTOi (INSTRUCTION)107#define iFdTOi (INSTRUCTION)108#define iFqTOi (INSTRUCTION)109#define iFMOVs0 (INSTRUCTION)110#define iFMOVd0 (INSTRUCTION)111#define iFMOVq0 (INSTRUCTION)112#define iFMOVs1 (INSTRUCTION)113 #define iFMOVd1 (INSTRUCTION)114#define iFMOVq1 (INSTRUCTION)115#define iFMOVs2 (INSTRUCTION)116#define iFMOVd2 (INSTRUCTION)117#define iFMOVq2 (INSTRUCTION)118#define iFMOVs3 (INSTRUCTION)119#define iFMOVd3 (INSTRUCTION)120#define iFMOVq3 (INSTRUCTION)121 #define iFMOVsi (INSTRUCTION)122#define iFMOVdi (INSTRUCTION)123#define iFMOVqi (INSTRUCTION)124#define iFMOVsx (INSTRUCTION)125#define iFMOVdx (INSTRUCTION)126#define iFMOVqx (INSTRUCTION)127#define iFCMPs (INSTRUCTION)128#define iFCMPd (INSTRUCTION)129#define iFCMPq (INSTRUCTION)130#define iFCMPEs (INSTRUCTION)131#define iFCMPEd (INSTRUCTION)132#define iFCMPEq (INSTRUCTION)133#define iFMOVRsZ (INSTRUCTION)134#define iFMOVRdZ (INSTRUCTION)135#define iFMOVRqZ (INSTRUCTION)136#define iFMOVRsLEZ (INSTRUCTION)137#define iFMOVRdLEZ (INSTRUCTION)138#define iFMOVRqLEZ (INSTRUCTION)139#define iFMOVRsLZ (INSTRUCTION)140#define iFMOVRdLZ (INSTRUCTION)141#define iFMOVRqLZ (INSTRUCTION)142#define iFMOVRsNZ (INSTRUCTION)143#define iFMOVRdNZ (INSTRUCTION)144#define iFMOVRqNZ (INSTRUCTION)145#define iFMOVRsGZ (INSTRUCTION)146#define iFMOVRdGZ (INSTRUCTION)147#define iFMOVRqGZ (INSTRUCTION)148#define iFMOVRsGEZ (INSTRUCTION)149#define iFMOVRdGEZ (INSTRUCTION)150#define iFMOVRqGEZ (INSTRUCTION)151#define iLDUW (INSTRUCTION)152#define iLDUB (INSTRUCTION)153#define iLDUH (INSTRUCTION)154#define iLDD (INSTRUCTION)155#define iSTW (INSTRUCTION)156#define iSTB (INSTRUCTION)157#define iSTH (INSTRUCTION)158#define iSTD (INSTRUCTION)159#define iLDSW (INSTRUCTION)160#define iLDSB (INSTRUCTION)161#define iLDSH (INSTRUCTION)162#define iLDX (INSTRUCTION)163#define iLDSTUB (INSTRUCTION)164#define iSTX (INSTRUCTION)165#define iSWAP (INSTRUCTION)166#define iLDUWA (INSTRUCTION)167#define iLDUBA (INSTRUCTION)168#define iLDUHA (INSTRUCTION)169#define iLDDA (INSTRUCTION)170#define iSTWA (INSTRUCTION)171#define iSTBA (INSTRUCTION)172#define iSTHA (INSTRUCTION)173#define iSTDA (INSTRUCTION)174#define iLDSWA (INSTRUCTION)175#define iLDSBA (INSTRUCTION)176#define iLDSHA (INSTRUCTION)177#define iLDXA (INSTRUCTION)178#define iLDSTUBA (INSTRUCTION)179#define iSTXA (INSTRUCTION)180#define iSWAPA (INSTRUCTION)181#define iLDF (INSTRUCTION)182#define iLDFSR (INSTRUCTION)183#define iLDXFSR (INSTRUCTION)184#define iLDQF (INSTRUCTION)185#define iLDDF (INSTRUCTION)186#define iSTF (INSTRUCTION)187#define iSTFSR (INSTRUCTION)188#define iSTXFSR (INSTRUCTION)189#define iSTQF (INSTRUCTION)190#define iSTDF (INSTRUCTION)191#define iPREFETCH (INSTRUCTION)192#define iLDFA (INSTRUCTION)193#define iLDQFA (INSTRUCTION)194#define iLDDFA (INSTRUCTION)195#define iSTFA (INSTRUCTION)196#define iSTQFA (INSTRUCTION)197#define iSTDFA (INSTRUCTION)198#define iCASA (INSTRUCTION)199#define iPREFETCHA (INSTRUCTION)200#define iCASXA (INSTRUCTION)201#define iRWSD (INSTRUCTION)202#define iRWWT_I (INSTRUCTION)203#define iRWWTI_I (INSTRUCTION)204#define iRWWS_I (INSTRUCTION)205#define iRWWSI_I (INSTRUCTION)206 /* various WriteThrough RW */#define iRWWT_F (INSTRUCTION)207#define iRWWTI_F (INSTRUCTION)208#define iRWWS_F (INSTRUCTION)209#define iRWWSI_F (INSTRUCTION)210 /* various WriteSend RW */#define numINSTRS (INSTRUCTION)211/* NOTE: THIS MUST BE THE LAST ENTRY HERE -- PUT ALL NEW INSTRUCTIONS BEFORE THIS ONE!!! *//* instruction names array */extern const char *inames[numINSTRS]; /* functions to simulate the instructions */struct ProcState;class instance;typedef void (*EFP)(instance *, ProcState *);extern EFP instr_func[numINSTRS]; /**************************************************************************//************* INSTRUCTIONS types -- SPARC architecture-specific **********//**************************************************************************//* * First are bits 31 and 30 */enum op{ BRANCH = 0, CALL = 1, ARITH = 2, MEM = 3};/* * Now, within BRANCH, let's look at field op2, bits 24-22. We'll keep * cond/rcond as a field in our instruction structure and do a case * statement on that. */enum br_op2{ ILLTRAP = 0, BPcc = 1, Bicc = 2, BPr = 3, SETHI = 4, FBPfcc = 5, FBfcc = 6, brRES = 7};/* * within ARITH, look at op3, which is bits 24-19 */enum arith_ops{ ADD, AND, OR, XOR, SUB, ANDN, ORN, XNOR, ADDC, MULX, UMUL, SMUL, SUBC, UDIVX, UDIV, SDIV, ADDcc, ANDcc, ORcc, XORcc, SUBcc, ANDNcc, ORNcc, XNORcc, ADDCcc, arithRES1, UMULcc, SMULcc, SUBCcc, arithRES2, UDIVcc, SDIVcc, TADDcc, TSUBcc, TADDccTV, TSUBccTV, MULScc, SLL, SRL, SRA, arithSPECIAL1 /* includes RDY, RDCCR, etc */, arithRES3, RDPR, FLUSHW, MOVcc, SDIVX, POPC, MOVR, arithSPECIAL2 /* includes WRY, etc */, SAVRESTD, WRPR, arithRES4, FPop1, FPop2, IMPDEP1, IMPDEP2, JMPL, RETURN, Tcc, FLUSH, SAVE, RESTORE, DONERETRY, arithRES5 };/* * Within FPop1, look at opf, bits 13-5 * fill in the table with reserveds, then fill in these spaces separately */enum FPop1_ops{ FMOVs = 0x01, FMOVd, FMOVq, FNEGs = 0x05, FNEGd, FNEGq, FABSs = 0x09, FABSd, FABSq, FSQRTs= 0x29, FSQRTd, FSQRTq, FADDs = 0x41, FADDd, FADDq,
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