except.cc

ml-rsim 多处理器模拟器 支持类bsd操作系统

      
      return(0);

      
      //-----------------------------------------------------------------------
    case iarithSPECIAL2:               // e.g. WR to special regs.
      if (inst->code.aux1)
        proc->phy_int_reg_file[proc->intmapper[inst->lrd]] =
          proc->log_int_reg_file[inst->lrd] =
          inst->rs1vali ^ inst->code.imm;
      else
        proc->phy_int_reg_file[proc->intmapper[inst->lrd]] =
          proc->log_int_reg_file[inst->lrd] =
          inst->rs1vali ^ inst->rs2vali;

      if (inst->code.rd == STATE_TICK)
	proc->tick_base =
	  (long long)YS__Simtime-(long long)proc->log_int_reg_file[inst->lrd]; 
      
      if (inst->code.rd == STATE_PC)
	{
	  proc->pc = proc->log_int_reg_file[inst->lrd];
	  proc->npc = proc->pc + SIZE_OF_SPARC_INSTRUCTION;
	}
      
      return(0);
 

      //-----------------------------------------------------------------------
    case iWRPR:
      if (inst->code.aux1)
        proc->phy_int_reg_file[proc->intmapper[inst->lrd]] =
          proc->log_int_reg_file[inst->lrd] =
          inst->rs1vali ^ inst->code.imm;
      else
        proc->phy_int_reg_file[proc->intmapper[inst->lrd]] =
          proc->log_int_reg_file[inst->lrd] =
          inst->rs1vali ^ inst->rs2vali;


      //-----------------------------------------------------------------------
      // compute new tick base upon write to tick register

      if (inst->code.rd == PRIV_TICK)
	proc->tick_base =
	  (long long)YS__Simtime-(long long)proc->log_int_reg_file[inst->lrd]; 
      

      //-----------------------------------------------------------------------
      // assign window control variables when writing to such a register

      
      if (inst->code.rd == PRIV_CANSAVE)
	proc->cansave    = proc->phy_int_reg_file[proc->intmapper[inst->lrd]];
      if ((proc->cansave > NUM_WINS-1) || (proc->cansave < 0))
	YS__errmsg(proc->proc_id / ARCH_cpus,
		   "Illegal value 0x%X written to CANSAVE at 0x%08X\n",
		   proc->cansave, inst->pc);

      if (inst->code.rd == PRIV_CANRESTORE)
	proc->canrestore = proc->phy_int_reg_file[proc->intmapper[inst->lrd]];
      if ((proc->canrestore > NUM_WINS-1) || (proc->canrestore < 0))
	YS__errmsg(proc->proc_id / ARCH_cpus,
		   "Illegal value 0x%X written to CANRESTORE at 0x%08X\n",
		   proc->canrestore, inst->pc);

      if (inst->code.rd == PRIV_OTHERWIN)
	proc->otherwin = proc->phy_int_reg_file[proc->intmapper[inst->lrd]];
      if ((proc->otherwin > NUM_WINS-1) || (proc->otherwin < 0))
	YS__errmsg(proc->proc_id / ARCH_cpus,
		   "Illegal value 0x%X written to OTHERWIN at 0x%08X\n",
		   proc->otherwin, inst->pc);

      if (inst->code.rd == PRIV_CLEANWIN)
	proc->cleanwin = proc->phy_int_reg_file[proc->intmapper[inst->lrd]];
      if ((proc->cleanwin > NUM_WINS) || (proc->cleanwin < 0))
	YS__errmsg(proc->proc_id / ARCH_cpus,
		   "Illegal value 0x%X written to CLEANWIN at 0x%08X\n",
		   proc->cleanwin, inst->pc);

      if (inst->code.rd == PRIV_CWP)
	proc->cwp = proc->phy_int_reg_file[proc->intmapper[inst->lrd]];
      if ((proc->cwp > NUM_WINS-1) || (proc->cwp < 0))
	YS__errmsg(proc->proc_id / ARCH_cpus,
		   "Illegal value 0x%X written to CWP at 0x%08X\n",
		   proc->cwp, inst->pc);

      
      //-----------------------------------------------------------------------
      // other supervisor state registers

      if (inst->code.rd == PRIV_PSTATE)
	proc->pstate = proc->phy_int_reg_file[proc->intmapper[inst->lrd]];
	
      if (inst->code.rd == PRIV_TL)
	proc->tl = proc->phy_int_reg_file[proc->intmapper[inst->lrd]];

      if (inst->code.rd == PRIV_PIL)
	proc->pil = proc->phy_int_reg_file[proc->intmapper[inst->lrd]];
	

      //-----------------------------------------------------------------------

      if (inst->code.rd == PRIV_ITLB_DATA)         // trigger ITLB entry write
        proc->itlb->
          WriteEntry(proc->
                     phy_int_reg_file[proc->intmapper[arch_to_log(proc,
							 proc->cwp,
							 PRIV_TLB_INDEX)]],
                     proc->
                     phy_int_reg_file[proc->intmapper[arch_to_log(proc,
							 proc->cwp,
							 PRIV_TLB_TAG)]],
                     proc->
                     phy_int_reg_file[proc->intmapper[arch_to_log(proc,
							 proc->cwp,
							 PRIV_TLB_CONTEXT)]],
                     proc->
                     phy_int_reg_file[proc->intmapper[arch_to_log(proc,
							 proc->cwp,
							 PRIV_ITLB_DATA)]]);


      if (inst->code.rd == PRIV_DTLB_DATA)         // trigger DTLB entry write
        proc->dtlb->
          WriteEntry(proc->
                     phy_int_reg_file[proc->intmapper[arch_to_log(proc,
							 proc->cwp,
							 PRIV_TLB_INDEX)]],
                     proc->
                     phy_int_reg_file[proc->intmapper[arch_to_log(proc,
							 proc->cwp,
							 PRIV_TLB_TAG)]],
                     proc->
                     phy_int_reg_file[proc->intmapper[arch_to_log(proc,
							 proc->cwp,
							 PRIV_TLB_CONTEXT)]],
                     proc->
                     phy_int_reg_file[proc->intmapper[arch_to_log(proc,
							 proc->cwp,
							 PRIV_DTLB_DATA)]]);

      
      //-----------------------------------------------------------------------

      if (inst->code.rd == PRIV_ITLB_WIRED)        // reset ITLB random reg.
	{
	  proc->itlb_wired  = proc->phy_int_reg_file[proc->intmapper[inst->lrd]];
	  proc->itlb_random = ITLB_SIZE - 1;
	}
 
      if (inst->code.rd == PRIV_DTLB_WIRED)        // reset ITLB random reg.
	{
	  proc->dtlb_wired  = proc->phy_int_reg_file[proc->intmapper[inst->lrd]];
	  proc->dtlb_random = DTLB_SIZE - 1;
	}
 
      if (inst->code.rd == PRIV_ITLB_RANDOM)
	proc->itlb_random = proc->phy_int_reg_file[proc->intmapper[inst->lrd]];
      
      if (inst->code.rd == PRIV_DTLB_RANDOM)
	proc->dtlb_random = proc->phy_int_reg_file[proc->intmapper[inst->lrd]];


      //-----------------------------------------------------------------------
      
      if (inst->code.rd == PRIV_TLB_COMMAND)
        {
          if (proc->phy_int_reg_file[proc->intmapper[inst->lrd]] == DTLB_CMD_PROBE)
            proc->dtlb->
              ProbeEntry(proc->
                         phy_int_reg_file[proc->intmapper[arch_to_log(proc,
						          proc->cwp,
						          PRIV_TLB_TAG)]],
                         &(proc->
                         phy_int_reg_file[proc->intmapper[arch_to_log(proc,
						          proc->cwp,
						          PRIV_TLB_INDEX)]]));

          if (proc->phy_int_reg_file[proc->intmapper[inst->lrd]] == ITLB_CMD_PROBE)
            proc->itlb->
              ProbeEntry(proc->
                         phy_int_reg_file[proc->intmapper[arch_to_log(proc,
						          proc->cwp,
						          PRIV_TLB_TAG)]],
                         &(proc->
                         phy_int_reg_file[proc->intmapper[arch_to_log(proc,
						          proc->cwp,
						          PRIV_TLB_INDEX)]]));
	  
          proc->log_int_reg_file[arch_to_log(proc,
					     proc->cwp,
					     PRIV_TLB_INDEX)] =
            proc->phy_int_reg_file[proc->intmapper[arch_to_log(proc,
							   proc->cwp,
						           PRIV_TLB_INDEX)]];
 
          if (proc->phy_int_reg_file[proc->intmapper[inst->lrd]] == ITLB_CMD_FLUSH)
            proc->itlb->Flush();

          if (proc->phy_int_reg_file[proc->intmapper[inst->lrd]] == DTLB_CMD_FLUSH)
            proc->dtlb->Flush();
        }
      return 0;

      
      //-----------------------------------------------------------------------
    case iRDPR:
      proc->log_int_reg_file[arch_to_log(proc, proc->cwp,
						PRIV_TICK)] =
	proc->phy_int_reg_file[proc->intmapper[arch_to_log(proc, proc->cwp,
							   PRIV_TICK)]] =
	(unsigned int)((long long)YS__Simtime - proc->tick_base);

      proc->log_int_reg_file[arch_to_log(proc, proc->cwp, PRIV_CWP)] =
	proc->phy_int_reg_file[proc->intmapper[arch_to_log(proc, proc->cwp,
							   PRIV_CWP)]] =
	proc->cwp;
      
      proc->log_int_reg_file[arch_to_log(proc, proc->cwp, PRIV_CANSAVE)] =
	proc->phy_int_reg_file[proc->intmapper[arch_to_log(proc, proc->cwp,
							   PRIV_CANSAVE)]] =
	proc->cansave;
      
      proc->log_int_reg_file[arch_to_log(proc, proc->cwp, PRIV_CANRESTORE)] =
	proc->phy_int_reg_file[proc->intmapper[arch_to_log(proc, proc->cwp,
							   PRIV_CANRESTORE)]] =
	proc->canrestore;
      
      proc->log_int_reg_file[arch_to_log(proc, proc->cwp, PRIV_OTHERWIN)] =
	proc->phy_int_reg_file[proc->intmapper[arch_to_log(proc, proc->cwp,
							   PRIV_OTHERWIN)]] =
	proc->otherwin;

      proc->log_int_reg_file[arch_to_log(proc, proc->cwp, PRIV_CLEANWIN)] =
	proc->phy_int_reg_file[proc->intmapper[arch_to_log(proc, proc->cwp,
							   PRIV_CLEANWIN)]] =
	proc->cleanwin;

      proc->log_int_reg_file[arch_to_log(proc, proc->cwp, PRIV_PSTATE)] =
	proc->phy_int_reg_file[proc->intmapper[arch_to_log(proc, proc->cwp,
							   PRIV_PSTATE)]] =
	proc->pstate;

      proc->log_int_reg_file[arch_to_log(proc, proc->cwp, PRIV_TL)] =
	proc->phy_int_reg_file[proc->intmapper[arch_to_log(proc, proc->cwp,
							   PRIV_TL)]] =
	proc->tl;

      proc->log_int_reg_file[arch_to_log(proc, proc->cwp, PRIV_PIL)] =
	proc->phy_int_reg_file[proc->intmapper[arch_to_log(proc, proc->cwp,
							   PRIV_PIL)]] =
	proc->pil;

      proc->log_int_reg_file[arch_to_log(proc, proc->cwp, PRIV_ITLB_RANDOM)] =
	proc->phy_int_reg_file[proc->intmapper[arch_to_log(proc, proc->cwp,
							   PRIV_ITLB_RANDOM)]] =
	proc->itlb_random;

      proc->log_int_reg_file[arch_to_log(proc, proc->cwp, PRIV_ITLB_WIRED)] =
	proc->phy_int_reg_file[proc->intmapper[arch_to_log(proc, proc->cwp,
							   PRIV_ITLB_WIRED)]] =
	proc->itlb_wired;

      proc->log_int_reg_file[arch_to_log(proc, proc->cwp, PRIV_DTLB_RANDOM)] =
	proc->phy_int_reg_file[proc->intmapper[arch_to_log(proc, proc->cwp,
							   PRIV_DTLB_RANDOM)]] =
	proc->dtlb_random;

      proc->log_int_reg_file[arch_to_log(proc, proc->cwp, PRIV_DTLB_WIRED)] =
	proc->phy_int_reg_file[proc->intmapper[arch_to_log(proc, proc->cwp,
							   PRIV_DTLB_WIRED)]] =
	proc->dtlb_wired;


      
      proc->phy_int_reg_file[proc->intmapper[inst->lrd]] =
        proc->log_int_reg_file[inst->lrd] =
        proc->phy_int_reg_file[proc->intmapper[inst->lrs1]];
      return 0;

      
      //-----------------------------------------------------------------------
    case iMULScc:
      fnMULScc_serialized(inst, proc);
      return 0;
 
      
      //-----------------------------------------------------------------------
    case iSMULcc:
      fnSMULcc_serialized(inst, proc);
      return 0;
      
 
      //-----------------------------------------------------------------------
    case iUMULcc:
      fnUMULcc_serialized(inst, proc);
      return 0;
 
      
      //-----------------------------------------------------------------------
    case iLDFSR:
 
      //-----------------------------------------------------------------------
    case iLDXFSR:
      set_fsr(proc, inst);
      return 0;
 
      
      //-----------------------------------------------------------------------
    case iSTFSR:                    // simply retry instruction, it will
    case iSTXFSR:                   // succeed as there are no FP ops ahead
      {
	proc->pc = inst->pc;
	proc->npc = inst->npc;
	return 1;
      } 
 
      //-----------------------------------------------------------------------
    case iSAVRESTD:
      {
        if (inst->code.aux1 == 0)  // SAVE
          {
            if ((proc->cansave != 0) && (inst->code.instruction == iSAVE))
              YS__logmsg(proc->proc_id / ARCH_cpus,
			 "Why did we have a SAVED with CANSAVE != 0 ?\n");
 
            proc->cansave++;
	    if (proc->otherwin == 0)
	      proc->canrestore--;
	    else
	      proc->otherwin--;

#ifdef COREFILE
            if (YS__Simtime > DEBUG_TIME)
              fprintf(corefile,
                      "SAVED makes CANSAVE %d, CANRESTORE %d, OTHERWIN %d, CLEANWIN %d\n",
                      proc->cansave,
                      proc->canrestore,
		      proc->otherwin,
		      proc->cleanwin);
#endif
            
          }
        else                        // RESTORE
          {
            proc->canrestore++;
	    if (proc->otherwin == 0)
	      proc->cansave--;
	    else
	      proc->otherwin--;

	    if (proc->cleanwin != NUM_WINS)
	      proc->cleanwin++;
	    
#ifdef COREFILE
            if (YS__Simtime > DEBUG_TIME)
              fprintf(corefile,
                      "RESTORED makes CANSAVE %d, CANRESTORE %d, OTHERWIN %d, CLEANWIN %d\n",
                      proc->cansave,
                      proc->canrestore,
		      proc->otherwin,
		      proc->cleanwin);
#endif
            
          }
      }
      break;
 
 
      //-----------------------------------------------------------------------
    case iDONERETRY:
      {
	int tt = proc->phy_int_reg_file[proc->intmapper[arch_to_log(proc,
								    proc->cwp,
								    PRIV_TT)]];
	
        // statistics: add cycle count and instruction count
        proc->cycles[tt] += (long long)YS__Simtime + proc->DELAY -
	  proc->start_cycle[tt];

        proc->graduated[tt] += proc->graduates - proc->start_graduated[tt];
	proc->start_graduated[tt] = 0;

        //---------------------------------------------------------------------
        // return from trap state

        if (inst->code.aux1 == 0)         // DONE
          {
	    proc->pc =
	      proc->phy_int_reg_file[proc->intmapper[arch_to_log(proc,
							proc->cwp,
							PRIV_TNPC)]];
            proc->npc =
	      proc->phy_int_reg_file[proc->intmapper[arch_to_log(proc,
							proc->cwp,
							PRIV_TNPC)]]+SIZE_OF_SPARC_INSTRUCTION;
          }
        else                               // RETRY
          {
	    proc->pc =
	      proc->phy_int_reg_file[proc->intmapper[arch_to_log(proc,
							proc->cwp,
							PRIV_TPC)]];
            proc->npc =
	      proc->phy_int_reg_file[proc->intmapper[arch_to_log(proc,
							proc->cwp,
							PRIV_TNPC)]];
          }

	
        // common operation ---------------------------------------------------
        // restore PState & CCR, decrement TL
	proc->pstate = 
	  proc->log_int_reg_file[arch_to_log(proc, proc->cwp,
						    PRIV_PSTATE)] =
          proc->phy_int_reg_file[proc->intmapper[arch_to_log(proc, proc->cwp,
						    PRIV_PSTATE)]] =
          proc->phy_int_reg_file[proc->intmapper[arch_to_log(proc,
						    proc->cwp,
						    PRIV_TSTATE)]] & 0x0000FFFF;

	proc->cwp =
	  proc->phy_int_reg_file[proc->intmapper[arch_to_log(proc,
						    proc->cwp,
						    PRIV_TSTATE)]] >> 16;
	proc->cwp &= 0x000000FF;

        proc->phy_int_reg_file[proc->intmapper[arch_to_log(proc, proc->cwp, COND_ICC)]] =
          proc->log_int_reg_file[arch_to_log(proc, proc->cwp, COND_ICC)] =
          proc->phy_int_reg_file[proc->intmapper[arch_to_log(proc, proc->cwp, PRIV_TSTATE)]] >> 24;
          

	proc->tl--;
        proc->log_int_reg_file[arch_to_log(proc, proc->cwp,
						  PRIV_TL)] --;
        proc->phy_int_reg_file[proc->intmapper[arch_to_log(proc, proc->cwp,
						  PRIV_TL)]] --;
 
        if (proc->tl < 0)
	  YS__errmsg(proc->proc_id / ARCH_cpus,
		     "DoneRetry arrives at TrapLevel %i at 0x%08X\n",
		     proc->tl, inst->pc);


      if (!PSTATE_GET_PRIV(proc->pstate))
	{
	  proc->start_graduated[OK] = proc->graduates;
	  proc->start_cycle[OK] = proc->curr_cycle;
	}

	
#ifdef TRACE
	if (YS__Simtime > TRACE)
	  {
	    YS__logmsg(proc->proc_id / ARCH_cpus,
		       "    [%i] Restore PC: 0x%X  NPC: 0x%X  PState: 0x%X  ICC: 0x%X\n",
		       proc->proc_id,
		       proc->pc,
		       proc->npc,
		       proc->pstate,
		       proc->phy_int_reg_file[proc->intmapper[arch_to_log(proc, proc->cwp, COND_ICC)]]);
 
	    YS__logmsg(proc->proc_id / ARCH_cpus,
		       "    [%i] CWP: %i CanSave: %i Canrestore: %i Otherwin: %i Cleanwin: %i\n",
		       proc->proc_id,
		       proc->cwp,
		       proc->cansave,
		       proc->canrestore,
		       proc->otherwin,
		       proc->cleanwin);
	  }
#endif
 
        return 1;
      }
      
 
      //-----------------------------------------------------------------------
    default:
      YS__logmsg(proc->proc_id / ARCH_cpus,
		 "Unexpected serialized instruction.\n");
      exit(-1);
      break;
    }
 
  return 0;
}