except.cc

ml-rsim 多处理器模拟器 支持类bsd操作系统

/*
 * Copyright (c) 2002 The Board of Trustees of the University of Illinois and
 *                    William Marsh Rice University
 * Copyright (c) 2002 The University of Utah
 * Copyright (c) 2002 The University of Notre Dame du Lac
 *
 * All rights reserved.
 *
 * Based on RSIM 1.0, developed by:
 *   Professor Sarita Adve's RSIM research group
 *   University of Illinois at Urbana-Champaign and
     William Marsh Rice University
 *   http://www.cs.uiuc.edu/rsim and http://www.ece.rice.edu/~rsim/dist.html
 * ML-RSIM/URSIM extensions by:
 *   The Impulse Research Group, University of Utah
 *   http://www.cs.utah.edu/impulse
 *   Lambert Schaelicke, University of Utah and University of Notre Dame du Lac
 *   http://www.cse.nd.edu/~lambert
 *   Mike Parker, University of Utah
 *   http://www.cs.utah.edu/~map
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal with the Software without restriction, including without
 * limitation the rights to use, copy, modify, merge, publish, distribute,
 * sublicense, and/or sell copies of the Software, and to permit persons to
 * whom the Software is furnished to do so, subject to the following
 * conditions:
 *
 * 1. Redistributions of source code must retain the above copyright notice,
 *    this list of conditions and the following disclaimers. 
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimers in the
 *    documentation and/or other materials provided with the distribution.
 * 3. Neither the names of Professor Sarita Adve's RSIM research group,
 *    the University of Illinois at Urbana-Champaign, William Marsh Rice
 *    University, nor the names of its contributors may be used to endorse
 *    or promote products derived from this Software without specific prior
 *    written permission. 
 * 4. Neither the names of the ML-RSIM project, the URSIM project, the
 *    Impulse research group, the University of Utah, the University of
 *    Notre Dame du Lac, nor the names of its contributors may be used to
 *    endorse or promote products derived from this software without specific
 *    prior written permission. 
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS WITH THE SOFTWARE. 
 */

#include <signal.h>
#include <unistd.h>
#include <sys/time.h>

extern "C"
{
#include "sim_main/simsys.h"
#include "Caches/ubuf.h"
}                    

#include "Processor/procstate.h"
#include "Processor/memunit.h"
#include "Processor/branchpred.h"
#include "Processor/traps.h"
#include "Processor/exec.h"
#include "Processor/mainsim.h"
#include "Processor/simio.h"
#include "Processor/fsr.h"
#include "Processor/multiprocessor.h"
#include "Processor/procstate.hh"
#include "Processor/fastnews.h"
#include "Processor/active.hh"
#include "Processor/tagcvt.hh"
#include "Processor/stallq.hh"
#include "Processor/memunit.hh"


static void SaveCPUState(instance *, ProcState *);
static int  ProcessSerializedInstruction(instance *, ProcState *);
static void FatalException(instance *, ProcState *);

#define FAULT_COUNT_MAX 1024
static int FaultCount = 0;


void PrintDataFault(instance *inst, ProcState *proc)
{
  YS__logmsg(proc->proc_id / ARCH_cpus,
	  "DATA FAULT [%i] %.0f PC: 0x%X  NPC: 0x%X  Addr: 0x%08X   PState: 0x%08X\n",
	  proc->proc_id,
	  YS__Simtime,
	  inst->pc,
	  inst->npc,
	  inst->addr,
	  proc->pstate);
  
  if (FaultCount++ > FAULT_COUNT_MAX)
    {
      FaultCount = 0;
      YS__logmsg(proc->proc_id / ARCH_cpus,
	      "Too many faults encountered - suspending process\n");
      YS__logmsg(proc->proc_id / ARCH_cpus,
		 "Resume simulation by sending SIGCONT (%i) to process %i\n",
		 SIGCONT, getpid());
      kill(getpid(), SIGSTOP);
    }
}



void PrintInstrFault(instance *inst, ProcState *proc)
{
  YS__logmsg(proc->proc_id / ARCH_cpus,
	     "INSTR FAULT [%i] %.0f PC: 0x%X  NPC: 0x%X  Addr: 0x%08X   PState: 0x%08X\n",
	     proc->proc_id,
	     YS__Simtime,
	     inst->pc,
	     inst->npc,
	     inst->pc,
	     proc->pstate);

  if (FaultCount++ > FAULT_COUNT_MAX)
    {
      FaultCount = 0;
      YS__logmsg(proc->proc_id / ARCH_cpus,
		 "Too many faults encountered - suspending process\n");
      YS__logmsg(proc->proc_id / ARCH_cpus,
		 "Resume simulation by sending SIGCONT (%i) to process %i\n",
		 SIGCONT, getpid());
      kill(getpid(), SIGSTOP);
    }
}


 
 
const char *enames[] =
{
  "OK               ",
  "Serialize Instr. ",
  "ITLB Miss        ",
  "unused - inline  ",
  "unused - inline  ",
  "unused - inline  ",
  "DTLB Miss        ",
  "unused - inline  ",
  "unused - inline  ",
  "unused - inline  ",
  "unused           ",
  "Privileged Instr.",
  "Instruction Fault",
  "Data Fault       ",
  "Bus Error        ",
  "Illegal Instr.   ",
  "Clean Window     ",
  "unused - inline  ",
  "unused - inline  ",
  "unused - inline  ",
  "Window Overflow  ",
  "unused - inline  ",
  "unused - inline  ",
  "unused - inline  ",
  "Window Underflow ",
  "unused - inline  ",
  "unused - inline  ",
  "unused - inline  ",
  "Soft: Limbo      ",
  "Soft: Coherency  ",
  "Soft: Replacement",
  "FP Disabled      ",
  "FP Error         ",
  "Div by Zero      ",
  "System Trap 00   ",
  "System Trap 01   ",
  "Simulator Trap   ",
  "System Trap 03   ",
  "System Trap 04   ",
  "System Trap 05   ",
  "System Trap 06   ",
  "System Trap 07   ",
  "System Trap 08   ",
  "System Trap 09   ",
  "System Trap 0A   ",
  "System Trap 0B   ",
  "System Trap 0C   ",
  "System Trap 0D   ",
  "System Trap 0E   ",
  "System Trap 0F   ",
  "System Trap 10   ",
  "System Trap 11   ",
  "System Trap 12   ",
  "System Trap 13   ",
  "System Trap 14   ",
  "System Trap 15   ",
  "System Trap 16   ",
  "System Trap 17   ",
  "System Trap 18   ",
  "System Trap 19   ",
  "System Trap 1A   ",
  "System Trap 1B   ",
  "System Trap 1C   ",
  "System Trap 1D   ",
  "System Trap 1E   ",
  "System Trap 1F   ",
  "System Trap 20   ",
  "System Trap 21   ",
  "System Trap 22   ",
  "System Trap 23   ",
  "System Trap 24   ",
  "System Trap 25   ",
  "System Trap 26   ",
  "System Trap 27   ",
  "System Trap 28   ",
  "System Trap 29   ",
  "System Trap 2A   ",
  "System Trap 2B   ",
  "System Trap 2C   ",
  "System Trap 2D   ",
  "System Trap 2E   ",
  "System Trap 2F   ",
  "Interrupt 0F     ",
  "Interrupt 0E     ",
  "Interrupt 0D     ",
  "Interrupt 0C     ",
  "Interrupt 0B     ",
  "Interrupt 0A     ",
  "Interrupt 09     ",
  "Interrupt 08     ",
  "Interrupt 07     ",
  "Interrupt 06     ",
  "Interrupt 05     ",
  "Interrupt 04     ",
  "Interrupt 03     ",
  "Interrupt 02     ",
  "Interrupt 01     ",
  "Interrupt 00     "
};


/*************************************************************************/
/* IsSoftException : returns true if exception code flags soft exception */
/*************************************************************************/
 
inline int IsSoftException(except code)
{
  return (code == SOFT_LIMBO) || (code==SOFT_SL_COHE) || (code==SOFT_SL_REPL);
}



/*************************************************************************/
/* PreExceptionHandler : Ensures precise exceptions on "hard" exceptions */
/*************************************************************************/

int PreExceptionHandler(instance * inst, ProcState * proc)
{
   proc->in_exception = inst;

  // "hard" exceptions -- that is, exceptions which trap to kernel
  // code (and which can thus possibly alter the TLB) have to at least
  // wait for all prior stores to at least _issue_. In addition, they have
  // to wait for any possible S-L constraint, since loads can go speculatively
  // and can cause exceptions detected later. Fortunately, the latter only
  // affects SC. "soft" exceptions don't have to wait for anything.

  if (IsSoftException(inst->exception_code) || proc->ReadyUnissuedStores == 0)
    {
      proc->in_exception = NULL;
      return ExceptionHandler(inst->tag, proc); // now we're for real!
    }
  else
    {
#ifdef COREFILE
      if (proc->curr_cycle > DEBUG_TIME)
        fprintf(corefile,
                "Processor %d in PreExceptionHandler; waiting for %d stores to i
ssue\n",
                proc->proc_id,
                proc->ReadyUnissuedStores);
#endif
      return -1;
    }
}




/*************************************************************************/
/* ExceptionHandler : Ensures preciseness of exceptions                  */
/*************************************************************************/
 
int ExceptionHandler(long long tag, ProcState * proc)
{
  unsigned int n, i, addr;
 
  /* We have got an exception at the tag value */
  instance *inst = TagCvtHead(tag, proc);
  instance icopy = *inst;
 
#ifndef NOSTAT
  if (!IsSoftException(inst->exception_code))
    StatrecUpdate(proc->in_except,
		  proc->curr_cycle-proc->time_pre_exception,
		  1);
#endif
  
  // At this point, all instructions before this instruction
  // have completed and all instructions after this have not
  // written back -- precise interrupts
 
  // There are certain things we do irrespective of the exception,
  // they are ...
 
  FlushBranchQ(tag, proc);
  tag = tag-1;        // because we should also kill the excepting instruction
 
  FlushMems(tag, proc);
    
  FlushStallQ(tag, proc);

  int fetch_flush;
  fetch_flush = proc->fetch_queue->NumItems();
  FlushFetchQ(proc);
 
  /* This will delete all entries in the DoneHeap */
 
  UnitSetup(proc, 1);
 
  /* WE HAVE TO FLUSH STALL BEFORE ACTIVE */

  int pre = proc->active_list.NumElements();
  FlushActiveList(tag, proc);
  int post = proc->active_list.NumElements();

  int flushed = fetch_flush > (pre - post) ? fetch_flush : pre - post;
  
  if (EXCEPT_FLUSHES_PER_CYCLE != 0)
    proc->DELAY = (flushed+EXCEPT_FLUSHES_PER_CYCLE-1) / EXCEPT_FLUSHES_PER_CYCLE;

#ifndef NOSTAT
  StatrecUpdate(proc->ExceptFlushed, pre-post, 1);
#endif


#ifdef COREFILE
  if (proc->curr_cycle > DEBUG_TIME)
    fprintf(corefile,
            "Tag %lld caused exception %d at time %d\n",
            icopy.tag,
            icopy.exception_code,
            proc->curr_cycle);
#endif
 
 
  
#ifdef COREFILE
  /* check to make sure that all busy bits are off */
  int bctr;
  for (bctr = 0; bctr < NO_OF_PHY_INT_REGS; bctr++)
    {
      if (proc->intregbusy[bctr])
        {
          YS__logmsg(proc->proc_id / ARCH_cpus,
		     "Busy bit #%d set at exception!\n", bctr);
          if (proc->curr_cycle > DEBUG_TIME)
            fprintf(corefile, "Busy bit #%d set at exception!\n", bctr);
        }
    }
 
  for (bctr = 0; bctr < NO_OF_PHY_FP_REGS; bctr++)
    {
      if (proc->fpregbusy[bctr])
        {
          YS__logmsg(proc->proc_id / ARCH_cpus, "FPBusy bit #%d set at exception!\n", bctr);
          if (proc->curr_cycle > DEBUG_TIME)
            fprintf(corefile, "FPBusy bit #%d set at exception!\n", bctr);
        }
    }
#endif

#ifdef TRACE
  if (YS__Simtime > TRACE)
    {
      YS__logmsg(proc->proc_id / ARCH_cpus,
		 "    [%i] %s ",
		 proc->proc_id,
		 enames[icopy.exception_code]);

      if (inst->unit_type == uMEM)
	if (IsStore(inst))
	  YS__logmsg(proc->proc_id / ARCH_cpus,
		     "\t%s\t[%08x]=%08x (R%02i)\n",
		     inames[inst->code.instruction],
		     inst->addr,
		     inst->rs1vali,
		     inst->code.rs1);
	else
	  YS__logmsg(proc->proc_id / ARCH_cpus,
		     "\t%s\t[%08x]=%08x (R%02i)\n",
		     inames[inst->code.instruction],
		     inst->addr,
		     inst->rdvali,
		     inst->code.rd);
      else
	YS__logmsg(proc->proc_id / ARCH_cpus,
		   "\t%s\tR%02i = %08x\n",
		   inames[inst->code.instruction],
		   inst->code.rd,
		   proc->log_int_reg_file[inst->lrd]);
  }
#endif

  proc->exceptions[icopy.exception_code]++;
 
 
  //---------------------------------------------------------------------------
  // Let us look at the type of exception first
  switch(icopy.exception_code)
    {
 
      // ----------------------------------------------------------------------
    case OK:
 
      /* No exception, we should not have come here */
      YS__logmsg(proc->proc_id / ARCH_cpus,
		 "ERROR -- P%d(%lld) @ %lld, exception flagged when none!\n",
		 proc->proc_id, icopy.tag, proc->curr_cycle);
 
#ifdef COREFILE
      fprintf(corefile, "ERROR, exception flagged when none!\n");
#endif
      exit(-1);
      return -1;
 
 
      // ----------------------------------------------------------------------
    case BUSERR:
      if (icopy.code.instruction == iCASA || icopy.code.instruction == iCASXA)
	addr = icopy.rs2vali;
      else if (icopy.code.aux1)
	addr = icopy.rs2vali + icopy.code.imm;
      else
	addr = icopy.rs2vali + icopy.rsccvali;
      
      proc->log_int_reg_file[arch_to_log(proc, proc->cwp,
						PRIV_TLB_BADADDR)] =
        proc->phy_int_reg_file[proc->intmapper[arch_to_log(proc, proc->cwp,
						  PRIV_TLB_BADADDR)]] = addr;
      break;

      
      // ----------------------------------------------------------------------
    case SERIALIZE:

      proc->reset_lists();

      proc->graduates++;
      proc->graduation_count++;

      if (ProcessSerializedInstruction(&icopy, proc))
        // if it returns non-zero, then it has set the PC as it desires
        {
        }
      else
        {
          proc->pc = icopy.npc; // don't restart the instruction separately
          proc->npc = proc->pc + SIZE_OF_SPARC_INSTRUCTION;
        }

      // statistics: add cycle count and instruction count
      proc->cycles[SERIALIZE] +=
        (long long)YS__Simtime + proc->DELAY - proc->start_cycle[SERIALIZE];
      proc->graduated[SERIALIZE] +=
        proc->graduates - proc->start_graduated[SERIALIZE];
      proc->start_graduated[SERIALIZE] = 0;

      if (!PSTATE_GET_PRIV(proc->pstate))
	{
	  proc->start_graduated[OK] = proc->graduates;
	  proc->start_cycle[OK] = proc->curr_cycle;
	}
      return(0);
      break;