predecode_instr.cc

ml-rsim 多处理器模拟器 支持类bsd操作系统

      /* immediate */
      in->aux1 = 1;
      in->imm = SE(Extract(undec,12,0),13);
    }
  else
    {
      in->aux1=0;
      in->rscc =Extract(undec,4,0);
    }

  return 1;
}

int amem_op2f(instr *in, unsigned undec)
{
  in->rd=Extract(undec,29,25);
  in->rd_regtype=REG_FP;
  in->rs2=Extract(undec,18,14);
  if (Extract(undec,13,13))
    {
      /* immediate */
      in->aux1 = 1;
      in->imm = SE(Extract(undec,12,0),13);
    }
  else
    {
      in->aux1=0;
      in->rscc =Extract(undec,4,0);
    }

  return 1;
}

int amem_op2fs(instr *in, unsigned undec)
{
  amem_op2f(in,undec);
  in->rd_regtype=REG_FPHALF;
  return 1;
}

int cas(instr *in, unsigned undec)
{
  in->rd=Extract(undec,29,25);
  in->rs1=Extract(undec,4,0);
  in->rs2=Extract(undec,18,14);

  in->rscc = in->rd;

  // NOTE: we currently do not support ASI's.
  int t = Extract(undec,12,5);

  return 1;
}

int swap(instr *in, unsigned undec)
{
  in->rd=Extract(undec,29,25);
  in->rs1=Extract(undec,29,25);
  in->rs2=Extract(undec,18,14);
  if (Extract(undec,13,13))
    {
      in->aux1 = 1;
      in->imm = SE(Extract(undec,12,0),13);
    }
  else
    {
      in->aux1=0;
      in->rscc =Extract(undec,4,0);
    }

  return 1;
}

int aswap(instr *in, unsigned undec)
{
  in->rd=Extract(undec,29,25);
  in->rs1=Extract(undec,29,25);
  in->rs2=Extract(undec,18,14);
  if (Extract(undec,13,13))
    {
      in->aux1 = 1;
      in->imm = SE(Extract(undec,12,0),13);
    }
  else
    {
      in->aux1=0;
      in->imm = Extract(undec,12,5);
      in->rscc =Extract(undec,4,0);
    }

  return 1;
}

int smem_op2(instr *in, unsigned undec)
{
  in->rs1=Extract(undec,29,25);
  in->rs2=Extract(undec,18,14);
  if (Extract(undec,13,13))
    {
      /* immediate */
      in->aux1 = 1;
      in->imm = SE(Extract(undec,12,0),13);
    }
  else
    {
      in->aux1=0;
      in->rscc =Extract(undec,4,0);
    }

  return 1;
}

int sdmem_op2(instr *in, unsigned undec)
{
  in->rs1=Extract(undec,29,25);
  in->rs1_regtype = REG_INTPAIR;
  in->rs2=Extract(undec,18,14);
  if (Extract(undec,13,13))
    {
      /* immediate */
      in->aux1 = 1;
      in->imm = SE(Extract(undec,12,0),13);
    }
  else
    {
      in->aux1=0;
      in->rscc =Extract(undec,4,0);
    }

  return 1;
}

int sdamem_op2(instr *in, unsigned undec)
{
  in->rs1=Extract(undec,29,25);
  in->rs1_regtype = REG_INTPAIR;
  in->rs2=Extract(undec,18,14);
  if (Extract(undec,13,13))
    {
      /* immediate */
      in->aux1 = 1;
      in->imm = SE(Extract(undec,12,0),13);
    }
  else
    {
      in->aux1=0;
      in->rscc =Extract(undec,4,0);
      switch(Extract(undec,12,5))
	{
	default:
	  // AN ERROR, if this is actually in the code (likely just a case statement)
	  break;
	} 
    }

  return 1;
}

int smem_op2f(instr *in, unsigned undec)
{
  in->rs1=Extract(undec,29,25);
  in->rs1_regtype=REG_FP;
  in->rs2=Extract(undec,18,14);
  if (Extract(undec,13,13))
    {
      /* immediate */
      in->aux1 = 1;
      in->imm = SE(Extract(undec,12,0),13);
    }
  else
    {
      in->aux1=0;
      in->rscc =Extract(undec,4,0);
    }

  return 1;
}

int smem_op2fsr(instr *in, unsigned undec)
{
  in->rs1 = 0;
  int fsr;
  fsr=Extract(undec,29,25); /* if 0: FSR -- if 1: XFSR */
  if (fsr == 0) // FSR
    {
      in->rs1_regtype=REG_FSR;
    }
  else if (fsr == 1)
    {
      in->rs1_regtype = REG_FSR;
      in->instruction = iSTXFSR; /* override default */
    }
  else
    {
      /* neither an FSR or XFSR ... just let it be */
    }
  in->rs2=Extract(undec,18,14);
  if (Extract(undec,13,13))
    {
      /* immediate */
      in->aux1 = 1;
      in->imm = SE(Extract(undec,12,0),13);
    }
  else
    {
      in->aux1=0;
      in->rscc =Extract(undec,4,0);
    }

  return 1;
}

int smem_op2fs(instr *in, unsigned undec)
{
  smem_op2f(in,undec);
  in->rs1_regtype=REG_FPHALF;
  return 1;
}

int samem_op2(instr *in, unsigned undec)
{
  in->rs1=Extract(undec,29,25);
  in->rs2=Extract(undec,18,14);
  if (Extract(undec,13,13))
    {
      /* immediate */
      in->aux1 = 1;
      in->imm = SE(Extract(undec,12,0),13);
    }
  else
    {
      in->aux1=0;
      in->rscc =Extract(undec,4,0);
      switch(Extract(undec,12,5))
	{
	  case ASI_RW_SETDEST:
	    // remote write set processor destination (WriteSend)
		in->instruction = iRWSD;
	    break;
	  case ASI_RW_WT_I:
	    // remote write WriteThrough integer
		in->instruction = iRWWT_I;
	    break;
	  case ASI_RW_WTI_I:
	    // remote write WriteThroughInv integer
		in->instruction = iRWWTI_I;
	    break;
	  case ASI_RW_WS_I:
	    // remote write WriteSend    integer
		in->instruction = iRWWS_I;
	    break;
	  case ASI_RW_WSI_I:
	    // remote write WriteSendInv integer
		in->instruction = iRWWT_I;
	    break;
	default:
	  // AN ERROR, if this is actually in the code (likely just a case statement)
	  break;
	}

    }

  return 1;
}

int samem_op2f(instr *in, unsigned undec)
{
  in->rs1=Extract(undec,29,25);
  in->rs1_regtype=REG_FP;
  in->rs2=Extract(undec,18,14);
  if (Extract(undec,13,13))
    {
      /* immediate */
      in->aux1 = 1;
      in->imm = SE(Extract(undec,12,0),13);
    }
  else
    {
      in->aux1=0;
      in->rscc =Extract(undec,4,0);
      switch(Extract(undec,12,5))
	{
	  case ASI_RW_WT_F:
	    // remote write WriteThrough double 
		in->instruction = iRWWT_F;
	    break;
	  case ASI_RW_WTI_F:
	    // remote write WriteThroughInv double
		in->instruction = iRWWTI_F;
	    break;
	  case ASI_RW_WS_F:
	    // remote write WriteSend double
		in->instruction = iRWWS_F;
	    break;
	  case ASI_RW_WSI_F:
	    // remote write WriteSendInv double
		in->instruction = iRWWT_F;
	    break;
	default:
	  // AN ERROR, if this is actually in the code (likely just a case statement)
	  break;
	}

    }

  return 1;
}

int samem_op2fs(instr *in, unsigned undec)
{
  samem_op2f(in,undec);
  in->rs1_regtype=REG_FPHALF;
  return 1;
}

int mem_res(instr *in, unsigned undec)
{
  /* fprintf(stderr,"Reserved memory instruction encountered\n");  */ /* may appear in case statements, etc. */

  return 1;
}

/* FOR GENERALITY OF IMPLEMENTATION, TREAT CONDITION CODES
   LIKE ANY OTHER LOGICAL REGISTERS */

int movcc(instr *in, unsigned undec)
{
  in->rs1=in->rd=Extract(undec,29,25);
  if ((in->aux1 = Extract(undec,13,13)))
    {
      in->imm=SE(Extract(undec,10,0),11);
    }
  else
    {
      in->rs2=Extract(undec,4,0);
    }
  in->aux2=Extract(undec,17,14);

  /* here rscc represents the condition code used */
  in->rscc=COND_REGISTERS+ 4*Extract(undec,18,18) + Extract(undec,12,11);
  return 1;
}

int fmovcc(instr *in, unsigned undec)
{
  in->rs1=in->rd=Extract(undec,29,25);
  in->rs2=Extract(undec,4,0);
  in->aux2=Extract(undec,17,14);

  /* here rscc represents the condition code used */
  in->rscc=COND_REGISTERS+ Extract(undec,13,11);
  in->rd_regtype =REG_FP;
  in->rs2_regtype =REG_FP;
  in->rs1_regtype =REG_FP;

  return 1;
}

int fmovccs(instr *in, unsigned undec)
{
  in->rs1=in->rd=Extract(undec,29,25);
  in->rs2=Extract(undec,4,0);
  in->aux2=Extract(undec,17,14);

  /* here rscc represents the condition code used */
  in->rscc=COND_REGISTERS+ Extract(undec,13,11);
  in->rd_regtype =REG_FPHALF;
  in->rs2_regtype =REG_FPHALF;
  in->rs1_regtype =REG_FPHALF;

  return 1;
}



int tcc(instr *in, unsigned undec)
{
  in->rs1=Extract(undec,18,14);
  if ((in->aux1 = Extract(undec,13,13)))
    {
      in->imm=Extract(undec,6,0);
    }
  else
    {
      in->rs2=Extract(undec,4,0);
    }
  in->aux2=Extract(undec,28,25);

  return 1;
}

int movr(instr *in, unsigned undec)
{
  in->rd=Extract(undec,29,25);
  in->rs1=Extract(undec,29,25);
  if ((in->aux1 = Extract(undec,13,13)))
    {
      in->imm=SE(Extract(undec,9,0),10);
    }
  else
    {
      in->rs2=Extract(undec,4,0);
    }
  in->aux2=Extract(undec,12,10);

  /* here rs1 represents the condition code used */
  in->rscc=Extract(undec,18,14);
  return 1;
}

int popc(instr *in, unsigned undec)
{
  in->rd=Extract(undec,29,25);
  if ((in->aux1=Extract(undec,13,13)))
    {
      in->imm=SE(Extract(undec,12,0),13);
    }
  else
    {
      in->rs2=Extract(undec,4,0);
    }

  return 1;
}

int savrestd(instr *in, unsigned undec)
{
  in->aux1 = Extract(undec,29,25);

  return 1;
}

int doneretry(instr *in, unsigned undec)
{
  in->aux1 = Extract(undec,29,25);
  in->sync = 1;
  
  return 1;
}

int impdep1(instr *in, unsigned undec)
{
  return 1;
}

int impdep2(instr *in, unsigned undec)
{
  /*   fprintf(stderr,"Imp-dep1 encountered\n"); */
  return 1;
}

static IMF starters[4]={branch_instr,call_instr,arith_instr,mem_instr};

int start_decode(instr *in, unsigned undec)
{
  return (*(starters[Extract(undec,31,30)]))(in, undec);
}



extern "C" int PredecodeBlock(unsigned pc, int nodeid, char *daddr, int num)
{
  int      n, rc;
  unsigned instruction, *paddr;
  instr   *in;

  paddr = (unsigned*)PageTables[nodeid]->lookup(pc);
  if (!paddr)
    return(0);
  
  in = (instr*)daddr;
  memset(in, 0, sizeof(instr) * num);

  for (n = 0; n < num; n++)
    {
      instruction = endian_swap(*paddr);
      if (!(*(starters[Extract(instruction, 31, 30)]))(in, instruction))
	{
	  YS__warnmsg(nodeid, "Predecode failed\n");
	  return(0);
	}

      paddr++;
      in++;
    }

  return(1);
}