predecode_instr.cc

ml-rsim 多处理器模拟器 支持类bsd操作系统

      in->aux1 = 1;
      in->imm = SE(Extract(undec,12,0),13);
    }
  else
    {
      in->aux1=0;
      in->rscc = Extract(undec,4,0);
    }

  return 1;
}



/********** JMPL, RETURN WILL BE MESSY FOR US BECAUSE IT USES NON-RELATIVE
  CONTROL TRANSFER!!!! THIS IS A BIG PROBLEM SINCE ALL "RET"s are
  actually "JMPL", as well as many "CALL"s ********/

int arith_shift(instr *in, unsigned undec)
{
  in->rd=Extract(undec,29,25);
  in->rs1=Extract(undec,18,14);

  switch (in->aux1 = Extract(undec,13,12))
    {
    case 3:
      /* extended */
      in->imm=Extract(undec,5,0);
      break;
    case 2:
      in->imm=Extract(undec,4,0);
      break;
    case 1:
    default:
      in->rs2=Extract(undec,4,0);
      break;
    }

  return 1;
}

int arith_spec1(instr *in, unsigned undec)
{
  /* NOTE: arith_spec1 can either be read of some state register or
     a MEMBAR. It's a MEMBAR if the register specified is #15.

     Here is the register mapping:
     rs1               register type
     0                 Y register (for old mul/div ops)
     1		       reserved
     2		       Condition Codes Reg (xcc/icc)
     3		       ASI reg
     4		       Tick register
     5		       PC
     6		       FP registers status register
     7-14	       ancillary state regs (reserved)
     15		       STBAR/MEMBAR
     16-31	       imp-dep
     */
     

  in->rd = Extract(undec,29,25);
  in->rs1 = STATE_REGISTERS + Extract(undec,18,14); /* this is all for read state register */

  if (in->rs1 == STATE_MEMBAR)
    {
      /* this is special... treat it as such */
      if (Extract(undec,13,13)) /* MEMBAR */
	{
	  in->aux2=Extract(undec,3,0);
	  in->aux1=Extract(undec,6,4);
	  /* Bits 6-4 includes "instruction issue barrier" (6),
	     "memory issue barrier" (5),
	     and "lookaside barrier" (4, prior stores must complete before
	     subsequent loads to same address can be initiated: so, no fwds
	     from memq, etc.) --
	     we currently only implement #5 (and only in RC) -- all these
	     cases are basically invisible to the user */

	  if (in->aux1 & MB_SYNC)
	    in->sync = 1;
	}
      else /* STBAR */
	{
	  in->aux2=8; /* STORE-STORE only */
	  in->aux1=0;
	}
    }
  else if (in->rs1 == STATE_CCR)
    {
      in->rs1 = COND_ICC; /* they're the same thing... */
    }
  
  return 1;
}

int arith_spec2(instr *in, unsigned undec)
{
  /* NOTE: arith_spec2 can either be write of some state register or
     a software-initiated reset.

     Here is the register mapping:
     rd                register type
     0                 Y register (for old mul/div ops)
     1		       reserved
     2		       Condition Codes Reg (xcc/icc)
     3		       ASI reg
     4,5	       Ancillary state registers (reserved)
     6		       FP registers status register
     7-14	       Ancillary state regs (reserved)
     15		       Software initiated reset
     16-31	       imp-dep
     */
     
  in->rd = STATE_REGISTERS + Extract(undec,29,25);  /* this is all for write state register */
  in->rs1 = Extract(undec,18,14);
  if (in->rd == STATE_CCR)
    {
      in->rd = COND_ICC; /* they're the same thing... */
    }
  if ((in->aux1 = Extract(undec,13,13)))
    {
      in->imm = SE(Extract(undec,12,0),13);
    }
  else
    {
      in->rs2 = Extract(undec,4,0);
    }

  /* we will implement the other specialties later.... */
  return 1;
}


int rdpr(instr *in, unsigned undec)
{
  /* fprintf(stderr,"rdpr encountered\n"); */
  in->rd = Extract(undec,29,25);
  in->rs1 = PRIV_REGISTERS + Extract(undec,18,14); /* this is all for read priv register */

  return 1;
}

int wrpr(instr *in, unsigned undec)
{
  /* fprintf(stderr,"wrpr encountered\n"); */
  in->rd = PRIV_REGISTERS + Extract(undec,29,25);
  in->rs1 = Extract(undec,18,14);
  if ((in->aux1 = Extract(undec,13,13)))
    {
      in->imm = SE(Extract(undec,12,0),13);
    }
  else
    {
      in->rs2 = Extract(undec,4,0);
    }

  return 1;
}

int flushw(instr *in, unsigned undec)
{
  in->rd   = 0;
  in->rs1  = 0;
  in->rs2  = 0;
  in->aux1 = 0;
  in->imm  = 0;
  in->wpchange = WPC_FLUSHW;
  return 1;
}

int fp_op1(instr *in, unsigned undec)
{
  IMF fp;
  int tmp=Extract(undec,13,5);
  fp=fpop1[tmp];
  in->instruction=ifpop1[tmp];
  return (*fp)(in,undec);
}

int fp_op2(instr *in, unsigned undec)
{
  IMF fp;
  int tmp = Extract(undec,13,5);  
  fp=fpop2[tmp];
  in->instruction=ifpop2[tmp];
  return (*fp)(in,undec);
}

int fp_3(instr *in, unsigned undec)
{
  in->rd =Extract(undec,29,25);
  in->rs1 = Extract(undec,18,14);
  in->rs2 = Extract(undec,4,0);
  in->rd_regtype =REG_FP;
  in->rs1_regtype =REG_FP;
  in->rs2_regtype =REG_FP;

  return 1;
}

int fp_3s(instr *in, unsigned undec)
{
  in->rd =Extract(undec,29,25);
  in->rs1 = Extract(undec,18,14);
  in->rs2 = Extract(undec,4,0);
  in->rd_regtype =REG_FPHALF;
  in->rs1_regtype =REG_FPHALF;
  in->rs2_regtype =REG_FPHALF;

  return 1;
}

int fp_3sd(instr *in, unsigned undec)
{
  in->rd =Extract(undec,29,25);
  in->rs1 = Extract(undec,18,14);
  in->rs2 = Extract(undec,4,0);
  in->rd_regtype =REG_FP;
  in->rs1_regtype =REG_FPHALF;
  in->rs2_regtype =REG_FPHALF;

  return 1;
}

int fmovrcc(instr *in, unsigned undec)
{
  in->rs1=in->rd =Extract(undec,29,25);
  in->rscc = Extract(undec,18,14);
  in->rs2 = Extract(undec,4,0);
  in->aux2 = Extract(undec,12,10);
  in->rd_regtype =REG_FP;
  in->rs2_regtype =REG_FP;
  in->rs1_regtype =REG_FP;

  return 1;
}

int fmovrccs(instr *in, unsigned undec)
{
  in->rs1=in->rd =Extract(undec,29,25);
  in->rscc = Extract(undec,18,14);
  in->rs2 = Extract(undec,4,0);
  in->aux2 = Extract(undec,12,10);
  in->rd_regtype =REG_FPHALF;
  in->rs2_regtype =REG_FPHALF;
  in->rs1_regtype =REG_FPHALF;

  return 1;
}

int fcmp(instr *in, unsigned undec)
{
  in->rd = COND_REGISTERS+Extract(undec,26,25);
  in->rs1 = Extract(undec,18,14);
  in->rs2 = Extract(undec,4,0);
  in->rs1_regtype =REG_FP;
  in->rs2_regtype =REG_FP;

  return 1;
}

int fcmps(instr *in, unsigned undec)
{
  in->rd = COND_REGISTERS+Extract(undec,26,25);
  in->rs1 = Extract(undec,18,14);
  in->rs2 = Extract(undec,4,0);
  in->rs1_regtype =REG_FPHALF;
  in->rs2_regtype =REG_FPHALF;

  return 1;
}

int fp_2(instr *in, unsigned undec)
{
  in->rd =Extract(undec,29,25);
  in->rs2 = Extract(undec,4,0);
  in->rd_regtype =REG_FP;
  in->rs2_regtype =REG_FP;

  return 1;
}

int fp_2s(instr *in, unsigned undec)
{
  in->rd =Extract(undec,29,25);
  in->rs2 = Extract(undec,4,0);
  in->rd_regtype =REG_FPHALF;
  in->rs2_regtype =REG_FPHALF;

  return 1;
}

int fp_2sd(instr *in, unsigned undec)
{
  in->rd =Extract(undec,29,25);
  in->rs2 = Extract(undec,4,0);
  in->rd_regtype =REG_FP;
  in->rs2_regtype =REG_FPHALF;

  return 1;
}

int fp_2ds(instr *in, unsigned undec)
{
  in->rd =Extract(undec,29,25);
  in->rs2 = Extract(undec,4,0);
  in->rd_regtype =REG_FPHALF;
  in->rs2_regtype =REG_FP;

  return 1;
}


int mem_instr(instr *in, unsigned undec)
{
  IMF fp;
  int tmp=Extract(undec,24,19);
  fp=memop3[tmp];
  in->instruction=imemop3[tmp];
  return (*fp)(in,undec);
}

int mem_op2(instr *in, unsigned undec)
{
  in->rd=Extract(undec,29,25);
  in->rs2=Extract(undec,18,14);
  if (Extract(undec,13,13))
    {
      /* immediate */
      in->aux1 = 1;
      in->imm = SE(Extract(undec,12,0),13);
    }
  else
    {
      in->aux1=0;
      in->rscc = Extract(undec,4,0);
    }

  return 1;
}

int dmem_op2(instr *in, unsigned undec)
{
  in->rd=Extract(undec,29,25);
  // in->rcc=in->rd+1;
  in->rd_regtype = REG_INTPAIR;
  in->rs2=Extract(undec,18,14);
  if (Extract(undec,13,13))
    {
      /* immediate */
      in->aux1 = 1;
      in->imm = SE(Extract(undec,12,0),13);
    }
  else
    {
      in->aux1=0;
      in->rscc =Extract(undec,4,0);
    }

  return 1;
}

int mem_op2f(instr *in, unsigned undec)
{
  in->rd=Extract(undec,29,25);
  in->rd_regtype=REG_FP;
  in->rs2=Extract(undec,18,14);
  if (Extract(undec,13,13))
    {
      /* immediate */
      in->aux1 = 1;
      in->imm = SE(Extract(undec,12,0),13);
    }
  else
    {
      in->aux1=0;
      in->rscc =Extract(undec,4,0);
    }

  return 1;
}

int mem_op2fsr(instr *in, unsigned undec)
{
  int fsr;
  in->rd = 0; /* no "basic" register used; only FSR */
  fsr=Extract(undec,29,25); /* if 0: FSR; if 1: XFSR */
  if (fsr == 0) // FSR
    {
      in->rd_regtype=REG_INT;
    }
  else if (fsr == 1)
    {
      in->rd_regtype = REG_INT64;
      in->instruction = iLDXFSR; /* override default */
    }
  else
    {
      /* neither an FSR or XFSR ... just let it be */
    }
  in->rs2=Extract(undec,18,14);
  if (Extract(undec,13,13))
    {
      /* immediate */
      in->aux1 = 1;
      in->imm = SE(Extract(undec,12,0),13);
    }
  else
    {
      in->aux1=0;
      in->rscc =Extract(undec,4,0);
    }

  return 1;
}

int mem_op2fs(instr *in, unsigned undec)
{
  mem_op2f(in,undec);
  in->rd_regtype=REG_FPHALF;
  return 1;
}

int pref(instr *in, unsigned undec)
{
  in->aux2=Extract(undec,29,25);
  in->rs2=Extract(undec,18,14);
  if (Extract(undec,13,13))
    {
      /* immediate */
      in->aux1 = 1;
      in->imm = SE(Extract(undec,12,0),13);
    }
  else
    {
      in->aux1=0;
      in->rscc =Extract(undec,4,0);
    }

  return 1;
}

int apref(instr *in, unsigned undec)
{
  in->aux2=Extract(undec,29,25);
  in->rs2=Extract(undec,18,14);
  if (Extract(undec,13,13))
    {
      /* immediate */
      in->aux1 = 1;
      in->imm = SE(Extract(undec,12,0),13);
    }
  else
    {
      in->aux1=0;
      in->rscc =Extract(undec,4,0);
      in->imm=Extract(undec,12,5);
    }

  return 1;
}

int amem_op2(instr *in, unsigned undec)
{
  in->rd=Extract(undec,29,25);
  in->rs2=Extract(undec,18,14);
  if (Extract(undec,13,13))
    {
      /* immediate */
      in->aux1 = 1;
      in->imm = SE(Extract(undec,12,0),13);
    }
  else
    {
      in->aux1=0;
      in->rscc =Extract(undec,4,0);
    }

  return 1;
}

int damem_op2(instr *in, unsigned undec)
{
  in->rd=Extract(undec,29,25);
  // in->rcc=in->rd+1;
  in->rd_regtype = REG_INTPAIR;
  in->rs2=Extract(undec,18,14);
  if (Extract(undec,13,13))
    {