predecode_table.cc

ml-rsim 多处理器模拟器 支持类bsd操作系统

/*
 * Copyright (c) 2002 The Board of Trustees of the University of Illinois and
 *                    William Marsh Rice University
 * Copyright (c) 2002 The University of Utah
 * Copyright (c) 2002 The University of Notre Dame du Lac
 *
 * All rights reserved.
 *
 * Based on RSIM 1.0, developed by:
 *   Professor Sarita Adve's RSIM research group
 *   University of Illinois at Urbana-Champaign and
     William Marsh Rice University
 *   http://www.cs.uiuc.edu/rsim and http://www.ece.rice.edu/~rsim/dist.html
 * ML-RSIM/URSIM extensions by:
 *   The Impulse Research Group, University of Utah
 *   http://www.cs.utah.edu/impulse
 *   Lambert Schaelicke, University of Utah and University of Notre Dame du Lac
 *   http://www.cse.nd.edu/~lambert
 *   Mike Parker, University of Utah
 *   http://www.cs.utah.edu/~map
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal with the Software without restriction, including without
 * limitation the rights to use, copy, modify, merge, publish, distribute,
 * sublicense, and/or sell copies of the Software, and to permit persons to
 * whom the Software is furnished to do so, subject to the following
 * conditions:
 *
 * 1. Redistributions of source code must retain the above copyright notice,
 *    this list of conditions and the following disclaimers. 
 * 2. Redistributions in binary form must reproduce the above copyright
 *    notice, this list of conditions and the following disclaimers in the
 *    documentation and/or other materials provided with the distribution.
 * 3. Neither the names of Professor Sarita Adve's RSIM research group,
 *    the University of Illinois at Urbana-Champaign, William Marsh Rice
 *    University, nor the names of its contributors may be used to endorse
 *    or promote products derived from this Software without specific prior
 *    written permission. 
 * 4. Neither the names of the ML-RSIM project, the URSIM project, the
 *    Impulse research group, the University of Utah, the University of
 *    Notre Dame du Lac, nor the names of its contributors may be used to
 *    endorse or promote products derived from this software without specific
 *    prior written permission. 
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
 * THE CONTRIBUTORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS WITH THE SOFTWARE. 
 */

/*
  predecode_table.cc

  Instruction table setup code for the predecode phase

  */


#include <stdio.h>

extern "C"
{
#include "sim_main/util.h"
}

#include "Processor/registers.h"
#include "Processor/instruction.h"
#include "Processor/funcs.h"
#include "Processor/funcunits.h"
#include "Processor/instance.h"
#include "Processor/procstate.h"



int SIZEOF_INSTR;



/* First are bits 31 and 30 */

IMF toplevelop[4];

IMF brop2[8];
INSTRUCTION ibrop2[8];

IMF arithop[64];
INSTRUCTION iarithop[64];

IMF fpop1[512];
INSTRUCTION ifpop1[512];

IMF fpop2[512];
INSTRUCTION ifpop2[512];

IMF memop3[64];
INSTRUCTION imemop3[64];


/* Now, within BRANCH, let's look at field op2,
   bits 24-22. We'll keep cond/rcond as a
   field in our instruction structure and
   do a case statement on that. */

/* within ARITH, look at op3, which is bits 24-19 */


/* Within FPop1, look at opf, bits 13-5 */

/* fill in the table with reserveds, then fill in these spaces separately */

/* Within FPop2, look at opf, bits 13-5 */

/* within MEM, look at op3, which is bits 24-19 */

void PredecodeTableSetup()
{
  int i;

  toplevelop[BRANCH]      = branch_instr;
  toplevelop[CALL]        = call_instr;
  toplevelop[ARITH]       = arith_instr;
  toplevelop[MEM]         = mem_instr;
  
  brop2[ILLTRAP]          = illtrap;
  ibrop2[ILLTRAP]         = iILLTRAP;
  
  brop2[BPcc]             = bpcc;
  ibrop2[BPcc]            = iBPcc;

  brop2[Bicc]             = bicc;
  ibrop2[Bicc]            = iBicc;

  brop2[BPr]              = bpr;
  ibrop2[BPr]             = iBPr;

  brop2[SETHI]            = sethi;
  ibrop2[SETHI]           = iSETHI;
 
  brop2[FBPfcc]           = fbpfcc;
  ibrop2[FBPfcc]          = iFBPfcc;
 
  brop2[FBfcc]            = fbfcc;
  ibrop2[FBfcc]           = iFBfcc;

  brop2[brRES]            = brres;
  ibrop2[brRES]           = iRESERVED;
  
  for (i = 0; i < 64; i++)
    {
      arithop[i]          = arith_res;
      iarithop[i]         = iRESERVED;
    }

  arithop[ADD]            = arith_3;
  iarithop[ADD]           = iADD;

  arithop[AND]            = arith_3;
  iarithop[AND]           = iAND;

  arithop[OR]             = arith_3;
  iarithop[OR]            = iOR;

  arithop[XOR]            = arith_3;
  iarithop[XOR]           = iXOR;

  arithop[SUB]            = arith_3;
  iarithop[SUB]           = iSUB;

  arithop[ANDN]           = arith_3;
  iarithop[ANDN]          = iANDN;

  arithop[ORN]            = arith_3;
  iarithop[ORN]           = iORN;

  arithop[XNOR]           = arith_3;
  iarithop[XNOR]          = iXNOR;

  arithop[ADDC]           = arith_3sc;
  iarithop[ADDC]          = iADDC;

  arithop[MULX]           = arith_3;
  iarithop[MULX]          = iMULX;

  arithop[UMUL]           = arith_3y;
  iarithop[UMUL]          = iUMUL;

  arithop[SMUL]           = arith_3y;
  iarithop[SMUL]          = iSMUL;

  arithop[SUBC]           = arith_3sc;
  iarithop[SUBC]          = iSUBC;

  arithop[UDIVX]          = arith_3;
  iarithop[UDIVX]         = iUDIVX;

  arithop[UDIV]           = arith_3y;
  iarithop[UDIV]          = iUDIV;

  arithop[SDIV]           = arith_3y;
  iarithop[SDIV]          = iSDIV;

  
  arithop[ADDcc]          = arith_3cc;
  iarithop[ADDcc]         = iADDcc;

  arithop[ANDcc]          = arith_3cc;
  iarithop[ANDcc]         = iANDcc;

  arithop[ORcc]           = arith_3cc;
  iarithop[ORcc]          = iORcc;

  arithop[XORcc]          = arith_3cc;
  iarithop[XORcc]         = iXORcc;

  arithop[SUBcc]          = arith_3cc;
  iarithop[SUBcc]         = iSUBcc;

  arithop[ANDNcc]         = arith_3cc;
  iarithop[ANDNcc]        = iANDNcc;
 
  arithop[ORNcc]          = arith_3cc;
  iarithop[ORNcc]         = iORNcc;

  arithop[XNORcc]         = arith_3cc;
  iarithop[XNORcc]        = iXNORcc;

  arithop[ADDCcc]         = arith_3sccc;
  iarithop[ADDCcc]        = iADDCcc;

  
  arithop[arithRES1]      = arith_res;
  
  arithop[UMULcc]         = arith_3y;
  iarithop[UMULcc]        = iUMULcc;

  arithop[SMULcc]         = arith_3y;
  iarithop[SMULcc]        = iSMULcc;

  arithop[SUBCcc]         = arith_3sccc;
  iarithop[SUBCcc]        = iSUBCcc;

  
  arithop[arithRES2]      = arith_res;

  arithop[UDIVcc]         = arith_3y;
  iarithop[UDIVcc]        = iUDIVcc;

  arithop[SDIVcc]         = arith_3y;
  iarithop[SDIVcc]        = iSDIVcc;

  
  arithop[TADDcc]         = arith_3cc;
  iarithop[TADDcc]        = iTADDcc;

  arithop[TSUBcc]         = arith_3cc;
  iarithop[TSUBcc]        = iTSUBcc;

  arithop[TADDccTV]       = arith_3cc;
  iarithop[TADDccTV]      = iTADDccTV;

  arithop[TSUBccTV]       = arith_3cc;
  iarithop[TSUBccTV]      = iTSUBccTV;

  arithop[MULScc]         = arith_3y;
  iarithop[MULScc]        = iMULScc;

  
  arithop[SLL]            = arith_shift;
  iarithop[SLL]           = iSLL;

  arithop[SRL]            = arith_shift;
  iarithop[SRL]           = iSRL;

  arithop[SRA]            = arith_shift;
  iarithop[SRA]           = iSRA;

  
  arithop[arithSPECIAL1]  = arith_spec1;/* includes RDY, RDCCR, etc */
  iarithop[arithSPECIAL1] = iarithSPECIAL1;

  arithop[arithRES3]      = arith_res;
  arithop[RDPR]           = rdpr;
  iarithop[RDPR]          = iRDPR;

  arithop[FLUSHW]         = flushw;
  iarithop[FLUSHW]        = iFLUSHW;

  arithop[MOVcc]          = movcc;
  iarithop[MOVcc]         = iMOVcc;

  arithop[SDIVX]          = arith_3;
  iarithop[SDIVX]         = iSDIVX;

  arithop[POPC]           = popc;
  iarithop[POPC]          = iPOPC;

  arithop[MOVR]           = movr;
  iarithop[MOVR]          = iMOVR;

  
  arithop[arithSPECIAL2]  = arith_spec2;/* includes WRY, etc */
  iarithop[arithSPECIAL2] = iarithSPECIAL2;

  arithop[SAVRESTD]       = savrestd;
  iarithop[SAVRESTD]      = iSAVRESTD;

  arithop[WRPR]           = wrpr;
  iarithop[WRPR]          = iWRPR;

  arithop[arithRES4]      = arith_res;
  arithop[FPop1]          = fp_op1;

  arithop[FPop2]          = fp_op2;

  arithop[IMPDEP1]        = impdep1;
  iarithop[IMPDEP1]       = iIMPDEP1;

  arithop[IMPDEP2]        = impdep2;
  iarithop[IMPDEP2]       = iIMPDEP2;

  
  arithop[JMPL]           = jmpl;
  iarithop[JMPL]          = iJMPL;

  arithop[RETURN]         = ret;
  iarithop[RETURN]        = iRETURN;

  arithop[Tcc]            = tcc;
  iarithop[Tcc]           = iTcc;

  arithop[FLUSH]          = flush;
  iarithop[FLUSH]         = iFLUSH;

  arithop[SAVE]           = sarith_3;
  iarithop[SAVE]          = iSAVE;

  arithop[RESTORE]        = rarith_3;
  iarithop[RESTORE]       = iRESTORE;

  arithop[DONERETRY]      = doneretry;
  iarithop[DONERETRY]     = iDONERETRY;

  arithop[arithRES5]      = arith_res;

  for (i = 0; i < 512; i++)
    {
      fpop1[i]            = arith_res;
      ifpop1[i]           = iRESERVED;
    }

  fpop1[FMOVs]            = fp_2s;
  ifpop1[FMOVs]           = iFMOVs;

  fpop1[FMOVd]            = fp_2;
  ifpop1[FMOVd]           = iFMOVd;

  fpop1[FMOVq]            = fp_2;
  ifpop1[FMOVq]           = iFMOVq;

  
  fpop1[FNEGs]            = fp_2s;
  ifpop1[FNEGs]           = iFNEGs;

  fpop1[FNEGd]            = fp_2;
  ifpop1[FNEGd]           = iFNEGd;

  fpop1[FNEGq]            = fp_2;
  ifpop1[FNEGq]           = iFNEGq;

  
  fpop1[FABSs]            = fp_2s;
  ifpop1[FABSs]           = iFABSs;

  fpop1[FABSd]            = fp_2;
  ifpop1[FABSd]           = iFABSd;

  fpop1[FABSq]            = fp_2;
  ifpop1[FABSq]           = iFABSq;

  
  fpop1[FSQRTs]           = fp_2s;
  ifpop1[FSQRTs]          = iFSQRTs;

  fpop1[FSQRTd]           = fp_2;
  ifpop1[FSQRTd]          = iFSQRTd;

  fpop1[FSQRTq]           = fp_2;
  ifpop1[FSQRTq]          = iFSQRTq;

  
  fpop1[FADDs]            = fp_3s;
  ifpop1[FADDs]           = iFADDs;

  fpop1[FADDd]            = fp_3;
  ifpop1[FADDd]           = iFADDd;

  fpop1[FADDq]            = fp_3;
  ifpop1[FADDq]           = iFADDq;

  
  fpop1[FSUBs]            = fp_3s;
  ifpop1[FSUBs]           = iFSUBs;

  fpop1[FSUBd]            = fp_3;
  ifpop1[FSUBd]           = iFSUBd;

  fpop1[FSUBq]            = fp_3;
  ifpop1[FSUBq]           = iFSUBq;

  
  fpop1[FMULs]            = fp_3s;
  ifpop1[FMULs]           = iFMULs;

  fpop1[FMULd]            = fp_3;
  ifpop1[FMULd]           = iFMULd;

  fpop1[FMULq]            = fp_3;
  ifpop1[FMULq]           = iFMULq;